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`Filing or 371 (C) Date:
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`Application Typc:
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`Group Art Unit:
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`First Named Inventor:
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`\\ \\ .2 .
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`09-26-2003
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`Utility
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`LEWIS, MONICA
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`2822
`9439
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`ELM-2 CONT. 4
`438/238
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`Glenn Leedyw, Saline, MI
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`Three dimensional multi layer memory and control logic
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`integrated circuit structure
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`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 223l3—l450
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`Sir:
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`RESPONSE
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`Rcsponsivc to the Office Action of 10/ 10/2008, plcasc amend this application as
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`follows.
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`MICRON ET AL. EXHIBIT 1028
`Page 1 of 13
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`IN THE CLAIMS
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`1-87. (Canceled)
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`88.
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`(Currently Amended) An integrated circuit structure comprising:
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`a first substrate comprising a first surface having interconnect contacts
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`formed thereon; and
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`a second substrate comprising a first surface having intcrconncct contacts
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`forrncd thereon; and
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`a thermal diffusion bond between the first surface of the second substrate
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`and the first surface of the first substrate that forms conductive paths between the
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`interconnect contacts of the first surfaces of the first and second substrates, wherein the
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`second substrate, the first
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`' the first
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`of the first surface of the first and-seeend--substrates-having-thesarrre--late-i=al——é%nie-nsieris.
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`89.
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`(Withdrawn) The apparatus of claim 88, wherein the second
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`substrate is one of a thinned monocrystalline semiconductor substrate and a thinned
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`polycrystalline semiconductor substrate.
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`90.
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`(Withdrawn) The apparatus of claim 88, wherein the circuitry
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`formed on the second substrate is one of active circuitry and passive circuitry.
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`91.
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`(Withdrawn) The apparatus of claim 88, wherein the circuitry
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`formed on the second substrate consists of both active circuitry and passive circuitry.
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`92.
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`(Withdrawn) The apparatus of claim 88, wherein the first substrate
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`is a substrate having circuitry formed thereon.
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`93.
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`(Withdrawn) The apparatus of claim 92, wherein the circuitry of
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`the first substrate is one of active circuitry and passive circuitry.
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`MICRON ET AL. EXHIBIT 1028
`Page 2 of 13
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`94.
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`(Withdrawn) The apparatus of claim 92, wherein the circuitry of
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`the first substrate comprises both active circuitry and passive circuitry.
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`95.
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`(Previously Presented) The structure of claim 88, further
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive paths formed between said first of said at least one additional
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`each additional thinned substrate and at least one of said substrates of the integrated
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`96.
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`(Withdrawn) The apparatus of claim 95, wherein at least two of the
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`first, the second and the at least one additional thinned substrates are formed using a
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`different process technology, wherein the different process technology is selected from
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`the group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and
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`Giant Magneto Resistance.
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`97.
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`(Withdrawn) The apparatus of claim 95, wherein at least one of the
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`first, the second and the at least one additional thinned substrates comprises a
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`microprocessor.
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`98.
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`(Withdrawn) The apparatus of claim 95, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`at least one substrate of the first, the second and the at least one additional
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`thinncd substrates has logic circuitry formcd thereon that performs tests on the at least
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`one substrate that has memory circuitry formed thereon.
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`99.
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`(Withdrawn) The apparatus of claim 95, wherein at least one
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`substrate of the first, the second and the at least one additional thinned substrates has
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`MICRON ET AL. EXHIBIT 1028
`Page 3 of 13
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`memory circuitry formed thereon, the memory circuitry having a plurality of memory
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`locations, wherein at least one memory location of the plurality of memory locations is
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`used for sparing and wherein data from the at least one memory location on the at least
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`one substrate having memory circuitry formed thereon is used instead of data from a
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`defective memory location on the at least one substrate that has memory circuitry formed
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`thereon.
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`100.
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`(Withdrawn) The apparatus of claim 95, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has logic circuitry formed thereon that performs programmable gate
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`line address assignment with respect to the at least one substrate having memory circuitry
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`l0l.
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`(Withdrawn) The apparatus of claim 95, further comprising a
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`plurality of interior Vertical interconnections that traverse at least one of the first, the
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`102.
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`(Withdrawn) The apparatus of claim 95, wherein information
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`processing is performed on data routed between the circuitry of at least two of the first,
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`103.
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`(Withdrawn) The apparatus of claim 95, wherein at least one of the
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`first, the second and the at least one additional thinned substrates has reconfiguration
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`circuitry.
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`lO4.
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`(Withdrawn) The apparatus of claim 95, wherein at least one of the
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`first, the second, and the at least one additional thinned substrates has logic circuitry
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`formed thereon for performing at least one function from the group consisting of: virtual
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`memory management, ECC, indirect addressing, content addressing, data compression,
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`data decompression, graphics acceleration, audio encoding, audio decoding, Video
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`MICRON ET AL. EXHIBIT 1028
`Page 4 of 13
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`encoding, video decoding, voice recognition, handwriting recognition, power
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`management and database processing.
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`105.
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`(Withdrawn) The apparatus of claim 95, further comprising:
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`a memory array having a plurality of memory storage cells, a plurality of
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`data lines, and a plurality of gate lines, each memory storage cell stores a data value and
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`has circuitry for coupling the data value to one of the plurality of data lines in response to
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`receiving a gate control signal from one of the plurality of gate lines;
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`circuitry that generates the gate control signal in response to receiving an
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`address, including means for mapping addresses to gate lines; and
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`a controller that determines if one of the plurality of memory cells is
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`defective and alters said mapping to remove references to the one of the plurality of
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`memory cells that is defective.
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`106.
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality of data lines and a plurality of gate lines on each memory
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data value and has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one of the plurality of gate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
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`address assignments for at least one gate line of the plurality of gate lines and wherein the
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`address assignments for determining which of the plurality of gate lines is selected for
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`each programmed address assignment; and
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`controller substrate logic that determines if one memory cell of the array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`lines to remove references to the gate line that causes the defective memory cell to couple
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`a data value to one of the plurality of data lines.
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`MICRON ET AL. EXHIBIT 1028
`Page 5 of 13
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`107.
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`(Previously Presented) The structure of claim 106, wherein the
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`controller substrate logic:
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`tests the array of memory cells periodically to determine if one of the
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`array of memory cells is defective; and
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality of data lines.
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`108.
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`(Previously Presented) The structure of claim 106, further
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`programmable logic to prevent the use of data values from the plurality of
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality of data lines.
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`109.
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`(Previously Presented) The structure of claim 106, wherein the
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`array of memory cells are arranged within physical space in a physical order and are
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`arranged within an address space in a logical order and wherein the physical order of at
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`least one memory cell is different than the logical order of the at least one memory cell.
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`110.
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`(Previously Presented) The structure of claim 106, wherein:
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`the logic circuitry of the at least one controller substrate is tested by an
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`external means; and
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
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`a functional testing of a substantial portion of the array of memory cells.
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`11].
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`(Previously Presented) The structure of claim 106, wherein the
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`logic circuitry of the at least one controller substrate performs functional testing of a
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`substantial portion of the array of memory cells.
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`l 12.
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`(Previously Presented) The structure of claim l06, wherein the
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`controller substrate logic is further configured to:
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`prevent the use of at least one defective gate line; and
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`MICRON ET AL. EXHIBIT 1028
`Page 6 of 13
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`113.
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`(Previously Presented) The structure of claim 106, wherein the
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`controller substrate logic is further configured to prevent the use of at least one defective
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`gate line.
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`114.
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`(Previously Presented) The structure of claim 106, wherein the
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`logic circuitry of the at least one controller substrate performs all functional testing of the
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`array of memory cells of the at least one memory substrate.
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`is a non—semiconductor material.
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`1 15.
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`(Withdrawn) The apparatus of claim 88, wherein the first substrate
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`116.
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`(Currently Amended) An integrated circuit structure comprising:
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`a flrst substrate having topside and bottomside surfaces, wherein the
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`topside surface of the flrst substrate has interconnect contacts formed thereon;
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`a second substrate having topside and bottomside surfaces, wherein the
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`bottomside surface of the second substrate has interconnect contacts formed thereon;
`a thermal diffusion bond between the bottomside surface of the second
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`substrate and the topside surface of the first substrate; and
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`conductive paths formed between the interconnect contacts on the topside
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`of the first substrate and on the bottorr1side of the second substrate, the conductive paths
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`providing electrical connections between the first substrate and the second substrate,
`wherein the first substrate is at least twice as thick as the second substrate the bottomside
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`surface of the second substrate overlap pine at least a inaorit ' of the to side surface of
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`117.
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`(Previously Presented) The integrated circuit structure of
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`claim 116, wherein selected ones of said interconnect contacts on said topside surface of
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`said first substrate are in electrical contact with selected ones of the interconnect contacts
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`MICRON ET AL. EXHIBIT 1028
`Page 7 of 13
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`on said bottomside surface of said second substrate so as to form said electrical
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`connections.
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`118.
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`(Currently Amended) An integrated circuit structure comprising:
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`a first substrate having a first and second surface;
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`a second substrate having a first and second surface, wherein said second
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`surfaces of the first and second substrates are opposite to said first surfaces;
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`a thermal compression bond between the first surface of the first substrate
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`and the first surface of the second substrate; and
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`conductive paths fomied on the first surfaces of the first and second
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`substrates, wl'1ereiii the first substrate is at least twice as tliick as the second substrate the
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`firs: surface of the second substrate overlat» in at least a maoritv of the first surface of
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`l 19.
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`(Previously Presented) The structure of claim l 16, further
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`comprisin g:
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive paths formed between said first of said at least one additional
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`thinned substrate and at least one of said first and second substrates and also between
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`each additional thinncd substrate and at least one of said substrates of thc integrated
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`circuit structure.
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`l20.
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`(Previously Presented) The structure of claim l 19, further
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`comprising:
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality of data lines and a plurality of gate lines on each memory
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`MICRON ET AL. EXHIBIT 1028
`Page 8 of 13
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`substrate;
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data value and has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one of the plurality of gate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
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`address assignments for at least one gate line of the plurality of gate lines and wherein the
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`address assignments for determining which of the plurality of gate lines is selected for
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`each programmed address assignment; and
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`controller substrate logic that determines if one memory cell of the array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`lines to remove references to the gate line that causes the defective memory cell to couple
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`a data value to one of the plurality of data lines.
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`l2l.
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`(Previously Presented) The structure of claim l20, wherein the
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`controller substrate logic:
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`tests the array of memory cells periodically to determine ifone ofthe
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`array of memory cells is defective; and
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality of data lines.
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`122.
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`(Previously Presented) The structure of claim l20, further
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`comprising:
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`programmable logic to prevent the use of data values from the plurality of
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality of data lines.
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`123.
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`(Previously Presented) The structure of claim 120, wherein the
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`array of memory cells are arranged within physical space in a physical order and are
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`arranged within an address space in a logical order and wherein the physical order of at
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`least one memory cell is different than the logical order of the at least one memory cell.
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`MICRON ET AL. EXHIBIT 1028
`Page 9 of 13
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`124.
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`(Previously Presented) The structure of claim 120, wherein:
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`the logic circuitry of the at least one controller substrate is tested by an
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`external means; and
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
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`a functional testing of a substantial portion of the array of memory cells.
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`125.
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`(Previously Presented) The structure of claim 120, wherein the
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`logic circuitry of the at least one controller substrate performs functional testing of a
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`substantial portion of the array of memory cells.
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`126.
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`(Previously Presented) The structure of claim 120, wherein the
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`controller substrate logic is further configured to:
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`prevent the use of at least one defective gate line; and
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`127.
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`(Previously Presented) The structure of claim 120, wherein the
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`controller substrate logic is further configured to prevent the use of at least one defective
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`gate line.
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`128.
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`(Previously Presented) The structure of claim 120, wherein the
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`logic circuitry of the at least one controller substrate performs all functional testing of the
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`array of memory cells of the at least one memory substrate.
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`MICRON ET AL. EXHIBIT 1028
`Page 10 of 13
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`REMARKS
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`The Office Action of 10/09/2008 has been carefully considered.
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`Claims 110 and 124 were indicated as containing allowable subject matter, which
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`indication is apprcciatively acknowledged.
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`Claims 88, 95 and 116-119 were rejected as being unpatentable over Sugiyama in
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`view ofLeedy. Claims 106-108, 111-114, 120-122 and 125-128 were rejected as being
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`unpatentable over the same base combination further in View of Faris and Sakui. Claims
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`109 and 123 were rejected as being unpatentable over the prior combination further in
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`view of Daberko. These rejections are respectfully traversed.
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`The claims have been amended for greater clarity. Reconsideration is respectfully
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`requested.
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`Rejection 0[ Claims 88, 95 and 116-119 as Ungatentable Over Sugiyama in View of
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`Leedy
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`The rejection of claim 88 states in part:
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`[S]ugiyama fails to disclose the following:
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`a) the second substrate is a thinned substrate having circuitry
`formed thereon.
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`However, Leedy discloses a thinned substrate (For Example: See column
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`5 Lines 62-68). It would have been obvious. . .to modify the semiconductor
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`device of Sugiyama to include a thinned substrate as disclosed in Leedy
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`because it aids in pr0vz'dI'ng a structural I'n.tegrz'zy (For Example: See
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`Column 5 Lines 62-68 and Column 6 Line 15,).
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`The foregoing “motivation” is specious; Applicant respectfully disagrees.
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`MICRON ET AL. EXHIBIT 1028
`Page 11 of 13
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`The concept of structural integrity arises in Leedy precisely because Leedy
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`pertains to thin integrated circuit structures, or “membranes,” having a thickness
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`dimension of less than 50 microns, for example, as compared to the typical thickness of
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`an IC wafer of 300-500 microns. That is, the IC membranes of Leedy are typically l0
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`times or more thinner than a typical IC wafer. Dielectric layer stresses can easily cause
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`such a thin membrane to fracture and disintegrate during attempted formation. The use of
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`low stress dielectric as described in Leedy provides for the structural integrity of such
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`thin membranes, allowing them to be successfully formed and used.
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`Sugiyama, of course, does not teach the use of a thinned substrate (Office Action,
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`page 2, final line). There is no indication in Sugiyama that the substrates are anything but
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`ordinary thickness (e.g., 300-500 microns). The structural integrity of substrates of such
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`ordinary thickness without the need of any further measures is well-established and
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`demonstrated. Hence, contrary to the rejection, Sugiyama has no need of the techniques
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`of Leedy for ensuring structural integrity of a thinned substrate or IC membrane. To
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`argue otherwise would be a classic instance of circular logic. The rejection therefore
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`cannot be maintained.
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`As no reasonable motivation has been identified for combining the teachings of
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`the references in the manner indicated, the cited references are not believed to teach or
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`suggest the invention of claim 88.
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`The same argument applies equally to claims 116 and 119.
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`Hence, it may be seen that the cited references does not teach or suggest the
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`invention of claims 88, 116 or 119.
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`The various combinations of references used to reject the dependent claims do
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`nothing to address the teachings absent from the base combination as noted above.
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`Therefore, the dependent claims are believed to be allowable as depending on an
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`MICRON ET AL. EXHIBIT 1028
`Page 12 of 13
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`Advisogg Action
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`The Advisory Action of 01/29/2009 attempts to bolster motivation for combining
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`the teachings of the references with the following statement:
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`[A] thinned substrate aids in providing structural integrity by smoothing
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`the surface. A smooth surface is provided on the substrate before a circuit
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`is placed on it.
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`This statement, unfortunately, only raises additional questions. In the case of Sugiyama,
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`circuits are fabricated on smooth surfaces of two different substrates, which are then
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`bonded face to face, bonding together opposing contacts. The surfaces are presumably
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`lapped and polished prior to circuit fabrication using conventional wafer manufacturing
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`techniques. Although this lapping and polishing does not produce a thinned substrate in
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`accordance with the terms of the claims as amended (i.e., a substrate that is half as thin or
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`less than another substrate to which it is to be bonded), it produces a surface of
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`comparable smoothness as the surfaces in Leedy, for example. Furthermore, the term
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`“structural integrity” is used in Leedy to refer to the ability of a structure to withstand
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`forces that would otherwise cause cracking or disintegration. If the term is used in that
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`same sense by the Examiner, then smoothness and structural integrity are unrelated.
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`Withdrawal of the rejections and allowance of claims 88, 95, 106-109, 111-114,
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`116-123 and 125-128 is respectfully requested.
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`Respectfully submitted,
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`/Michael J. Ure/
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`Michael J. Ure, Reg. 33,089
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`Dated: 2/16/2009
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`MICRON ET AL. EXHIBIT 1028
`Page 13 of 13
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