US008791581B2
`
`(12) United States Patent
`Leedy
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 8,791,581 B2
`*Jul. 29, 2014
`
`(54)
`
`(71)
`
`(72)
`
`THREE DIMENSIONAL STRUCTURE
`MEMORY
`
`Applicant: Glenn J Leedy, Carmel, CA (US)
`
`Inventor: Glenn J Leedy, Carmel, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`This patent is subject to a terminal dis
`claimer.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
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`1/1972 GroschwitZ
`(Continued)
`
`(21)
`
`(22)
`
`(65)
`
`(63)
`
`Appl. No.: 14/060,840
`
`Filed:
`
`Oct. 23, 2013
`
`Prior Publication Data
`
`US 2014/0043883 A1
`
`Feb. 13,2014
`
`Related US. Application Data
`
`Continuation of application No. 12/788,618, ?led on
`May 27, 2010, now Pat. No. 8,653,672, which is a
`continuation of application No. 10/143,200, ?led on
`May 13, 2002, now abandoned, which is a
`continuation of application No. 09/607,363, ?led on
`Jun. 30, 2000, now Pat. No. 6,632,706, which is a
`continuation of application No. 08/971,565, ?led on
`Nov. 17, 1997, now Pat. No. 6,133,640, which is a
`continuation of application No. 08/835,190, ?led on
`Apr. 4, 1997, now Pat. No. 5,915,167.
`
`(51)
`
`(52)
`
`(58)
`
`(2006.01)
`
`Int. Cl.
`H01L 23/48
`US. Cl.
`USPC .......... .. 257/777; 257/778; 257/685; 257/686
`Field of Classi?cation Search
`USPC ...... .. 365/51, 63, 72; 257/7774778, 6854686;
`438/455, 977, 1074108
`See application ?le for complete search history.
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`WO
`WO
`
`0531723
`9509438
`9641624
`
`3/1993
`4/1995
`12/1996
`
`OTHER PUBLICATIONS
`
`Interview Summary?led Oct. 16,2013 inU.S.Appl.N0. 13/734,874.
`(Continued)
`
`Primary Examiner * David Lam
`(74) Attorney, Agent, or Firm * Useful Arts IP
`
`ABSTRACT
`(57)
`A Three-Dimensional Structure (3DS) Memory allows for
`physical separation of the memory circuits and the control
`logic circuit onto different layers such that each layer may be
`separately optimized. One control logic circuit su?ices for
`several memory circuits, reducing cost. Fabrication of 3DS
`memory involves thinning of the memory circuit to less than
`50 microns in thickness and bonding the circuit to a circuit
`stack while still in wafer substrate form. Fine-grain high
`density inter-layer vertical bus connections are used. The 3DS
`memory manufacturing method enables several performance
`and physical size e?iciencies, and is implemented with estab
`lished semiconductor processing techniques.
`
`161 Claims, 9 Drawing Sheets
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`21191.
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`B B
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`B B
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`B B
`B
`B
`B
`B
`B
`B
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`B
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`B
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`BBBBB BB BBBBBB
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`BBBBB
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`MICRON ET AL. EXHIBIT 1001
`Page 1 of 33
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`

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`US 8,791,581 B2
`Page 2
`
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`MICRON ET AL. EXHIBIT 1001
`Page 2 of 33
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`

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`US 8,791,581 B2
`Page 3
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`
`>D>D>D>>>>>D>D>>m>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
`
`B2
`B2
`B1
`B2
`B2
`B2
`B2
`B2
`B2
`B1
`B2
`B2
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`11/1998
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`MICRON ET AL. EXHIBIT 1001
`Page 3 of 33
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`

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`US 8,791,581 B2
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`2/2009 Chen etal.
`7,504,732 B2
`3/2009 Leedy
`7,521,785 B2
`4/2009 Damberg etal.
`7,550,805 B2
`6/2009 Leedy
`7,615,837 B2 11/2009 Leedy
`7,670,893 B2
`3/2010 Leedy
`7,705,466 B2
`4/2010 Leedy
`7,736,948 B2
`6/2010 Dekkeretal.
`7,763,948 B2
`7/2010 Leedy
`7,820,469 B2 10/2010 Leedy
`7,911,012 B2
`3/2011 Leedy
`8,080,442 B2 12/2011 Leedy
`8,410,617 B2
`4/2013 Leedy
`2001/0002711 A1
`6/2001 Gonzalez
`2001/0014051 A1
`8/2001 Watanabe etal.
`2001/0025364 A1
`9/2001 Kaneko
`2001/0033030 A1 10/2001 Leedy
`2002/0117689 A1
`8/2002 Akimoto
`2002/0127775 A1
`9/2002 Haba et a1.
`{Biggayashi
`900% Leedy
`2003/0173608 A1
`2003/0184976 A1 10/2003 Brandenburg et 31,
`2003/0197253 A1 10/2003 Gannet a1.
`2003/0218182 A1 11/2003 Leedy
`
`2003/0223535 A1 12/2003 Leedy
`2004/0000708 A1
`1/2004 Rapport et al.
`2004/0021212 A1
`2/2004 Hamaguchietal.
`2004/0070063 A1
`4/2004 Leedy
`2004/0140547 A1
`7/2004 Yamazaki et al.
`2004/0197951 A1 10/2004 Leedy
`2004/0245617 A1 12/2004 Damberg etal.
`2005/0023656 A1
`2/2005 Leedy
`2005/0051841 A1
`3/2005 Leedy
`2005/0082641 A1
`4/2005 Leedy
`2006/0231927 A1 10/2006 Ohno
`2007/0035033 A1
`2/2007 OZgu-Z et al.
`2007/0176297 A1
`8/2007 Zohn1
`2008/0237591 A1 10/2008 Leedy
`2008/0254572 A1 10/2008 Leedy
`2008/0284611 A1 11/2008 Leedy
`2008/0302559 A1 12/2008 Leedy
`2009/0014897 A1
`1/2009 Ohno
`2009/0067210 A1
`3/2009 Leedy
`2009/0174082 A1
`7/2009 Leedy
`2009/0175104 A1
`7/2009 Leedy
`2009/0194768 A1
`8/2009 Leedy
`2009/0218700 A1
`9/2009 Leedy
`2009/0219742 A1
`9/2009 Leedy
`2009/0219743 A1
`9/2009 Leedy
`2009/0219744 A1
`9/2009 Leedy
`2009/0219772 A1
`9/2009 Leedy
`2009/0230501 A1
`9/2009 Leedy
`2010/0148371 A1
`6/2010 Kaskoun et a1.
`2010/0171224 A1
`7/2010 Leedy
`2010/0171225 A1
`7/2010 Leedy
`2010/0172197 A1
`7/2010 Leedy
`2010/0173453 A1
`7/2010 Leedy
`2011/0042829 A1
`2/2011 Kaskoun 6131.
`2011/0198672 A1* 8/2011 Leedy ......................... .. 257/211
`
`OTHER PUBLICATIONS
`Bollmannetal.,Three Dimensional Metallization forVerticallyInte
`grated Circuits, Materials for Advanced Metallization, 1997, Euro
`pean Workshop; Date of Conference: Mar. 16-19, 1997.
`
`* cited by examiner
`
`MICRON ET AL. EXHIBIT 1001
`Page 4 of 33
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`

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`US. Patent
`
`Jul. 29, 2014
`
`Sheet 1 0f9
`
`US 8,791,581 B2
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`MICRON ET AL. EXHIBIT 1001
`Page 5 of 33
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`

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`US. Patent
`
`Jul. 29, 2014
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`MICRON ET AL. EXHIBIT 1001
`Page 6 of 33
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`

`
`US. Patent
`
`Jul. 29, 2014
`
`Sheet 3 0f9
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`US 8,791,581 B2
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`MICRON ET AL. EXHIBIT 1001
`Page 7 of 33
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`

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`US. Patent
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`Jul. 29, 2014
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`MICRON ET AL. EXHIBIT 1001
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`U.S. Patent
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`Jul. 29, 2014
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`MICRON ET AL. EXHIBIT 1001
`Page 9 of 33
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`Jul. 29, 2014
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`MICRON ET AL. EXHIBIT 1001
`Page 10 of 33
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`US. Patent
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`Jul. 29, 2014
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`Sheet 7 0f9
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`US 8,791,581 B2
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`MICRON ET AL. EXHIBIT 1001
`Page 11 of 33
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`US. Patent
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`Jul. 29, 2014
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`US 8,791,581 B2
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`MICRON ET AL. EXHIBIT 1001
`Page 12 of 33
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`

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`US. Patent
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`Jul. 29, 2014
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`MICRON ET AL. EXHIBIT 1001
`Page 13 of 33
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`

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`US 8,791,581 B2
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`1
`THREE DIMENSIONAL STRUCTURE
`MEMORY
`
`BACKGROUND OF THE INVENTION
`
`2
`sense amp sensitivity in order to sense ever smaller memory
`cells while preventing the area used by the sense amp from
`becoming too large.
`If this design constraint or trade-off between control and
`memory circuits did not exist, the control circuitry could be
`made to perform numerous additional functions, such as sens
`ing multiple storage states per memory cell, faster memory
`access through larger more sensitive sense amps, caching,
`refresh, address translation, etc. But this trade-off is the
`physical and economic reality for memory ICs as they are
`presently made by all manufacturers.
`The capacity of DRAM circuits increases by a factor of
`four from one generation to the next; e.g. 1 bit, 4 bit, 16 Mbit
`and 64 Mbit DRAMs. This four times increase in circuit
`memory capacity per generation has resulted in larger and
`larger DRAM circuit areas. Upon introduction of a new
`DRAM generation the circuit yields are too low and, there
`fore, not cost effective for high volume manufacture. It is
`normally several years between the date prototype samples of
`a new DRAM generation are shown and the date such circuits
`are in volume production.
`Assembling die in a stacked or three dimensional (3D)
`manner is disclosed in US. Pat. No. 5,354,695 ofthe present
`inventor, incorporated herein by reference. Furthermore,
`assembling die in a 3D manner has been attempted with
`regard to memory. Texas Instruments of Dallas Tex., Irvine
`Sensors of Costa Mesa Calif. and Cubic Memory Corporation
`of Scotts Valley Calif. have all attempted to produce stacked
`or 3D DRAM products. In all three cases, conventional
`DRAM circuits in die form were stacked and the interconnect
`between each DRAM in the stack was formed along the
`outside surface of the circuit stack. These products have been
`available for the past several years and have proved to be too
`expensive for commercial applications, but have found some
`use in space and military applications due to their small
`physical size or footprint. The DRAM circuit type is referred
`to and often used as an example in this speci?cation, however,
`this invention is clearly not limited to the DRAM type of
`circuit. Undoubtedly memory cell types such as EEPROMs
`(Electrically Erasable Programmable Read Only Memories),
`?ash EPROM, Ferroelectric, GMR Giant Magneto Resis
`tance or combinations (intra or inter) of such memory cells
`can also be used with the present Three Dimensional Struc
`ture (3DS) methods to form 3DS memory devices.
`The present invention furthers, among others, the follow
`ing objectives:
`1. Several-fold lower fabrication cost per megabyte of
`memory than circuits conventionally made solely with mono
`lithic circuit integration methods.
`2. Several-fold higher performance than conventionally made
`memory circuits.
`3. Many-fold higher memory density per IC than convention
`ally made memory circuits.
`4. Greater designer control of circuit area size, and therefore,
`cost.
`5. Circuit dynamic and static self-test of memory cells by an
`internal controller.
`6. Dynamic error recovery and recon?guration.
`7. Multi-level storage per memory cell.
`8. Virtual address translation, address windowing, various
`address functions such as indirect addressing or content
`addressing, analog circuit functions and various graphics
`acceleration and microprocessor functions.
`
`SUMMARY OF THE INVENTION
`
`The present 3DS memory technology is a stacked or 3D
`circuit assembly technology. Features include:
`
`20
`
`25
`
`30
`
`35
`
`1. Field of the Invention
`The present invention relates to stacked integrated circuit
`memory.
`2. State of the Art
`Manufacturing methods for increasing the performance
`and decreasing the cost of electronic circuits, nearly without
`exception, are methods that increase the integration of the
`circuit and decrease its physical size per equivalent number of
`circuit devices such as transistors or capacitors. These meth
`ods have produced as of 1996 microprocessors capable of
`over 100 million operations per second that cost less than
`$1,000 and 64 Mbit DRAM circuits that access data in less
`than 50 ns and cost less than $50. The physical size of such
`circuits is less than 2 cm2. Such manufacturing methods
`support to a large degree the economic standard of living in
`the major industrialized countries and will most certainly
`continue to have signi?cant consequences in the daily lives of
`people all over the world.
`Circuit manufacturing methods take two primary forms:
`process integration and assembly integration. Historically the
`line between these two manufacturing disciplines has been
`clear, but recently with the rise in the use of MCMs (Multi
`Chip Modules) and ?ip-chip die attach, this clear separation
`may soon disappear. (The predominate use of the term Inte
`grated Circuit (IC) herein is in reference to an Integrated
`Circuit in singulated die form as sawed from a circuit sub
`strate such as s semiconductor wafer versus, for example, an
`Integrated Circuit in packaged form.) The majority of ICs
`when in initial die form are presently individually packaged,
`however, there is an increasing use of MCMs. Die in an MCM
`are normally attached to a circuit substrate in a planar fashion
`with conventional IC die I/O interconnect bonding methods
`such as wire bonding, DCA (Direct Chip Attach) or FCA
`40
`(Flip -Chip Attach).
`Integrated circuit memory such as DRAM, SRAM, ?ash
`EPROM, EEPROM, Ferroelectric, GMR (Giant MagnetoRe
`sistance), etc. have the common architectural or structural
`characteristic of being monolithic with the control circuitry
`integrated on the same die with the memory array circuitry.
`This established (standard or conventional) architecture or
`circuit layout structure creates a design trade-off constraint
`between control circuitry and memory array circuitry for
`large memory circuits. Reductions in the fabrication geom
`etries of memory cell circuitry has resulted in denser and
`denser memory ICs, however, these higher memory densities
`have resulted in more sophisticated control circuitry at the
`expense of increased area of the IC. Increased IC area means
`at least higher fabrication costs per IC (fewer ICs per wafer)
`and lower IC yields (fewer working ICs per wafer), and in the
`worst case, an IC design that cannot be manufactured due to
`its non-competitive cost or unreliable operation.
`As memory density increases and the individual memory
`cell size decreases more control circuitry is required. The
`control circuitry of a memory IC as a percentage of IC area in
`some cases such as DRAMs approaches or exceeds 40%. One
`portion of the control circuitry is the sense amp which senses
`the state, potential or charge of a memory cell in the memory
`array circuitry during a read operation. The sense amp cir
`cuitry is a signi?cant portion of the control circuitry and it is
`a constant challenge to the IC memory designer to improve
`
`45
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`50
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`MICRON ET AL. EXHIBIT 1001
`Page 14 of 33
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`US 8,791,581 B2
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`3
`1. Physical separation of the memory circuits and the control
`logic circuit onto different layers;
`2. The use of one control logic circuit for several memory
`circuits; 3 Thinning of the memory circuit to less than about
`50 microns in thickness forming a substantially ?exible sub
`strate with planar processed bond surfaces and bonding the
`circuit to the circuit stack while still in wafer substrate form;
`and
`4. The use of ?ne-grain high density inter layer vertical bus
`connections.
`The 3DS memory manufacturing method enables several
`performance and physical size ef?ciencies, and is imple
`mented with established semiconductor processing tech
`niques. Using the DRAM circuit as an example, a 64 Mbit
`DRAM made with a 0.25 microns process could have a die
`size of 84 m2, a memory area to die size ratio of 40% and a
`access time of about 50 ns for 8 Mbytes of storage; a 3DS
`DRAM IC made with the same 0.25 microns process would
`have a die size of 18.6 mm2, use 17 DRAM array circuit
`layers, a memory area to die size ratio of 94.4% and an
`expected access time of less than 10 ns for 64 Mbytes of
`storage. The 3DS DRAM IC manufacturing method repre
`sents a scalable, many-foldreduction in the cost per megabyte
`versus that of conventional DRAM IC manufacturing meth
`ods. In other words, the 3DS memory manufacturing method
`represents, at the infrastructure level, a fundamental cost sav
`ings that is independent of the process fabrication technology
`used.
`
`20
`
`25
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`30
`
`The present invention may be further understood from the
`following description in conjunction with the appended
`drawing. In the drawing:
`FIG. 1a is a pictorial view of a 3DS DRAM IC manufac
`tured with Method A or Method B and demonstrating the
`same physical appearance of I/ O bond pads as a conventional
`IC die;
`FIG. 1b is a cross-sectional view of a 3DS memory IC
`showing the metal bonding interconnect between several
`thinned circuit layers;
`FIG. lc is a pictorial view of a 3DS DRAM IC stack
`bonded and interconnected face-down onto a larger conven
`tional IC or another 3DS IC;
`FIG. 2a is a diagram showing the physical layout of a 3DS
`DRAM array circuit block with one data-line set of bus lines,
`i.e. one port;
`FIG. 2b is a diagram showing the physical layout of a 3DS
`DRAM array circuit block with two sets of data-line bus lines,
`i.e. two ports;
`FIG. 20 is a diagram showing the physical layout of a
`portion of an exemplary memory controller circuit;
`FIG. 3 is a diagram showing the physical layout of a 3DS
`DRAM array circuit showing partitions for sixty-four (64)
`3DS DRAM array blocks;
`FIG. 4 is a cross-sectional view of a generic 3DS vertical
`interconnection or feed-through in a thinned substrate;
`FIG. 5 is a diagram showing the layout of a 3DS memory
`multiplexer for down-selecting gate-line read or write selec
`tion.
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Referring to FIG. 1a and FIG. 1b, the 3DS (Three Dimen
`sional Structure) memory device 100 is a stack of integrated
`circuit layers with ?ne-grain vertical interconnect between all
`
`65
`
`4
`circuit layers. The term ?ne-grain inter-layer vertical inter
`connect is used to mean electrical conductors that pass
`through a circuit layer with or without an intervening device
`element and have a pitch of nominally less than 100 microns
`and more typically less than 10 microns, but not limited to a
`pitch of less than 2 microns, as best seen in FIG. 2a and FIG.
`2b. The ?ne-grain inter-layer vertical interconnect also func
`tions to bond together the various circuit layers. As shown in
`FIG. 1b, although the bond and interconnect layers 105a,
`105b, etc., are preferably metal, other material may also be
`used as described more fully hereinafter.
`The pattern 107a, 107b, etc. in the bond and interconnect
`layers 105a, 105b, etc. de?nes the vertical interconnect con
`tacts between the integrated circuit layers and serves to elec
`trically isolate these contacts from each other and the remain
`ing bond material; this pattern takes the form of either voids
`or dielectric ?lled spaces in the bond layers.
`The 3DS memory stack is typically organized as a control
`ler circuit 101 and some number of memory array circuit
`layers 103, typically between nine (9) and thirty-two (32), but
`there is no particular limit to the number of layers. The con
`troller circuit is of nominal circuit thickness (typically 0.5
`mm or greater), but each memory array circuit layer is a
`thinned and substantially ?exible circuit with net low stress,
`less than 50 microns and typically less than 10 microns in
`thickness. Conventional I/O bond pads are formed on a ?nal
`memory array circuit layer for use with conventional pack
`aging methods. Other metal patterns may be used such as
`insertion interconnection (disclosed in US. Pat. Nos. 5,323,
`035 and 5,453,404 of the present inventor), DCA (Direct Chip
`Attach) or FCA (Flip-Chip Attach) methods.
`Further, the ?ne grain inter-layer vertical interconnect can
`be used for direct singulated die bonding between a 3DS
`memory die and a conventional die (wherein the conventional
`die could be the controller circuit as shown in FIG. lc) or a
`3DS memory die and another 3DS memory die; it should be
`assumed that the areas (sizes) of the respective dice to be
`bonded together can vary and need not be the same. Referring
`more particularly to FIG. lc, a 3DS DRAM IC stack 100 is
`bonded and interconnected face-down onto a larger conven
`tional IC or another 3DS IC 107. Optionally the 3DS stack
`100 can be composed of only DRAM array circuits with the
`DRAM controller circuitry as part of the larger die. If the
`DRAM controller circuitry is part of the larger die, then
`?ne-grain vertical bus interconnect would be required (at the
`face 109 of the 3DS DRAM IC stack 100) to connect the 3DS
`DRAM array circuit to the DRAM controller, otherwise
`larger grain conventional interconnection could be incorpo
`rated (patterned) into the planarized bond layer.
`As shown in FIG. 3, each memory array circuit layer
`includes a memory array circuit 300 composed of memory
`array blocks 301 (nominally less than 5 mm2 in area) and each
`block is composed of memory cells (in much the same man
`ner as the cell array of a DRAM or EEPROM circuit), busing
`electrodes, andiat the option of the designer4enabling
`gates for selection of speci?c rows or columns of the memory
`array. The controller circuit is composed of sense amps,
`address, control and drive logic that would normally be found
`at the periphery of a typical memory circuit of monolithic
`design such as in a conventional DRAM.
`Fine-grain busing vertically connects the controller inde
`pendently to each memory array layer such that the controller
`can provide drive (power) or enable signals to any one layer
`without affecting the state of any of the other layers. This
`allows the controller to test, read or write independently each
`of the memory circuit layers.
`
`MICRON ET AL. EXHIBIT 1001
`Page 15 of 33
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`

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`US 8,791,581 B2
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`5
`FIG. 2a and FIG. 2b show examples of layouts of possible
`blocks of a memory array such as the block 301 of FIG. 3.
`Although only a portion of the block is shown, in the illus
`trated embodiment, the blocks exhibit bilateral symmetry
`such that the layout of the complete block may be ascertained
`from the illustrated portion. Abbreviations “T”, “L”, and
`“TL” are used following various reference numerals to indi
`cate “Top”, “Left” and “Top-Left,” respectively, implying
`corresponding elements not shown in the ?gure. Referring to
`FIG. 2a, a core portion 200 of the block is composed of a
`“sea” of memory cells. Logically, the aggregation of memory
`cells may be subdivided into “macrocells” 201 each cont