Elm Exhibit 2146
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00703
`
`

`
`SILICON PROCESSING
`
`FOR
`
`THE VLSI ERA
`
`VOLUME
`
`PROCESS iNTEGRATION
`
`

`
`SILICON PROCESSING
`
`FOR
`
`THE VLSI ERA
`
`VOLUME
`
`PROCESS INTEGRATION
`
`STANLEY WOLF Ph.D
`Professor Department of Electrical Engineering
`California State University Long Beach
`Long Beach California
`
`LATTICE PRESS
`
`Sunset Beach California
`
`

`
`DISCLAIMER
`
`This publication is based on sources and information believed to be reliable but
`the
`authors and Lattice Press disclaim any warranty or liability based on or relating to the
`contents of this publication
`
`Published by
`
`Lattice Press
`Post Office Box 340
`Sunset Beach California 90742 U.S.A
`
`Cover design by Roy Montibon Visionary Art Resources
`
`Inc Santa Ana CA
`
`1990 by Lattice Press
`Copyright
`All rights reserved No part of this book may be reproduced
`or transmitted in any form
`or mechanical
`or by any means electronic
`including photocopying recording or by any
`information storage and retrieval system without written permission
`from the publisher
`review
`for the inclusion of brief quotations
`in
`except
`
`Library of Congress Cataloging
`Wolf Stanley
`
`in Publication Data
`
`Silicon Processing for the VLSI Era
`Volume
`Process
`
`Integration
`
`Includes Index
`
`Integrated circuits-Very large scale
`
`integration
`
`Silicon
`
`Title
`
`86-081923
`
`ISBN 0-961672-4-5
`
`9876
`
`PRINTED IN THE UNITED STATES OF AMERICA
`
`

`
`To my wife Carrol Ann
`and my children Jennifer Laura and Stanley Charles Ross
`
`

`
`CONTENTS
`
`PREFACE
`
`CHAP
`PROCESS INTEGRATION FOR
`VLSI AND ULSI
`
`1.1 PROCESS INTEGRATION
`
`1.1.1 Process Sequence Used to Fabricate an
`Integrated-Circuit MOS Capacitor
`Process Sequence
`1.1.2 Specifying
`Levels of Process Integration Tasks
`1.1.3
`
`1.2
`
`AND
`PROCESS-DEVELOPMENT
`ISSUES
`PROCESS-INTEGRATION
`
`REFERENCES
`
`11
`
`CHAP
`
`ISOLATION TECHNOLOGIES FOR
`INTEGRATED CIRCUITS
`
`12
`
`2.1 BASIC ISOLATION PROCESSES FOR BIPOLAR ICs
`
`13
`
`2.1.1 Junction Isolation
`13
`Isolation in the SBC Process
`
`2.1.1.1 Junction
`
`2.1.1.2 Collector-Diffusion
`
`Isolation
`
`PROCESS FOR MOS ICs
`2.2 BASIC ISOLATION
`LOCOS ISOLATION
`17
`
`2.2.1 Punchthrough Prevention
`Circuits 20
`2.2.2 Details of the Semirecessed Oxide LOCOS Process
`2.2.2.1 Pad-Oxide Layer
`2.2.2.2 CVD of Silicon Nitride Layer
`2.2.2.3 Mask and Etch Pad-Oxide/Nitride
`
`between Adjacent Devices in MOS
`
`20
`
`Regions
`
`vii
`
`Layer
`
`to Define Active
`
`

`
`viii
`
`CONTENTS
`
`2.2.2.4 Channel-Stop Implant
`2.2.2.5 Problems Arising from the Channel-Stop Implants
`2.2.2.6 Grow Field Oxide
`
`2.2.2.7 Strip the Masking Nitride/Pad-Oxide
`Layer
`2.2 2.8 Regrow Sacrificial Pad Oxide and Strip Kooi Effect
`of Conventional Semi-Recessed Oxide LOGOS for
`2.2.3 Limitations
`27
`
`Small-Geometry
`
`IGs
`
`2.3 FULLY RECESSED OXIDE
`
`LOCOS PROCESSES
`
`28
`
`Modeling the LOGOS Process
`
`31
`
`ADVANCED
`PROCESSES
`
`SEMIRECESSED OXIDE LOCOS ISOLATION
`31
`
`31
`
`LOGOS
`Etched-Back
`Polybuffered LOGOS
`32
`SILO Sealed-Interface Local Oxidation 33
`Laterally Sealed LOGOS Isolation
`35
`in LOGOS by Mask-Stack Engineering
`Birds Beak Suppression
`Planarized SILO with High-Energy Channel-Stop
`Implant 38
`
`38
`
`ADVANCED
`PROCESSES
`
`FULLY RECESSED OXIDE
`39
`
`LOCOS ISOLATION
`
`SWAMI Sidewall-Masked Isolation Technique
`39
`2.5.2 SPOT Self-Aligned Planar-Oxidation Technology
`FUROX Fully Recessed Oxide 41
`2.5.4 OSELO II
`43
`
`41
`
`TECHNOLOGIES
`NON-LOCOS ISOLATION
`TRENCH ETCH AND REFILL
`45
`
`and Refill
`2.6.1 Shallow Trench
`BOX Isolation
`to Improve BOX Isolation
`Isolation 48
`and Refill
`Trench
`
`2.6.1.1
`
`2.6.1.2 Modifications
`
`2.6.2 Moderate-Depth
`
`Isolation 45
`
`2.6.2.1
`
`U-Groove
`
`Isolation
`
`2.6.2.2
`
`Isolation for CMOS
`
`Toshiba Moderate-Depth Trench
`and Refill
`2.6.3 Deep Narrow Trench
`51
`Ion Etching of the Substrate
`
`2.6.3.1
`
`Reactive
`
`2.6.3.2
`
`Refilling
`
`the Trench
`
`2.6.3.3 Planarization after Refill
`
`

`
`CONTENTS
`
`ix
`
`2.7 NON-LOCOS ISOLATION
`TECHNOLOGIES
`SEG
`EPITAXIAL GROWTH
`58
`
`II SELECTIVE
`
`2.7.1 Refill by SEG of Windows Cut into Surface Oxide
`59
`Deposition SSPD 60
`2.7.2 Simultaneous
`Single-Crystal/Poly
`and Refilling with SEG to Form Active
`2.7.3 Etching of Silicon Trenches
`Device Regions
`61
`Field Oxidation SELFOX 61
`2.7.4 Selective-Epitaxial-Layer
`2.7.5 SEG Refill of Trenches as an Alternative to Poly Refill
`2.7.6 Epitaxial Lateral Overgrowth ELO 62
`
`62
`
`NON-LOCOS
`2.8 MISCELLANEOUS
`ISOLATION TECHNOLOGIES
`
`63
`
`2.8.1 Field-Shield
`
`Isolation
`2.8.2 Buried Insulator between Source/Drain
`
`63
`
`Polysilicon BIPS 64
`
`2.9 SUMMARY CANDIDATE ISOLATION
`SUBMICRON DEVICES
`65
`
`TECHNOLOGIES FOR
`
`of VLSI and ULSI
`2.9.1 Basic Requirements
`2.9.2 The Need for Planarity
`65
`2.9.3 How the Various Isolation Technologies Meet
`
`Isolation Technologies
`
`65
`
`the Requirements
`
`66
`
`2.10 SILICON-ON-INSULATOR SOI
`TECHNOLOGIES
`66
`
`ISOLATION
`
`2.10.1
`
`Dielectric
`
`67
`
`70
`
`Isolation
`2.10.2 Wafer Bonding
`2.10.3 Silicon-on-Sapphire SOS 72
`by Implanted Oxygen SIMOX 72
`2.10.4 Separation
`Recrystallization ZMR 75
`2.10.5 Zone-Melting
`2.10.6 Full Isolation by Porous Oxidized Silicon FIPOS 76
`2.10.7 Novel SOl CMOS Processes with Selective Oxidation and Selective
`Epitaxial Growth 77
`
`REFERENCES
`
`79
`
`

`
`CONTENTS
`
`CHAP
`
`CONTACT TECHNOLOGY AND
`LOCAL INTERCONNECTS FOR VLSI
`
`84
`
`3.1
`
`THE ROLE OF CONTACT STRUCTURES
`CIRCUIT BEHAVIOR
`84
`
`IN DEVICE AND
`
`3.1.1 Contact Structures in Planar MOSFETs and Bipolar Transistors 85
`
`3.2 THEORY OF METAL-SEMICONDUCTOR CONTACTS
`
`87
`
`3.3
`
`EXTRACTING VALUES OF SPECIFIC CONTACT RESISTIVITY
`FROM MEASUREMENTS
`91
`
`3.3.1 Extraction of
`
`the Specific Contact Resistivity from an Ideal Contact
`92
`
`Structure
`3.3.2 Current Flow in Actual Contact Structures
`3.3.3 Contact Structures Used to Extract Pc1 94
`3.3.4 Procedure for Accurately Extracting Pc from
`CBKR Test Structures 97
`3.3.5 Reported Values of Pc for Various Contact Structures
`Simple Contact-Chain Structure to Monitor Contact
`3.3.6 Use of
`Resistance
`101
`
`93
`
`100
`
`3.4
`
`EVOLUTION OF CONVENTIONAL METAL-TO-SILICON
`THE
`CONTACTS
`101
`
`3.4.1 The Basic Process Sequence of Conventional Ohmic-Contact
`102
`Structures to Silicon
`
`103
`
`3.4.2
`
`3.4.2.1
`
`the Processing Steps
`Additional Details Concerning
`Formation of the Heavily Doped Regions in the Silicon
`3.4.2.2 Formation of Contact Openings Etching
`3.4.2.3 Sidewall Contouring of the Contact Holes by Reflow
`3.4.2.4 Sidewall Contouring by Etching
`3.4.2.5 Deposition
`3.42.6 Metal Deposition
`and Patterning
`3.4.2.7 Sintering the Contacts
`3.4.3 Aluminum-Silicon Contact Characteristics 111
`The Kinetics of the Al-Si Jnteface During Sintering
`3.4.3.1
`3.4.4 Use of Aluminum-Silicon Alloys to Reduce Junction Spiking 116
`3.4.5 Platinum Silicide-to-Silicon Contacts 117
`3.4.5.1 Process Sequence Used to Form PtSi-Si Contacts
`3.4.5.2 Limitations of the PtSi-Si Contact Structure
`
`

`
`CONTENFS
`
`3.5 DIFFUSION BARRIERS
`
`121
`
`3.5.1 Theory of Diffusion Barrier Layers 121
`3.5.2 Materials Used as Diffusion Barriers
`124
`5.2.1 Sputter-Deposited
`Titanium-Tungsten
`35.22 Polysilicon Sacrjficial Barrier
`35.2.3 Titanium Sacrificial Barrier
`5.2.4 Titanium Nitride Passive Barrier
`3.5.2.5 CVD Tungsten
`35.2.6 Experimental Diffusion Barrier Materials
`
`Stuffed Barrier
`
`3.6 MULTILAYERED OHMIC-CONTACT STRUCTURES
`SILICON
`131
`
`TO
`
`3.6.1 AI-TiW-PtSi-Si Contacts
`
`132
`
`3.6.2 Al-TiN-Ti-Si Contacts
`132
`3.6.3 Mo-TiW-Si
`and Mo-Ti-Si Contacts
`
`134
`
`3.7
`
`SCHOTTKY-BARRIER CONTACTS
`
`134
`
`3.8 THE IMPACT OF THE INTRINSIC SERIES RESISTANCE ON
`MOS TRANSISTOR
`PERFORMANCE
`137
`
`3.8.1 The Impact of A5 on MOSFET Performance
`3.8.2 Estimates of A5h A5 Aac and
`138
`on Device Characteristics
`Impact of
`3.8.4 Summary of the Impact of Intrinsic Series- Resistance Effects on
`MOSFET Performance
`142
`
`3.8.3
`
`137
`
`142
`
`3.9
`
`ALTERNATIVE SELF-ALIGNED CONTACT STRUCTURES
`FOR ULSI MOS DEVICES
`143
`
`3.9.1 Self-Aligned Suicide Contacts 144
`3.9.1.1 Self-Aligned Titanium Suicide Contacts
`
`3.9.1.2 Self-Aligned Cobalt Silicide Contacts
`3.9.1.3 Measuring rc of Self-Aligned Silicide Contacts
`3.9.2 Buried-Oxide MOS Contact Structure BOMOS 153
`
`3.10 FORMATION OF SHALLOW JUNCTIONS
`ON CONTACT FABRICATION
`154
`
`AND THEIR
`
`IMPACT
`
`3.1 0.1 Conventional Shallow-Junction Formation
`154
`3.10.2 Alternative Approaches to Forming Shallow Junctions
`3.10.3 Impact of Shallow Junctions on Contact Formation 160
`
`155
`
`

`
`3.11 BURIED CONTACTS AND LOCAL INTERCONNECTS
`
`160
`
`CONTENTS
`
`3.11.1
`
`3.11.2
`
`Butted Contacts and Buried Contacts 160
`Local
`162
`Interconnects
`Formed TiSi2
`TiW over CoSi2
`TiN Formed over TiSi2
`3.11.2.4 Dual-Doped Polysilicon
`
`3.11.2.1
`
`Selectively
`
`3.11.2.2
`
`3.11.23
`
`with Diffused Source/Drain
`
`3.11.2.5
`
`Junctions
`CVD W-Clad Polysilicon
`
`REFERENCES
`
`CHAP
`
`INTERCONNECT
`MULTILEVEL
`TECHNOLOGY FOR VLSI AND ULSI
`
`176
`
`OF INTERCONNECT
`4.1 EARLY DEVELOPMENT
`TECHNOLOGY
`FOR INTEGRATED
`CIRCUITS
`
`176
`
`4.1.1 Interconnects
`
`4.1.2 Interconnects
`
`4.1.3 Evolution
`
`4.1.4 Evolution
`
`of
`
`of
`
`ICs 176
`for Early Bipolar
`in Silicon-Gate NMOS ICs 178
`ICs 179
`Interconnects for Bipolar
`Interconnects for CMOS ICs
`180
`
`4.2 THE NEED FOR MULTILEVEL INTERCONNECT
`TECHNOLOGIES
`180
`
`4.2.1 Interconnect
`
`Limitations
`
`of VLSI
`
`181
`
`4.2.1.1
`
`4.2.1.2
`
`Functional Density
`Propagation Delay
`4.2.1.3 Ease of Design and Gate Utilization
`
`for ASICs and Wafer Scale
`
`Integration
`4.2.1.4 Cost
`
`4.2.2 Problems Associated with Multimetal
`
`Interconnect Processes
`
`187
`
`4.2.3 Terminology
`
`of Multilevel
`
`Interconnect Structures
`
`188
`
`4.3 MATERIALS FOR MULTILEVEL
`TECHNOLOGIES
`189
`
`INTERCONNECT
`
`4.3.1 Conductor Materials for Multilevel
`
`4.3.1.2
`
`Interconnects
`4.3.1.1 Requirements of Conductor Materials Used for VLSI
`Local
`Conductor Materials Polysilicon Metal-Silicides
`Interconnect
`and Polycides
`
`189
`
`Interconnects
`
`

`
`CONTENTS
`
`XIII
`
`4.3.1.3 Aluminum Metallization
`
`4.3.1.4 Tungsten
`
`and Other Conductor Materials for VLSI
`
`Interconnects
`
`4.3.2 Dielectric Materials for Multilevel
`
`Interconnects
`
`194
`
`4.3.2.1 Requirements of Dielectric Layers in Multilevel
`4.3.2.2 Poly-Metal Interlevel Dielectric PMD Materials
`4.3.2.3 CVD Si02 Films as Intermetal Dielectrics
`Si02 Films as Intermetal
`4.3.2.4 Low-Temperature-TEOS
`
`Interconnects
`
`Dielectrics
`
`4.3.25 Other Materials and Deposition
`
`Processes
`
`Used to Form Intermetal
`
`Dielectrics
`
`4.4
`
`PLANARIZATION OF INTERLEVEL DIELECTRIC
`
`LAYERS 199
`
`4.4.1 Terminology
`
`of Planarization
`
`in Multilevel
`
`Interconnects
`
`199
`
`4.4.1.1 Degree of Planarization
`4.4.1.2 The Need for Dielectric Planarization
`4.4.1.3 The Price that Must be Paid as the Degree of Dielectric Planarization
`
`is Increased
`
`4.4.1.4 Design Rules Related to Intermetal Dielectric-Formation
`
`and
`
`Planarization Processes
`
`4.4.2 Step Height Reduction of Underlying Topography as
`208
`Alleviate the Need for Planarization
`
`Technique to
`
`4.4.2.2 Provide
`
`that
`
`is Completely Planar
`Levels
`
`Interconnect
`
`4.4.2.1 Provide Substrate Topography
`Planar Suiface over Local
`4.4.2.3 Minimize the Thickness
`of the Metal
`Layer
`in DM1 by Sloping
`4.4.2.4 Achieve Smoothing of Steps
`Metal-i Lines
`4.4.3 Deposition of Thick CVD 5i02 Layers and Etching Back Without
`
`the Sidewalls of
`
`Sacrificial
`
`211
`
`212
`
`Layer
`4.4.4 Oxide Spacers
`214
`4.4.5 Polyimides as Intermetal Dielectrics
`by Use of Bias-Sputtered 5i02 217
`4.4.6 Planarizing
`4.4.7 CVD 5i02 and Bias-Sputter Etchback
`220
`Layer Etchback
`by Sacrificial
`4.4.8.1 Degree of Planarization Achieved by Sacrificial
`4.4.8.2 Advantages of the Sacrjficial
`Etchback Process
`
`4.4.8 Planarization
`
`222
`
`Etchback
`
`4.4.8.3 Sacrificial
`
`Etchback Process Problems
`
`4.4.8.4 Alternative Sacrificial Etchback Processes
`4.4.9 Spin-On Glass SOG 449
`4.4.9.1 SOG Process Integration
`4.4.9.2 The Etchback SOG Process
`SOG Process
`Plasma CVD 237
`4.4.10 Electron-Cyclotron-Resonance
`Chemical-Mechanical
`238
`4.4.11
`
`4.4.9.3 The Non-Etchback
`
`Polishing
`
`

`
`xiv
`
`CONTENFS
`
`4.5 METAL DEPOSITION
`
`AND VIA FILLING
`
`240
`
`4.5.1 Conventional Approach to Via Fabrication
`to-Metal Contacts through the Vias 240
`45.1.1 Design Rules of Multilevel Metal Systems which are Impacted by
`
`and Formation of Metal-
`
`Conventional
`Via Processing Limitations
`4.5.2 Advanced Via Processing Vertical Vias and Complete Filling of Vias
`244
`by Metal
`45.2.1 Increases
`
`in Packing Density Resulting from Advanced Via
`Process Technology
`4.5.3 Processing Techniques which Allow
`245
`Vertical Vias to be Implemented
`
`45.3.1 Required Degree of Via Filling by Plugs
`4.5.4 CVD
`for Filling Vertical Vias and Contact Holes 245
`Techniques
`45.4.1 General Information on the CVD Tungsten Process
`4.5.4.2 Blanket CVD
`and Etchback
`45.4.3 Selective CVD
`4.5.5 Other CVD Via Filling Processes
`253
`Blanket CVD Polysilicon and Etchback for Contact Hole Filling
`45.5.1
`4.55.2 Selective Deposition
`of Poly
`Formed Silicide Contact Plugs
`4.5 5.3 Selectively
`4.5.5.4 CVD Aluminum
`to CVD for Filling of Vias 254
`4.5.6.1 Bias Sputtering of Al to Achieve Complete Filling of Via Holes
`5.6.2 Laser Planarization of Al Films
`45.6.3 Contact Hole and Via Filling by Selective Electroless Metal
`
`4.5.6 Alternatives
`
`Deposition
`4.5.7 Pillar Formation as an Alternative
`to Filling Contact Holes and Vias 258
`
`4.6
`
`FILLED GROOVES IN
`
`DIELECTRIC LAYER
`
`259
`
`4.7 MANUFACTURING YIELD AND
`RELIABILITY ISSUES OF VLSI
`
`INTERCONNECTS
`
`260
`
`4.7.1 Factors Which Impact Manufacturing Yield 261
`Interconnect-Related Yield Issues
`4.7.2 Multilevel
`
`261
`
`4.7.3 General Reliability
`
`Issues Associated with IC Interconnects
`
`264
`
`4.7.3.1 Electromigration
`
`4.7.3.2 Electromigration
`
`at the Contacts
`
`4.7.33 Stress-Induced Metal Cracks and Voids
`
`4.7.3.4 Corrosion
`
`4.7.4 Reliability
`
`Issues Associated with Multilevel
`
`Interconnects
`
`268
`
`

`
`CONTENTS
`
`xv
`
`4.7.4.1 Hillock Formation and Prevention Measures
`
`4.7.4.2 Dielectric Void Reliability Problems
`
`4.8 PASSIVATION LAYERS
`
`273
`
`4.9 SURVEY OF MULTILEVEL METAL SYSTEMS
`
`276
`
`4.9.1 Bipolar Double-Level Metal Systems 276
`4.9.2 CMOS Double-Level-Metal
`277
`Systems
`4.9.2.1 Non-Planarized DLM 2.0 pm CMOS
`4.9.2.2 Non-Planarized DLM CVD-W Metal 2.0-pm NMOS
`5i02 and SOG DLM for 1.5 pm
`4.9.2.3 Resist Etchback
`CMOS
`Layer Etchback DLM 1.0-pm CMOS
`4.9.2.4 Non-Sacrjficial
`4.9.25 Alternative CMOS DLM Process with TiW/Mo
`as Metal
`4.9.2.6 DLM Processes
`for Submicron CMOS
`283
`4.9.3 Three-Level Metal Systems
`4.9.4 Four-Level Metal Systems
`
`Bias-Sputtered
`
`285
`
`INTERCONNECT
`4.10 SUMMARY OF MULTILEVEL
`TECHNOLOGY REQUIREMENTS FOR VLSI
`
`286
`
`REFERENCES
`
`287
`
`CHAP
`
`MOS DEViCES AND
`NMOS PROCESS INTEGRATION
`
`5.1 MOS DEVICE PHYSICS
`
`298
`
`5.1.3
`
`5.1.1 The Structure and Device Fundamentals of MOS Transistors
`5.1.2 The Threshold Voltage of the MOS Transistor
`301
`Impact of Source-Body Bias on V1 Body Effect
`304
`5.1.4 Current-Voltage Characteristics
`MOS Transistors
`305
`of MOS Transistors 307
`5.1.5 The Capacitances
`
`of
`
`THROUGH DEVICE
`5.2 MAXIMIZING DEVICE PERFORMANCE
`DESIGN AND PROCESSING TECHNOLOGY
`307
`
`5.2.1 Output Current 1D and Transconductance
`gm1 308
`the Threshold Voltage through Process
`5.2.2 Controlling
`and Circuit-Design Techniques 309
`5.2.3 Subthreshold Currents IDst when VG IVTI
`
`311
`
`298
`
`298
`
`

`
`xvi
`
`CONTENTS
`
`313
`5.2.4 Switching Speed
`5.2.5 Junction Breakdown Voltage Drain-to-Substrate
`5.2.6 Gate-Oxide Breakdown Voltage 314
`5.2.7 High Field-Region Threshold-Voltage Value
`
`315
`
`313
`
`5.3 THE EVOLUTION OF MOS TECHNOLOGY
`PMOS AND NMOS
`315
`
`5.3.1 Aluminum-Gate PMOS 316
`5.3.2 Silicon-Gate MOS Technology
`5.3.3 Reduction of Oxide-Charge Densities
`for Adjusting Threshold Voltage
`5.3.4 Ion Implantation
`for MOS 323
`Isolation Technology
`323
`5.3.6 Short-Channel Devices
`
`318
`
`319
`
`5.3.5
`
`321
`
`5.4
`
`PROCESS SEQUENCE FOR FABRICATING NMOS
`LOADS
`INVERTERS WITH DEPLETION-MODE
`324
`
`5.4.1 Operation of an NMOS Inverter with
`Load 324
`Depletion-Mode
`Basic E-D NMOS IC Technology
`327
`5.4.2 Process Sequence of
`
`Starting Material
`5.4.2.1
`5.4.2.2 Active Region and Field Region Definitions
`5.4.2.3 Gate-Oxide Growth and Threshold-Voltage
`and Patterning
`5.4.2.4 Polysilicon Deposition
`5.4.25 Formation of the Source and Drain Regions
`5.4.2.6 Contact Formation
`
`Adjust
`
`and Patterning
`5.4.2.7 Metallization Deposition
`Layer and Pad Mask
`
`5.4.2.8 Passivation
`
`Implant
`
`5.5 SHORT-CHANNEL EFFECTS AND HOW THEY IMPACT MOS
`PROCESSING
`338
`
`5.5.1 Effect of Gate Dimensions on Threshold Voltage 338
`55.1.1 Short Channel Threshold Voltage Effect
`55.1.2 Narrow Gate-Width Effect on Threshold Voltage
`5.5.2 Short-Channel
`Effects on Subthreshold
`Currents Punchthrough
`and Drain-Induced Barrier Lowering
`341
`Effects on I-V Characteristics
`5.5.3 Short-Channel
`5.5.4 Summary of Short-Channel
`Effects
`on the Fabrication of MOS ICs 346
`
`343
`
`5.6
`
`HOT-CARRIER EFFECTS IN MOSFETS
`
`348
`
`5.6.1 Substrate Currents Due to Hot Carriers 349
`
`

`
`CONTENTS
`
`5.6.5
`
`5.6.2
`
`Hot-Carrier
`
`350
`Injection into the Gate Oxide
`Degradation Due to Hot-Carrier Effects
`5.6.3 Device-Performance
`354
`5.6.4 Techniques for Reducing Hot-Carrier Degradation
`354
`Lightly Doped Drains
`5.6.5.1 Drain Engi neering for Optimum LDD Structures
`5.65.2 Asymmetrical Characteristics of LDD MOSFETs
`The Impact of
`5.6.6
`IC Processing
`361
`on Hot-Carrier Device Degradation
`5.6.7 Hot-Carrier Effects in PMOS Transistors 362
`363
`5.6.8 Gate-Induced Drain-Leakage Current
`
`xvii
`
`352
`
`REFERENCES
`
`363
`
`CHAP
`
`CMOS PROCESS INTEGRATION
`
`368
`
`6.1
`
`INTRODUCTION
`
`TO CMOS TECHNOLOGY
`
`368
`
`6.1.1 The Power-Dissipation Crisis of VLSI and How CMOS Came to the
`368
`Rescue
`
`6.1.2 Historical Evolution
`
`6.1.4.1
`
`376
`
`of CMOS 370
`6.1.3 Operation of CMOS Inverters
`373
`6.1.4 Advantages and Disadvantages
`of Modern CMOS Technologies
`Device/Chip Performance Advantages
`6.1.4.2 Reliability Advantages of CMOS
`of CMOS
`6.1.4.3 Circuit Design Advantages
`6.1.4.4 Cost Analysis of CMOS
`of CMOS 380
`6.1.5 Disadvantages
`
`6.2
`
`THE WELL CONTROVERSY IN CMOS
`
`381
`
`6.2.1 The Need for Wells in CMOS 381
`6.2.2 p-Well CMOS 383
`n-Well CMOS 384
`6.2.3
`6.2.4 CMOS on Epitaxial Substrates
`6.2.5 Twin-Well CMOS 387
`6.2.6 Retrograde-Well CMOS 389
`6.2.7 Summary of CMOS Well-Technology
`
`385
`
`Issues
`
`392
`
`6.3 p-CHANNEL DEVICES IN CMOS
`
`392
`
`6.3.1 PMOS Devices with n-PolysiIicon Gates
`6.3.1.1 Punchthrough Susceptibility
`
`392
`
`

`
`xviii
`
`CONTENTS
`
`6.3.2 PMOS Devices with p-PoIysilicon Gates
`397
`6.3.3 Gate Materials having Symmetrical Work Functions with Respect to
`both NMOS and PMOS Devices
`398
`
`6.4 LATCHUP IN CMOS
`
`400
`
`400
`
`403
`
`406
`
`to flow through
`
`both bypass
`
`in CMOS Circuits
`6.4.1 Parasitic pnpn Structures
`6.4.2 Circuit Behavior of pnpn Diodes 402
`6.4.3 Device Physics Behavior of pnpn Diodes
`6.4.4 Summary of Conditions That Must Exist
`406
`in Order for Latchup to Occur
`in CMOS Circuits
`6.4.5 Circuit Behavior of Actual pnpn Structures
`in CMOS Vertical Parasitic Bipolar Transistors
`6.4.5.1 Value of /3
`6.4 5.2 Value of /3 in CMOS Lateral Parasitic Bipolar Transistors
`408
`6.4.6 Circuit and Device Effects that
`Induce Latchup
`6.4.6.1 An external stimulus forward-biases
`the emitter-base of one transistor
`then turns-on the second transistor
`and its collector
`current
`6.4.6.2 An external stimulus causes current
`one or both bipolar
`
`resistorsforward-biasing
`
`transistors
`
`6.4.6.3 Current is shunted through one of the parasitic transistors by some
`degradation mechanism and the resulting collector
`current
`flows
`through the bypass resistor of the second transistor and turns it on
`410
`6.4.7 Test Methods for Characterizing Latchup
`6.4.7.1 Modelling Latchup in CMOS Technology
`6.4.8 Techniques for Reduction
`
`or Elimination of Latchup Susceptibility
`the Current Gains of the Parasitic
`
`6.4.8.1 Processing Techniques that Reduce
`
`413
`
`Bipolar Transistors
`6.4.8.2 Processing Techniques that Reduce Rsub and Rw or Eliminate the
`pnpn Structure
`6.4.8.3 Circuit Layout Techniques used to Decouple Parasitic Bipolar
`
`Transistors
`
`6.5 CMOS ISOLATION TECHNOLOGY
`
`419
`
`Isolation for CMOS 425
`6.5.1 Trench
`6.5.2 Isolation by Selective-Epitaxial Growth for CMOS 426
`
`6.6 CMOS PROCESS SEQUENCES
`
`428
`
`6.6.1 Basic n-Well CMOS Process Sequence
`6.6.2 Twin-Well CMOS Process Sequence
`6.6.2.1 Starting Material
`
`428
`
`431
`
`6.6.2.2
`
`Forming the Wells and Channel Stops
`
`

`
`CONTENTS
`
`xix
`
`6.6.2.3 Active and Field Region Definition
`6.6.2.4 Gate Oxide Growth and Threshold Voltage Adjustment
`and Patterning
`6.6.2 .5 Polysilicon Deposition
`6.6.2.6 Formation of the Source/Drain Regions
`6.6.2.7 CVD Oxide Deposition
`and Contact Formation
`and Patterning
`6.6.2.8 Metal
`
`Deposition
`
`6.6.2.9 IntermetalDielectric Deposition/Planarization
`
`and Via Patterning
`
`6.6.2.10 Metal
`
`Deposition
`
`and Patterning
`
`6.6 .2 .1 Passivation Layer Deposition
`
`and Patterning
`
`6.7 MISCELLANEOUS CMOS TOPICS
`
`441
`
`6.7.1 Electrostatic Discharge Protection for CMOS 441
`6.7.1.1 Diode Protection
`
`6.7.1.2 Node-to-Node Punchthrough
`
`Breakdown Structure
`6.7.1.3 Gate-Controlled
`6.7.1.4 pnpn-Diode ESD Protection for Advanced CMOS Circuits
`6.7.2 Power Supply Voltage Levels for Future CMOS 446
`6.7.3 Low-Temperature CMOS 446
`CMOS 447
`6.7.4 Three-Dimensional
`
`REFERENCES
`
`447
`
`CHAPTER
`
`BIPOLAR AND
`BICMOS PROCESS INTEGRATION
`
`453
`
`7.1 BIPOLAR TRANSISTOR STRUCTURES
`FOR INTEGRATED
`CIRCUITS
`453
`
`7.1.1 The Transistor Action
`
`454
`
`7.1.1.1 Basic Bipolar Transistor Physics
`7.1.1.2 Bipolar Transistor Current Gain
`Transistor Stuctures 458
`
`7.1.2 Integrated-Circuit
`
`7.2 DIGITAL CIRCUITS USING BIPOLAR TRANSISTORS
`
`459
`
`7.2.1 Basic Bipolar-Transistor
`
`Inverter Circuits
`
`459
`
`7.2.2 Bipolar Digital-Logic-Circuit Families
`
`460
`
`7.3 MAXIMIZING BIPOLAR TRANSISTOR PERFORMANCE
`PROCESSING TECHNOLOGY
`THROUGH DEVICE DESIGN
`
`464
`
`

`
`xx
`
`cowtwrs
`
`7.3.1 Current Gain
`
`7.3.2 Early Voltage
`
`464
`
`466
`
`7.3.3 High-Level
`
`Injection Effects Kirk Effect
`
`467
`
`468
`
`Injection Limits in Advanced
`
`472
`
`7.3.4 Operating-Voltage Limits in Bipolar Transistors
`73.4.1 Reachthrough Breakdown
`7.3.4.2 Punchthrough Breakdown
`7.3.4.3 Breakdown
`Voltage and High-Level
`Bipolar Transistors
`7.3.5 Parasitic Series Resistances
`in Bipolar Transistors
`7.3.5.1 Collector Series Resistance Rc
`Base Series Resistance RB
`7.35.2
`7353 Base-Spreading Resistance RB2 and Emitter Current Crowding
`7.35.4 Emitter Series Resistance RE
`7.3.6 Parasitic Junction Capacitances
`73.6.1 Storage Capacitances
`
`in Bipolar Transistors
`
`475
`
`in Bipolar Transistors
`7.3.7 Bipolar Transistor Unity-Gain Frequency
`477
`7.3.8 First Order npn Device Design
`7.3.9 Switching Speed Behavior
`in Bipolar
`Time Calculation in Bipolar Transistors
`7.3.9.1 Propagation-Delay
`7.3.9.2 Propagation Delay in Digital MOS versus Digital Bipolar Circuits
`73 93 General Switching Speed Behavior of Digital Bipolar Circuits
`
`477
`
`ICs 478
`
`7.4 NON-OXIDE-ISOLATED BIPOLAR npn TRANSISTOR
`STRUCTURES
`482
`
`7.4.1 Triple-Diffused 3D Process
`
`483
`
`7.5 STANDARD-BURIED-COLLECTOR PROCESS
`
`483
`
`7.5.1 Characteristics
`
`of npn Transistors Fabricated with the Standard-
`Buried-Collector SBC Process
`483
`7.5.1.1 Limitations of Junction-Isolated SBC Transistors for VLSI Circuits
`486
`7.5.2 Standard-Buried-Collector Process Flow
`
`75.2.1 Starting Material
`
`75.2.2 Buried Layer Formation
`7.5.2.3 Epitaxial Growth
`75.2.4 Formation of Isolation Regions
`75.25 Deep-Collector
`Contact Formation Optional
`7.5.2.6 Base Region Formation
`
`7.5.2.7 Emitter Region Formation
`75.2.8 Contact and Interconnect
`Layer Formation
`
`7.5.2.9 Washed Emitters
`
`7.5.2.10 Schottky Contacts
`
`7.6
`
`OXIDE-ISOLATED
`
`BIPOLAR TRANSISTORS
`
`498
`
`

`
`CONTENTS
`
`xxi
`
`7.7 ADVANCED
`VLSI AND ULSI
`
`BIPOLAR TRANSISITOR STRUCTURES
`500
`
`FOR
`
`7.8 ADVANCED
`
`EMITTER
`
`STRUCTURES
`
`501
`
`7.8.1 Polysilicon
`7.8.1.1 Models
`
`Emitters
`
`501
`
`that Describe Polysilicon-Emitter Behavior
`
`7.8.1.2
`
`Process Technology for Polysilicon-Emitter Fabrication
`7.8.2 Heterojunction Bipolar Transistors HBT5
`506
`
`7.9 SELF-ALIGNED BIPOLAR STRUCTURES
`
`510
`
`7.9.1 Double-Polysilicon Self-Aligned Structures
`SA Structures
`Limitations
`7.9.1.1
`of Double-Polysilicon
`7.9.1.2 Current-Gain Degradation Due to Sidewall
`Injection in SA Bipolar
`Structures
`
`510
`
`7.9.2 Single-Polysilicon
`
`7.9.1.3 Link-Up Region Formation
`Self-Aligned Bipolar Structures
`structures SICOS 520
`
`7.9.3
`
`516
`
`7.10 TRENCH-ISOLATED
`
`BIPOLAR TRANSISTORS
`
`522
`
`7.11 BICMOS TECHNOLOGY
`
`523
`
`Device and Circuit Advantages of BiCMOS
`524
`7.11.1
`7.11.1.1 Comparison of BiCMO5 and CMOS Propagation Delay Times
`7.11.1.2 Power Consumption of BiCMOS versus CMOS Gates
`7.11.1.3 Capability of Providing Either IlL or ECL Outputs From
`BiCMOS Chip
`7.11.1.4 Process Complexity Increases Associated with BiCMOS
`7.11.1 .5 Extending Process Equipment Life by Fabricating BiCMOS
`
`7.12 CLASSIFICATION
`
`OF BICMOS TECHNOLOGIES
`
`529
`
`7.12.1 Digital BiCMOS Technology
`531
`7.12 1.1 Low-Cost Digital BiCMOS Technology
`7.12.1.2 High-Performance Digital BiCMOS
`7.12.1.3 Device-Design Issues Related to Optimizing
`High-Performance
`Digital Modified-Twin-Well BiCMOS Process
`7.12.1.4 An Example Process Sequence for Fabricating High-P etformance 5-V
`Digital BiCMOS ICs
`BiCMOS
`7.12.2 Process Integration of Analog/Digital
`543
`7.12.2.1 Process-Integration Issues of Medium-Voltage Analog BiCMOS
`An Example of an Analog/Digital BiCMOS Process
`7.12.2.2
`
`

`
`7.12.3 BiCMOS Applications
`7.12.3.1 Digital Logic Circuits and Gate Arrays
`Interface Driver Circuits
`7.12.3.3 BiCMOS SRAMs
`7.12.3.4 Analog/Digital Applications
`7.13 Trends in BiCMOS Technology
`
`CONTENTS
`
`551
`
`556
`
`7.12.3.2
`
`7.13
`
`COMPLEMENTARY
`
`BIPOLAR CB TECHNOLOGY
`
`557
`
`REFERENCES
`
`560
`
`CHAP
`
`SEMICONDUCTOR MEMORY PROCESS
`INTEGRATION
`
`557
`
`8.1 TERMINOLOGY OF SEMICONDUCTOR MEMORIES
`
`557
`
`and Read-Only Memories
`8.1.1 Random-Access
`RAMs and ROMS 568
`8.1.2 Semiconductor-Memory Architecture
`570
`8.1.3 Semiconductor-Memory Types
`8.1.4 Read Access Times and Cycle Times in Memories
`Introduced On-Chip Peripheral Circuits
`8.1.5 Recently
`571
`8.1.6 Logic-Memory Circuits
`
`568
`
`571
`
`571
`
`8.2
`
`STATIC RANDOM-ACCESS MEMORIES SRAMS
`
`572
`
`8.2.1.1
`
`8.2.1 MOS SRAMs
`575
`Circuit Operation of MOS SRAM Cells
`8.2.1.2 SRAM Processing and Cell Layout
`Issues
`8.2.1.3 High-Valued Polysilicon Load-Resistors
`8.2.2 Bipolar and BiCMOS SRAMS
`584
`8.2.2.1 BiCMOS SRAMs
`
`for MOS SRAMs
`
`8.3 DYNAMIC RANDOM ACCESS MEMORIES DRAMS
`
`587
`
`8.3.1 Evolution
`
`8.3.1.1 One-Transistor
`
`of DRAM Technology
`587
`DRAM Cell Design
`DRAM Cell
`8.3.1.2 Operation of the One-Transistor
`8.3.1.3 Writing Reading and Refreshing DRAM Cells
`8.3.1.4 Quantity of Charge Stored on DRAM Cells and Their Capacitance
`8.3.15 High-Capacity Hi-C DRAM Cells
`8.3.1.6 CMOS DRAMs
`8.3.2 Design and Economic Constraints
`
`on Advanced DRAM Cells
`
`597
`
`

`
`CONTENrS
`
`8.3.3 Trench Capacitor DRAM Cells
`600
`8.3.3.1 Trench Capacitor Processing for DRAMs
`Trench Capacitor-based DRAM Cells
`8.3.3.2 First Generation
`8.3.3.3 Trench Capacitor Structures with the Storage Electrode Inside the
`Trench
`Inverted Trench Cell
`8.3.3.4 Trench Capacitor Cells with the Access Transistor Stacked Above the
`
`Trench Capacitor
`8.3.4 Stacked Capacitor DRAM Cells
`8.3.5 Soft-Error Failures in DRAMs
`
`609
`
`83.5.1 Techniques Used to Reduce
`8.3.6 The DRAM as
`
`615
`the Soft-Error Rates in DRAMs
`618
`Technology Driver
`
`8.4 MASKED READ-ONLY MEMORIES ROMs
`
`619
`
`8.4.1 Masked ROM Implementation
`
`620
`
`8.5 PROGAMMABLE
`
`ROMS PROMS
`
`621
`
`8.6
`
`ERASABLE PROGRAMMABLE
`READ-ONLY MEMORIES EPROMS
`
`623
`
`8.7 ELECTRICALLY-ERASABLE
`
`PROMS EEPROMS
`
`628
`
`628
`
`8.7.1 MNOS-Based EEPROMs
`FLOTOX EEPROM5
`629
`EEPROMs
`
`8.7.2
`
`8.7.3
`
`Textured-Polysilicon
`
`631
`
`8.8 FLASH EEPROMS
`
`632
`
`8.9 NONVOLATILE
`
`FERROELECTRIC MOS RAMS
`
`635
`
`REFERENCES
`
`637
`
`CHAPS
`
`PROCESS SIMULATION
`
`643
`
`9.1 OVERVIEW OF PROCESS SIMULATION 644
`
`9.1.1 Hierarchy of Simulation Tools for IC Development
`9.1.2 Benefits and Limitations
`of Process Simulation
`9.1.3 Overview of Process Simulators
`647
`
`644
`645
`
`9.1.3.1 Simulator Availability
`9.1.4 General Aspects of Process Simulation
`650
`9.1.4.1 Analytical and Numerical Methods of Solving the Equations that
`Describe Processes
`
`

`
`xxiv
`
`CONThNFS
`
`9.1.4.2 Phenomenological
`
`versus Physical Models
`
`9.1.4.3 Gridding
`9.1.4.4 Interfacing One Simulator with Another
`
`9.2 ONE-DIMENSIONAL
`
`PROCESS SIMULATORS
`
`653
`
`9.2.1.1
`
`9.2.1 SUPREM III Stanford Qniversity PRocess Engineering Model III 655
`The Basic Operation and Capabilities of SUPREM IlL
`9.2.1.2 Additional Comments on the Use of SUPREM III
`9.2.2 SUPREM Ill Models Ion Implantation
`658
`9.2.3 SUPREM III Models Diffusion in Silicon and Si02 and Segregation
`663
`Effects at the Si/Si02 Interface
`9.2.3.1 Diffusion Models Used in SUPREM III
`9.2.3.2 Modeling Low Impurity-Concentration
`9.2.3.3 Modeling High-Impurity Concentration Extrinsic Diffusion in
`
`Intrinsic Diffusion in Silicon
`
`Silicon
`9.2.3.4 Oxidation-Enhanced Diffusion Modeling in SUPREM III
`the Si-SiO2 Inteiface and Diffusion in
`9.2.3.5 Dopant Segregation Effects at
`SiO2
`9.2.4 SUPREM III Models Thermal Oxidation of Silicon
`in One-Dimension
`669
`
`9.2.4.1 High Dopant-Concentration Cases
`the Oxide Growth Rate
`9.2.4.2 Modeling Other Factors Which Impact
`9.2.4.3 Accuracy of Modeling Oxide Growth with SUPREM III
`9.2.5 SUPREM III Models Epitaxial Growth
`674
`9.2.6 SUPREM III Models Deposition Oxidation and Material Properties
`675
`of Polysilicon Films
`SUPREM Ill
`679
`
`9.2.7 Creating
`9.2.8 PREDICT
`
`Input File 677
`
`9.3
`
`INTRODUCTION
`SIMULATORS
`
`TO 2-DIMENSIONAL PROCESS
`680
`
`9.3.1 Classes of 2-Dimensional Process Simulators
`
`683
`
`9.4 TWO-DIMENSIONAL DOPING-PROFILE AND OXIDATION
`PROCESS SIMULATORS
`684
`
`9.4.1.1
`
`9.4.1 SUPRA tanford niversity Eflocess Analysis Program 684
`SUPRA Ion Implantation Models
`9.4.1.2 SUPRA Djffusion Models
`9.4.1.3 SUPRA Oxidation Models
`9.4.1.4 SUPRA Epitaxial Model
`9.4.1.5 SUPRA Input File
`9.4.2SUPREMIV
`687
`
`

`
`CONTENTS
`
`xxv
`
`9.4.2.1 SUPREM IV Models of Djffusion
`9.4.2.2 SUPREM IV Models of Oxidation
`9.4.2.3 SUPREM IV Models of Ion Implantation Epitaxy Deposition and
`Etching
`9.4.2.4 SUPREM
`Input File Format
`9.4.2.5 Comparison of SUPRA and SUPREM P/for 2-D Process
`Simulation
`
`9.4.3 Two-Dimensional
`
`Simulation of Thermal Oxidation
`
`690
`
`9.4.3.1 Empirical Models of 2-D Thermal Oxidation
`
`9.4.3.2 Physical-Based Models of 2-D Thermal Oxidation
`
`9.5 TWO-DIMENSIONAL TOPOGRAPHY
`
`SIMULATORS
`
`696
`
`9.6 SAMPLE SIMULATION AND MODELING OF PROFILES IN
`LITHOGRAPHY AND ETCHING
`697
`
`9.6.1 Simulating Optical Lithography Processes with SAMPLE
`9.6.1.1 Optical
`Imaging Subprogram
`
`697
`
`9.6.1.2 Resist Exposure Subprogram
`
`9.6.1.3 Resist Development Subprogram
`9.6.2 Simulating Etching and Deposition with SAMPLE 706
`9.6.3 Creating Input Files for SAMPLE 708
`
`9.7 OTHER 2-D TOPOGRAPHY
`
`SIMULATORS
`
`710
`
`710
`
`9.7.1 PROLITH
`9.7.2 DEPICT
`710
`9.7.3 PROFILE 711
`9.7.4 SIMBAD
`713
`9.7.5 SIMPL Simulated Programs from the Layout
`9.7.6 SIMPL-DIX
`716
`
`714
`
`9.7.7 Manufacturing-Based
`
`Process Simulators
`
`718
`
`9.8 DEVICE SIMULATORS
`
`718
`
`9.8.1 Simulation of MOS Device Characteristics
`Linear Operation GEMINI
`719
`9.8.2 Simulation of MOS Device Under All dc Operating Conditions
`MINIMOS CADDET CANDE 719
`9.8.3 Bipolar Device Simulators SEDAN BIPOLE
`720
`9.8.4 Combined MOS and Bipolar Device Simulators PICSES SIFCOD
`PADRE and FIELDAY 721
`
`under Subthreshold
`
`and
`
`

`
`xxvi
`xxvi
`
`CONTENTS
`CONTENTS
`
`9.9 CIRCUIT SIMULATORS AND ELECTRICAL PARAMETER
`9.9 CIRCUIT SIMULATORS AND ELECTRICAL PARAMETER
`EXTRACTORS 723
`EXTRACTORS
`723
`
`9.10 FUTURE CHALLENGES IN PROCESS SIMULATION
`9.10 FUTURE CHALLENGES IN PROCESS SIMULATION
`
`723
`723
`
`REFERENCES
`REFERENCES
`
`724
`724
`
`APPENDIX
`APPENDIX A
`
`IC RESISTOR FABRICATION
`IC RESISTOR
`FABRICATION
`
`PROPERTIES OF SILICON AT 300
`APPENDIX B PROPERTIES OF SILICON AT 300 °K
`APPENDIX
`
`APPENDIX
`APPENDIX C
`
`PHYSICAL CONSTANTS
`PHYSICAL CONSTANTS
`
`INDEX
`INDEX
`
`731
`731
`
`737
`737
`
`738
`738
`
`739
`739
`
`

`
`LIST OF TECHNICAL REVIEWERS
`
`Each of the chapters was reviewed for technical correctness
`the review task for the chapters indicated
`graciously undertook
`
`The following persons
`
`Chapter
`
`Dr Joseph
`Monkowski
`Lam Research Corp
`CVD Division
`Fremont CA
`
`Dr Haiping Dun
`Intel Corp
`Santa Clara CA
`
`Chapter
`
`Dr Robert
`
`Blewer
`
`Sandia National Laboratories
`
`Albuquerque NM
`
`Chapter
`
`Dr Farhad
`
`Moghadam
`
`Intel Corp
`Santa Clara CA
`
`Dr Stan Swirhun
`Honeywell SSPL
`Bloomington MN
`
`Dr Terry Herndon
`MIT Lincoln
`Lexington MA
`
`Laboratory
`
`Chapter
`
`Chapter
`
`Chapter
`
`Chapter
`
`Mr Andrew
`Coulson
`TRW Electronic Systems Group
`Redondo Beach CA
`
`Dr John
`
`Chen
`
`Boeing Electronics
`Seattle WA
`
`Dr Samuel
`Wang
`International CMOS Technology
`San Jose CA
`
`Inc
`
`Professor Al
`
`Tasch Jr
`University of Texas
`Austin TX
`
`Dr Michael Kump
`Technology Modeling Associates
`Palo Alto CA
`
`Inc
`
`xxvii
`
`

`
`PREFACE
`
`text designed to provide
`
`SILICON PROCESSING FOR THE VLSI ERA is
`this important and rapidly changing field
`comprehensive and up-to-date treatment of
`three volumes of which this book is the second
`The text will consist of
`Volume
`
`Process Integration
`
`subtitled
`in 1986
`
`subtitled Process Technology was published
`and Manufacturing
`to be subtitled Assembly Packaging
`Technolojy
`for publication in 1993 In Volume
`the individual processes utilized in the
`are covered in depth e.g epitaxial growth
`of silicon VLSI circuits
`and polycrystalline films
`chemical vapor and physical vapor deposition of amorphous
`thermal oxidation of silicon diffusion ion implantation microlithography and etching
`
`Volume
`
`scheduled
`
`fabrication
`
`is
`
`processes
`In this volume we undertake
`Volume
`are combined
`
`to explain how the individual
`
`in
`
`processes described
`This
`integrated