United States Patent [19J
`Leedy
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,924,589
`May 15,1990
`
`(54] METHOD OF MAKING AND TESTING AN
`INTEGRATED CIRCUIT
`
`[76]
`
`Inventor: Glenn J. Leedy, 1061 E. Mountain
`Dr., Santa Barbara, Calif. 93108
`
`[21] Appl. No.: 194,596
`
`[22] Filed:
`
`May 16,1988
`
`Int. Cl.s .•...•.•.............•...........•...•......... HOSK 3/30
`[51]
`[52] u.s. Cl •.............•.............•............ 29/832; 29/407;
`29/846
`[58] Field of Search ....................... 437 /8; 324173 PC;
`29/846,832,407,593
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,405,361 10/1968 Kattner et al ..
`3,618,201 11/1971 Makimoto et al ....................•. 437/8
`3,702,025 11/1972 Archer .................................... 437/8
`3,762,037 10/1973 Baker et al .............................. 437/8
`3,781,670 12/1973 McMahon, Jr ............ 324173 PC X
`3,795,972 3/1974 Calhoun ..................•.•............. 437/8
`3,795,975 3/1974 Calhoun et al ......................... 437/8
`3,835,530 9/1974 Kilby ....•.......•.................•.....•.. 437/8
`3,969,670 7/1976 Wu ...•.•..........•..................•.• 437/8 X
`3,993,934 11/1976 Baker et al ......................... 437/8 X
`4,573,008 2/1986 Lischke .
`4,590,422 5/1986 Milligan .
`4,617,730 10/1986 Geldermans et al ..
`4,715,928- 12/1987 Hamby .
`
`OTHER PUBLICATIONS
`IBM Tech. Disci. Bull., vol. 10, No. 10, Mar. 1968, pp.
`1466-1467 by Dill et al.
`Primary Examiner-Carl J. Arbes
`Attorney, Agent, or Firm-Skjerven, Morrill,
`MacPherson, Franklin & Friel
`ABSTRAcr
`[57]
`Each transistor or logic unit on an integrated circuit
`wafer is tested prior to interconnect metallization. By
`CAD means, the transistor or logic units placement net
`list is revised to substitute redundant defect-free logic
`units for defective ones. Then the interconnect metalli(cid:173)
`zation is laid down and pattemed under control of a
`CAD means. Each die in the wafer thus has its own
`interconnect scheme, although each die is functionally
`equivalent, and yields are much higher than with con(cid:173)
`ventional testing at the completed circuit level.
`The individual transistor or logic unit testing is accom(cid:173)
`plished by a specially fabricated flexible tester surface
`made in one embodiment of several layers of flexible
`silicon dioxide, each layer containing vias and conduc(cid:173)
`tive traces leading to thousands of microscopic metal
`probe points on one side of the test surface. The probe
`points electrically contact the contacts on the wafer
`under test by fluid pressure. The tester surfaces traces
`are then connected, by means of multiplexers, to a con(cid:173)
`ventional tester signal processor.
`
`20 Claims, 16 Drawing Sheets
`
`DODD
`DO DOD
`DOD DO
`DODD
`
`2-16
`
`2-22
`
`Elm Exhibit 2135
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00703
`
`

`
`· U.S. Patent May 15, 1990
`
`Sheet 1 of6
`
`4,924,58~-
`
`FIG. 1
`
`15-2
`
`10
`
`lESlER CONNEC110N ARRAY
`TESTER CONNEC110N ARRAY
`
`FIG. 2
`
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`r
`
`FIG. 3
`
`Elm Exhibit 2135, Page 2
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`FIG. 4b
`
`OF COMPLETED IC
`TEST FUNCTIONALITY
`
`L ___ . ___ _j·
`I
`I
`GATE-ARRAY DEVICES
`LAYERS OF INDIVIDUAL
`I '---LIZA TION INTERCONNECT
`I
`I
`FABRICATION OF METAL-
`I
`I
`CONVENTIONAL FIXED MASK
`I ------:~
`
`REPLACED CONVENTIONAL lC STEP
`
`ARRAY DEVICES
`LAYERS OF INDIVIDUAL GATE-
`METALLIZATION INTERCONNECT
`FABRICATE DISCRETIONARY
`E -BEAM PROCESSING TO
`DEVICE DATABASE AND USE
`THE GENERATED FAULTY
`DATABASE OF THE IC WITH
`CORRECT THE INTERCONNECT
`
`I--
`
`DATABASE
`GENERATE FAULTY DEVICE
`CHARACTERIZATION AND
`GATE-ARRAY DEVICES,
`TESTING OF ALL INDIVIDUAL
`
`FABRICATION
`(TRANSISTOR)
`DEVICE
`GATE-ARRAY
`CONVENTIONAL
`
`FIG. 4a
`
`REVISED
`
`\
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`~ CAD
`PROCESS ~
`
`ORIGIN A
`
`LIST
`NET
`
`SIGNA
`TESTE
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`I
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`10
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`
`WAFER SUPPORT 26/
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`I
`
`SUPPORT
`
`RING
`
`Elm Exhibit 2135, Page 3
`
`

`
`US. Patent
`
`·May 15, 1990
`
`Sheet 3 of6
`
`4,924,589.
`
`Elm Exhibit 2135, Page 4
`
`

`
`U.S. Patent May 15,1990
`
`Sheet 4 of6
`
`4,924,589.
`
`SiD21
`104
`
`SIUCON WAFER
`
`101
`
`FIG. 7
`
`SIUCON WAFER
`
`101
`
`AG. 8
`
`GOLD /NICHROME
`METAL II
`118
`
`AG. 9
`
`Elm Exhibit 2135, Page 5
`
`

`
`4,924,58~ ..
`US. Patent May 15, 1990
`6120-1
`120-2>,
`118
`~~========::::::::=::::f(101
`I
`FIG. 10
`
`Sheet 5 of6
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`126-1
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`FIG. 11
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`124
`FIG. 12
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`Elm Exhibit 2135, Page 6
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`

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`Elm Exhibit 2135, Page 7
`
`

`
`1
`
`4,924,589
`
`METHOD OF MAKING AND TESTING AN
`INTEGRATED CIRCUIT
`
`S
`
`2
`Another object is to permit the fabrication of very
`large integrated circuits, in terms of number of ICLUs
`or devices per circuit.
`The present invention improves on prior art by test-
`ing each ICLU prior to metallization. Redundant
`UCLUs are provided on the die to substitute for those
`found to have defects. Then the metallization layers are
`fabricated so as to exclude defective ICLUs and substi(cid:173)
`tute good ones from the redundant group and render
`10 the circuit operable. The present invention uses a ftne
`grain testing approach, by testing at a low level of com(cid:173)
`plexity.
`One key to the present invention is a specially fabri(cid:173)
`cated flexible test means made of flexible silicon dioxide
`in one embodiment and including multi-layer metal
`interconnects and microscopic test points. The flexible
`tester means includes a tester surface, connected to test
`equipment, that permits testing of each device. Then by
`CAD (computer aided design) means, each die is metal(cid:173)
`lized and the metal layer is patterned by suitable means,
`such as E-beam processing, to fabricate discretionary
`metallization interconnect layers of individual gate
`array devices.
`The tester surface is formed on a standard silicon
`wafer typically by means of a low stress chemical vapor
`deposition process. The tester surface includes its own
`metallization layers. On one side of the tester surface are
`thousands of probe points to contact the contact points
`on the wafer under test. The tester surface is a special
`flexible form of silicon dioxide which can be pressed
`flexibly against the wafer under test to achieve good
`electrical contact.
`By eliminating defects at the device level, process
`yield is vastly increased-for example to about 90%
`regardless of die size, in contrast to much lower yields
`using prior art technology. The present invention also
`allows successful fabrication of very large die compared
`to conventional technology.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a method of making and
`testing integrated circuits, and a device used to perform
`such testing.
`2. Description of the Prior Art
`Integrated circuits (ICs) comprise active and passive
`elements such as transistors, diodes, resistors, and ca(cid:173)
`pacitors, that are interconnected in a predetermined
`pattern to perform desired functions. The interconnec- 15
`tions are effectuated by means of metallization layers
`and vias. A "via" is a hole through an insulation layer in
`which conductor material is located to electrically in(cid:173)
`terconnect one conductive layer to another or to an
`active or passive region in the underlying semiconduc- 20
`tor substrate. Present day technology generally em(cid:173)
`ploys two metallization layers that are superimposed
`over the semiconductor wafer structure. Integrated
`circuits and assemblies have become more complex
`with time and in a logic circuit, the number of inte- 25
`grated circuit logic units (ICLUs) and interconnects on
`a given size die have been substantially increased re(cid:173)
`flecting improved semiconductor processing technol(cid:173)
`ogy. An ICLU can be a device (such as a transistor), a 30
`gate (several transistors) or as many as 25 or more tran(cid:173)
`sistors and other devices.
`Standard processing to make logic structures (i.e.,
`gate arrays) includes ftr fabricating as many as half a
`million transistors comprising a quarter of a million 35
`gates per die. Each semiconductor wafer (typically
`silicon but sometimes of other material such as gallium
`arsenide) includes many die, for example, several hun(cid:173)
`dred. In one type of gate array, for example, the transis(cid:173)
`tors are arrayed in rows and columns on each die, and 40
`each transistor is provided with conductive contact
`points (typically metal but sometimes formed of other
`conductive material such as polycrystalline silicon),
`also arrayed in rows and columns.
`As is well known in the art, these conductive contact 45
`points have a typical center-to-center spacing of about 6
`to 15 microns (t.Lm).
`In the prior art, the next step is to use ftxed masks to
`fabricate the conductive layers (sometimes called "met(cid:173)
`allization layers"), to connect together the individual
`gate-array devices. Typically two or sometimes three
`metalization layers are used.
`After this, the completed die is tested. If any of the
`devices on the die are defective, that die will fail an
`exhaustive test and be scrapped. Therefore, the more
`transistors per die the lower the manufacturing yield. In
`some cases redundant sections of a circuit are provided
`that can be substituted for defective sections of a circuit
`by fuses after metallization. Typically such redundant 60
`sections can be 5% to 10% of the total circuit.
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWING
`FIG. 1 shows a section of a gate array wafer and the
`device contacts.
`FIGS. 2-3 show a top and side view of part of the
`tester surface.
`FIGS. 4(a) and 4(b) show the test procedure.
`FIG. 5 shows the fluid pressure test assembly.
`FIG. 6 shows an exploded view of the wafer and
`tester surface.
`FIGS. 7-12 show the steps to fabricate the tester
`50 surface.
`FIGS. 13-15 show the steps to fabricate another
`embodiment of the tester surface.
`FIG. 16 shows how nine die can form one super die.
`Each reference numeral when used in more than one
`Figure refers to the same structure.
`
`SUMMARY OF THE INVENTION
`An object of this invention is to provide an improved
`test procedure for integrated circuits to increase pro(cid:173)
`duction yields, by testing a circuit at the ICLU level
`(hereinafter called "ftne grain testing"), compared to
`conventional testing at the functional IC or die level.
`
`DETAILED DESCRIPTION
`As stated above, the prior art fabricates a plurality of
`transistors on a die, interconnects the transistors to form
`desired logic, tests the entire die, and scraps the die if
`the logic doesn't work. In the present invention, after
`fabricating the transistors exactly as before, the transis(cid:173)
`tors or ICLUs are tested individually. Then the inter(cid:173)
`connect scheme is modified, if necessary, by CAD
`65 means (of well known design) to bypass defective tran(cid:173)
`sistors or ICLUs and substitute, logically speaking,
`replacement ICLUs. Then the metallization layers are
`deposited, and patterned in accordance with the modi-
`
`Elm Exhibit 2135, Page 8
`
`

`
`4,924,589
`
`3
`tied interconnect scheme typically by E-beam (Elec(cid:173)
`tron-beam) lithography, instead of the masking process
`of the usual conventional scheme, even though each die
`is to carry out the same function as the other die.
`The present invention in one embodiment begins with 5
`a gate array conventionally fabricated on a silicon or
`GaAs wafer. The gate array transistors are arrayed in
`columns and rows on the wafer surface 1, and the active
`regions of each transistor are provided with contact
`points such as 2-1 to 2-32 which are in columns and 10
`rows also as shown in FIG. 1 (not all contact points are
`numbered). Redundant (or extra) devices are designed
`into each column, with a redundancy factor dependent
`on the expected yield of the individual transistors of
`ICLUs being tested.
`The surface of the wafer 1 is optionally planarized
`with a cured layer of polymide 0.8 to 1.5 micron thick
`if the step heights between contact points are greater
`than_ 0.5 microns. (The contact points 2-1 to .2-32 are
`masked from the polymide, and metal is deposited to fill 20
`the via.)
`The fabricated (but not metallized) wafer 1 is now
`ready for testing. In the described embodiment, only
`one column of transistors on each die is tested at a time,
`although testing more than one column per step is possi- 25
`ble. For a die of typical complexity this requires making
`contact with all of the perhaps 10,000 or so contact
`points such as 2-1 to 2-4 in one column simultaneously,
`and then stepping across all 100 or 200 or more columns
`in each die, to totally test each die in step-and-repeat 30
`fashion. Each contact point such as 2-1 is small-usually
`4 X 4 microns. Each wafer contains a plurality of die, the
`exact number depending on the size of the wafer but
`typically being in the hundreds.
`It is also therefore possible to test more than one 35
`column at once to perform testing on the ICLU's.
`The flexible tester of this invention includes a tester
`surface 10 (described in detail below) as seen in FIG. 2
`which includeS-a series of tester surface contact points
`including 15-1, 15-2 (which are arranged to contact on 40
`a one-to-one basis the corresponding contact points in a
`column on the die under test) and a complete wiring
`interconnection, including a testing array which in(cid:173)
`cludes contacts 16-1, 16-2 and 16-3 and interconnect
`pathways 17-1, 17-2 and 17-3 as seen in FIG. 3, at vari- 45
`ous levels 22, 23, 24 in the tester surface. The tester
`array which includes contacts 16-1, 16-2 and 16-3 con(cid:173)
`nects to a conventional tester signal processor as shown
`in FIG. 4a having line driver logic circuits for accessing
`serially or in parallel the devices under test. The driver 50
`logic signals are programmed separately in a well
`known manner and are multiplexed between testing
`array contacts 16, providing programmable input/out(cid:173)
`put means for supplying diagnostic signals to the transis(cid:173)
`tors or ICLUs under test. Therefore, all the wafer 55
`contact points in one column can be accessed in one
`physical contact step of the transistors or devices to be
`tested.
`The wafer 1 under test and the tester surface 10 are
`disposed on a support 26, as shown schematically in 60
`FIG. 4(a), for test purposes, to electrically connect the
`contact points on the tester surface 10 and correspond(cid:173)
`ing contact points on the wafer 1. FIG. 4(b) shows the
`test procedure in process-flow format. A fluid well or
`bladder (not shown) is used to exert an uniform pressure 65
`over the flexible tester surface 10 (FIG. 4(a)) in order to
`conform it to the surface of the wafer 1 under test and
`to ensure that the numerous corresponding contact
`
`4
`points on the tester surface 10 and the wafer 1 come
`together and make firm electrical contact. This is possi(cid:173)
`ble due to the fact that the surface of the wafer 1 under
`test typically has a controlled total runout flatness
`within 6 to 10 microns across its complete surface. Se(cid:173)
`condly,. the tester surface 10 is less than 15 microns
`thick and typically 1.5 microns thick and of a very
`flexible material, such as low stress silicon dioxide.
`Thirdly, the metal contact points are the highest raised
`surface features on either the tester surface 10 or the
`surface of the wafer 1 under test, and are of a controlled
`uniform height typically between 2 and 6 microns.
`The wafer 1 under test as shown in FIG. 4(a) is
`mounted on an x-y motion table (not shown). Move-
`15 ment of the table in the x-y directions positions the
`wafer for test by alignment of the contact points such as
`15-1 and 15-2 of the test surface 10 (FIG. 2) with the
`corresponding device contact points such as 2-1 and 2-2
`of the wafer 1.
`During the test procedure as shown in FIG. 4(a), the
`wafer 1 under test is retained by suction in a substan(cid:173)
`tially planar fixed position, by means of the support 26
`illustrated in FIG. 4(a) and in FIG. 5. Use of suction to
`hold a wafer in place is well-known. Tester surface 10 is
`mounted on a support ring 36 (as described below) to
`provide mechanical support and electrical connections,
`as shown in FIG. 5. The tester surface 10 is urged uni(cid:173)
`formly toward the wafer 1 under test by a fluid well or
`bladder 38 immediately behind tester surface 10. A
`solenoid (not shown) is provided for macro control of
`the pressure exerted by the fluid in the fluid well 38 on
`tester surface 10. The depth of fluid well 38 is less than
`100 mils; this is the distance between the back of tester
`surface 10 and piezoelectric pressure cell 40.
`Piezoelectric pressure cell 40 is a layer of material
`about five-hundredths of an inch (one millimeter) thick
`that will expand about one-half micron when voltage is
`applied to the piezoelectric material. The applied pres(cid:173)
`sure on the back of the tester surface 10 is only a few
`grams per square centimeter. Piezoelectric pressure cell
`40 provides the last increment of pressure on the fluid
`and in turn on the back of tester surface 10 to achieve
`good electrical contact between the contact points such
`as 15-1 and 15-2 on tester surface 10 and the contact
`points such as 2-1 and 2-2 on wafer 1. The fluid is pro(cid:173)
`vided to the assembly through fluid port 46 which is
`connected to a fluid reservoir (not shown). The support
`ring 36 includes computer cabling attachment sites 48
`and multiplexer circuits 50. The support ring structure
`is described in more detail below.
`As described above, mechanical positioners (i.e., x-y
`table aligners and conventional mechanical vertical
`positioners, not shown) bring the wafer 1 to within a
`few mils of the tester surface 10 and make a first approx(cid:173)
`imation of the alignment of contact points through a
`conventional optical aligner (not shown). The optical
`alignment is performed in a manner similar to that used
`by present semiconductor mask aligners, by using align(cid:173)
`ment patterns in predetermined positions on both the
`wafer 1 being tested and the tester surface 10. Only the
`pressure of the fluid moves the tester surface 10 the one
`or two mil distance separating the tester surface 10 and
`the wafer 1 to be tested in order to gain physical
`contact. FIG. 6 illustrates in an exploded view wafer 1
`and tester surface 10 being moved by fluid pressure
`from fluid well 38 just before wafer contact points such
`as 2-1 and 2-2 make contact with corresponding tester
`surface contacts such as 15-1 and 15-2.
`
`Elm Exhibit 2135, Page 9
`
`

`
`4,924,589
`
`5
`In an additional alignment method, a small area (not
`shown) with a pattern of alignment contact points of
`various sizes up to 1 mil (25 microns) square and posi(cid:173)
`tioned at two or three corresponding alignment sites on
`both the wafer 1 and the tester surface 10 is then used as 5
`an electrical circuit feedback system. The feedback
`system, starting with the largest contact points at each
`site and moving progressively to the smallest. deter(cid:173)
`mines the accuracy of the alignment and makes appro(cid:173)
`priate micron sized adjustments under computer control 10
`to within sub-micron x-y alignment accuracy.
`In the described embodiment, the fluid in the test
`surface assembly is Florinert from DuPont. Any alter(cid:173)
`nate fluid with similar nonconductive and nonreactive
`properties could be substituted.
`After an entire wafer 1 has been tested, it is removed
`and another wafer moved into position to be tested.
`The data resulting from the tester signal processor is
`a list of the location of each defective transistors or
`ICLUs. This list is automatically communicated to the 20
`conventional CAD means from the tester signal proces(cid:173)
`sor as shown in FIG. 4. The CAD means then, by spe(cid:173)
`cial software algorithms works out an interconnect
`strategy for each die. Therefore, the master placement
`scheme of the net list is modified in terms of the place- 25
`ment of the defective ICLUs so as to bypass the defec(cid:173)
`tive ICLUs and interconnect defectfree ICLUs from
`the stock of redundant ICLUs.
`The invention uses two alternative software algo(cid:173)
`rithms: recomputation of metallization trace routing or
`a CAD rip-up router.
`The first alternative is the well-known and commer(cid:173)
`cially available recomputation of the metallization trace
`routing for all affected layers of a specific IC after it has
`been tested. -The routing is performed automatically
`with CAD software. This routing procedure requires
`that sufficient defect-free redundant ICLUs have been
`allocated in the master placement ofiCLUs and that the
`redundant ICI:Us can be routed into the circuit given
`the potential restrictions that the number of metalliza(cid:173)
`tion layers may present. The software that precedes this
`processing performs the entry into a CAD system of the
`placement net-list change commands that direct the
`substitution of the defective ICLUs with available re(cid:173)
`dundant ICLUs. These change commands are specific
`to the CAD system that is selected for use, and the
`commands issued are similar to those a circuit designer
`would enter if making an ICLU placement select in a
`design change when using a gate-array
`This recomputation routing approach makes substan(cid:173)
`tial requirements on computing resources. However,
`super-minicomputers presently available are sufficient
`to meet the computational requirements.
`The second software alternative, a CAD rip-up
`router, takes advantage of the knowledge that the de- 55
`fects occurring in current bulk silicon semiconductor
`processes are few in number and are localized (i.e., the
`defects only affect one or two ICLUs at any particular
`defect site), and of the fine grain ICLU structure. The
`!me grain level of testing minimizes the area necessary
`for redundant ICLUs and the complexity of the place(cid:173)
`ment and routing changes that must be effected to cor(cid:173)
`rect for defective ICLUs. Wafer or large ICs that indi(cid:173)
`cate larger than normal numbers of defects or defects
`that are large in affected area when tested by testing
`equipment will cause the wafer to be rejected as outside
`of the acceptable bulk manufacturing standards which
`are typical of all existing IC lines. The number of de-
`
`6
`fects to be expected with standard available silicon
`wafers is approximately five per cm2 currently. This
`means that approximately five or less ICLUs can be
`expected to be defective per cm2. The number of de(cid:173)
`fects per cm2 increase as device feature sizes decrease,
`but not dramatically, as indicated by the current indus-
`trial use of 0.8 micron geometries for 4 Megabit mem(cid:173)
`ory devices, which will soon be in limited production.
`This rip-up router software process approach takes
`advantage of this wafer ICLU defect density character(cid:173)
`istic by employing a CAD rip-up router. This CAD
`software tool has only become available recently and
`heretofore was only used during the design phase of a
`large IC in an effort to conserve designer and computer
`15 time. The rip-up router attempts to make local changes
`to existing IC metallization layout and, therefore, avoid(cid:173)
`ing the expense of recomputing the complete IC's met(cid:173)
`allization trace routing. The rip-up router is an auto-
`matic tool; it accepts change commands to the ICLU
`placement net-list and then computes changes to the
`IC's metallization database. This modified IC metalliza-
`tion database is then processed for input to the E-beam
`lithographic equipment; this processing software is the
`standard software used to drive the E-beam equipment.
`The computer processing time required to do local
`rip-up route changes has been measured and found to be
`typically 1 to 2 seconds on an inexpensive 32-bit mini(cid:173)
`computer.
`The modified net list is next used to produce the
`30 database for the desired interconnect patterns on the
`wafer using E-beam means. The metallization process is
`in one embodiment a two layer metallization, although
`a single layer of metallization or three or more layers of
`metallization can also be used. The process involves
`35 depositing a layer of insulation, such as silicon dioxide,
`typically of about one micron thickness over the wafer
`surface, and cutting vias by means of a mask to the
`contact points on the wafer surface through the silicon
`dioxide layer. Then a layer of metal, typically alumi-
`40 num, is deposited over the silicon dioxide. Then a layer
`of photoresist is deposited and patterned, for example
`using E-beam (maskless) lithography. The E-beam is
`controlled by the CAD database means and its modified
`net list to make the desired interconnect pattern cor-
`45 rected in accordance with the test results. The photore(cid:173)
`sist is then developed and removed where not exposed
`to the E-beam, allowing the patterning of t.he intercon(cid:173)
`nects as desired.
`The metallization process is then repeated for the
`50 second metallization layer and any subsequent metalli(cid:173)
`zation layers. The metallization process is generally
`well known technology, the innovation being that the
`net list is modified for each die even though the function
`to be implemented on each die is identical.
`At this point the wafer is complete, ready for scrib(cid:173)
`ing, packaging and final test as usual.
`The tester surface as mentioned above is a key ele(cid:173)
`ment of this invention.
`The tester surface is specially fabricated using ad-
`60 vanced semiconductor manufacturing methods. Start(cid:173)
`ing as shown in FIG. 7 with typically a conventional5"
`or 6" silicon wafer substrate 101 (without any circuitry
`on it), a layer ofKBr or other release agent 102 is depos(cid:173)
`ited over the wafer 101 surface, followed by a layer of
`65 gold 103 about 1000 A (0.1 micron) thick. Then a layer
`of silicon dioxide 104 of about one micron thickness is
`deposited on the wafer 101 surface by means of chemi(cid:173)
`cal vapor deposition. This is a low stress layer, depos-
`
`Elm Exhibit 2135, Page 10
`
`

`
`4,924,589
`
`25
`
`8
`7
`ited at about 100° F., using commercially available sys(cid:173)
`points, the support ring 122 and its attached layers are
`tems such as provided by Ionic Systems (Milpitas,
`put in a float (not shown), and the float placed in an
`Calif.) or ASM Lithography, Inc. (Tempe, Ariz.). The
`electrolytic solution containing gold with the exposed
`silicon dioxide layer 104 has a surface stress of about
`ends of the vias 108 as shown in FIG. 9 immersed in the
`1()5 dynes/cm2, making it very flexible. Then, using 5
`solution. Voltage is applied and the probe points such as
`conventional mask methods and photoresist layer 106 as
`132 grow by electrolyzation at the ends of the vias 108.
`described above, vias such as 108 are etched, down to
`The probe points such as 132 are thus made of gold in
`the gold layer, in the silicon dioxide layer 104 to define
`the preferred embodiment and grow out of the central
`the probe points. The vias such as 108 are 2 to 4 microns
`part 124 of the test surface as shown in FIG. 12. The
`in diameter.
`10 probe points such as 132 are 2 to 4 microns in diameter,
`The tester surface, in the preferred embodiment, has
`and about 4 microns high. They connect with the m.etal
`two similar gold metallization layers on top of the wa(cid:173)
`in each via, and hence to the two metallization layers.
`fer. The first metallization layer is formed by first de(cid:173)
`The pattern of probe points such as 132 on the tester
`positing, over the KBr layer 102, a silicide layer (not
`surface is unique, and corresponds to the contact test
`shown) 1000 A to 2000 A (0.1 to 0.2 microns) thick to 15
`points on the wafer to be tested.
`act as an etch stop. Then the silicide deposition is re(cid:173)
`Several kinds of probe points 132 can be provided. In
`moved from all but the vias 108. A nichrome/ gold
`an alternative embodiment, probe point height is deter(cid:173)
`metallization-I layer 112 is deposited, to a thickness of
`mined by a mask. To provide masked probe points, a
`1000 to 2000 A, and a first layer metal mask and etch are
`mask containing vias is formed on surface 130 at the
`used to define the interconnect lines by forming traces. 20
`probe point locations, then the points grown in the vias
`Then a second silicon dioxide layer 114, also about
`and then the mask removed. The probe points can be
`one micron thick, is deposited, followed by the second
`aluminum or other suitable metals or conductive materi(cid:173)
`layer via 116 masking, second layer via etching, ni(cid:173)
`als.
`chrome/gold metallization layer-II 118 and second
`The tester surface itself can be fabricated with elasto-
`layer metal mask and etch as shown in FIG. 9.
`merle probe points such as conductive doped polyacet-
`Next, customized multiplexer circuits such as 120_1
`ylene (personal contact with Professor Alan G. Mac
`and 120-2 as shown in side view in FIG. 10 are attached
`Diarmid, University of Pennsylvania and also see "Plas-
`to the metallization-II layer 118. These multiplexers
`tics that Conduct Electricity", Scientific American,
`120-1 and 120-2 are individual die that contact the me-
`tallization-II layer 118 traces as desired, to provide 30 Feb., 1988, pgs. 106-111, by Richard B. Kaner and Alan
`electrical connections to the tester signal processor.
`G. MacDiarmid) that compress on contact with the
`The multiplexers such as 120-1 and 120-2 are dispersed
`contact points of the device or ICLU under test, to
`around the outer part of the metallization-II layer 118
`allow closer probe point spacing or to make the tester
`on the wafer 101, and serve as programmable input/out-
`surface more flexible. Such elastomeric materials are
`put means.
`35 applied and etched with established techniques.
`Next a mechanical structure called a support ring 122,
`In a slightly different method to fabricate the tester
`as shown in top view in FIG. 11, and in side view in
`surface, the substrate wafer first has etched in its center
`FIG. 12, is bonded with epoxy adhesive to the metalli-
`a circular depression one to two inches in diameter and
`zation-II layerl18 on top of the wafer 101. The support
`typically twenty microns deep. This depression will
`ring 122 is typically a quartz annulus (ring) of the same 40 impart a gradual extension to the outer part of the tester
`outer diameter as the wafer substrate 101 and an inner
`surface, so that the center part of the finished surface
`diameter of 1 to 2 inches.
`will extend slightly below the surrounding tester sur-
`The quartz support ring 122 is in one embodiment 0.1
`face.
`inch thick. Its inner area 124 (see FIG. 11) is the contact
`A different tester surface is illustrated in FIGS.
`area of the test surface. The ring 122 thus supports the 45 13-15. Here the multiplexer circuits and tester logic are
`actual contact area 124 and provides electrical connec-
`integrated into the tester surface. FIG. 13 shows how,
`tions to the remainder of the test system. The support
`as before, starting with a staodard semiconductor wafer
`ring 122 has holes such as 126-1 and 126-2 (FIGS. 11,12)
`133, multiplexer and tester· logic circuitry 134 is fabri-
`machined into it to accommodate the multiplexer cir-
`cated on the surface of wafer 133. Then. as described
`cuits including 120-1 and 120-2 as shown in FIG. 12.
`50 above, a depression 135 is etched in the center of wafer
`The support ring 122 and its underlying silicon diox-
`133. The depression 135 is again one to two inches in
`ide and metal layers are now released from the underly-
`diameter and typically twenty mils deep. Then, as
`ing silicon wafer 101 shown in FIG. 9. The release
`shown in FIG. 14. several layers of silicon dioxide and
`agent KBr (or similar material) was the material :first
`metallization 136 are formed on the wafer over depres-
`deposited on the wafer 101. By means of the release 55 sion 135 and over the logic sites 134. In this embodi-
`agent, scribing around the edge of the support ring and
`ment, the tester probe point array sites such as 138 may
`then dipping the assembly shown in FIG. 12 in water
`(optionally) be etched into the surface of the wafer 133
`allows the silicon dioxide layers to be peeled