Illllllllllllllll||||||||||l|||l|l|||l||||lllllllllllllll||||||||||||||||||
`US005502667A
`
`
`5,502,667
`
`
`Mar. 26, 1996
`
`
`[11] Patent Number:
`
`[45] Date of Patent:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Stolle, “Edge—Mounted Chip Assembly For Microproces-
`sor”, IBM Technical Disclosure Bulletin, vol. 23, No. 2, pp.
`
`
`
`
`
`
`
`
`
`581-582, Jul. 1980.
`
`
`
`Carson, “Unconventional focal—p1ane architecture (FPA)”,
`
`
`
`
`SPIE, vol. 225, IR Image Sensor Tech., pp.34-37, 1980.
`
`
`
`
`
`
`
`
`Parks,
`“Batch—Fabricated Three—Dimensional
`Planar
`
`
`
`
`Coaxial
`Interconnections or Microelectronic Systems,”
`
`
`
`
`
`IEEE Trans. on Computers, vol. C-20, No. 5, pp. 504—511,
`
`
`
`
`
`
`
`
`May 1971.
`
`
`Agusta ct al., “High Density Packaging of Monolithic Cir-
`
`
`
`
`
`
`
`cuits”, IBM Technical Disclosure Bulletin, vol. 10, No. 7, p.
`
`
`
`
`
`
`
`
`890, Dec. 1967.
`
`
`
`Bertin et al., “Evaluation of a 3D Memory Cube System”,
`
`
`
`
`
`IEEE, pp. 12-15, 1993.
`
`
`
`
`Primary Examiner——David C. Nelms
`
`
`Assistant Examiner—Huan Hoang
`
`
`
`Attorney, Agent, or Firm—Heslin & Rothenberg
`
`
`
`
`ABSTRACT
`
`
`
`United States Patent
`Bertin et al.
`
`
`
`
`
`[19]
`
`
`
`[54]
`
`
`
`INTEGRATED MULTICHH’ MEMORY
`
`
`
`MODULE STRUCTURE
`
`
`
`
`
`
`Inventors: Claude L. Bertin; Wayne J. Howell,
`
`
`
`
`both of South Burlington; Erik L.
`
`
`
`
`Hedberg, Essex Junction; Howard K.
`
`
`
`
`Kalter, Colchester; Gordon A. Kelley,
`
`
`
`
`Jr., Essex Junction, all of Vt.
`
`
`
`
`
`
`International Business Machines
`
`
`
`Corporation, Armonk, N.Y.
`
`
`
`
`
`Assignee:
`
`Appl. No.: 120,876
`
`
`
`Filed:
`Sep. 13, 1993
`
`
`
`
`Int. Cl.“ ....................................................... G11C 5/02
`
`
`
`
`U.S. Cl.
`.............................. 365/51; 365/63; 257/686;
`
`
`
`
`
`257/724; 361/735; 361/728
`
`
`Field of Search .................................. 365/51, 63, 52;
`
`
`
`
`
`257/686, 724, 777; 361/684, 735, 728
`
`
`
`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`10/1959 Slack ....................................... 317/101
`
`
`
`
`4/1962 Doctor
`29/155.5
`
`
`
`11/1962 Sprude
`317/101
`
`
`
`12/1962 Heidler
`317/100
`
`
`
`6/1964 Heidler .................................... 317/101
`
`
`
`
`
`
`
`
`
`
`
`2,907,926
`
`3,029,495
`
`3,065,384
`
`3,070,729
`
`3,139,559
`
`
`
`
`
`
`
`
`
`
`(List continued on next page.)
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`9/1982
`0075945
`European Pat. Off. .
`
`
`
`
`
`4/1986
`206696
`European Fat. 011.
`.
`
`
`
`
`
`
`France .
`4/1989
`2645681
`
`
`1/1983
`58—l03l49
`
`Japan .
`
`
`
`59—205747 12/1984
`Japan .
`
`
`
`
`
`(List continued on next page.)
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`Future Generations Computer Systems, vol. 4, No. 2, Sep.
`
`
`
`
`
`
`
`
`1988, Amsterdam NL —Kurokawa et al. “3—D VLSI Tech-
`
`
`
`
`
`
`
`nology in Japan and art Example: a Syndrome Decoder for
`
`
`
`
`
`
`
`Double Error Correction”.
`
`
`
`
`[57]
`
`
`
`
`An integrated multichip memory module structure and
`
`
`
`
`
`
`method of fabrication wherein stacked semiconductor
`
`
`
`
`
`
`memory chips are integrated by a controlling logic chip such
`
`
`
`
`
`
`
`
`that a more powerful memory architecture is defined with
`
`
`
`
`
`
`
`the appearance of a single, higher level memory chip. A
`
`
`
`
`
`
`
`
`memory subunit is formed having N memory chips with
`
`
`
`
`
`
`
`each memory chip of the subunit having M memory devices.
`
`
`
`
`
`
`
`
`The controlling logic chip coordinates external communi-
`
`
`
`
`
`
`
`cation with the N memory chips such that a single memory
`
`
`
`
`
`
`
`
`
`chip architecture with NXM memory devices appears at the
`
`
`
`
`
`
`
`
`module’s I/O pins. A preformed electrical interface layer is
`
`
`
`
`
`
`
`employed at one end of the memory subunit to electrically
`
`
`
`
`
`
`
`interconnect the controlling logic chip with the memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`chips comprising the subunit. The controlling logic chip has
`smaller dimensions than the dimensions of the memory
`
`
`
`
`
`
`
`
`chips comprising the subunit. A lead frame, having an inner
`
`
`
`
`
`
`
`opening extending therethrough, is secured to the electrical
`
`
`
`
`
`
`interface layer and the controlling logic chip is secured to the
`
`
`
`
`
`
`
`
`
`electrical interface layer so as to reside within the lead
`
`
`
`
`
`
`
`
`
`
`frame, thereby producing a dense multichip integrated cir-
`
`
`
`
`
`
`
`cuit package. Corresponding fabrication techniques include
`
`
`
`
`
`
`an approach for facilitating metallization patterning on the
`
`
`
`
`
`
`
`side surface of the memory subunit.
`
`
`
`
`
`
`26 Claims, 5 Drawing Sheets
`
`
`
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 1 of 17
`
`

`
`
`
`
`_
`
`5,502,667
`Page 2
`
`
`
`
`
`
`
`4,926,241
`5/1990 Carey ................................ 357/75
`
`
`
`
`4,956,746
`9/1990 Gates, Jr. et al.
`361/385
`
`
`
`
`
`
`
`
`4,983,533
`1/1991 G ................................... 437/7
`
`
`5016138
`5,1991 Wzodman
`351,381
`
`
`
`
`
`
`510191943
`5/1991 Fassbendergt.-111''''''''''''''''1' 361/396
`’
`’
`"
`
`
`
`
`
`
`
`
`
`
`
`
`5/1991 Eichelberger et a1.
`5,019,946
`361/414
`9/1991 K919 "
`' 391/335
`51951365
`
`
`
`
`
`11’1991 5°1°‘“°“
`5,954,771
`437/3
`
`
`
`
`5=°71v792 12/1991 Va“VaIm° 6131'
`437/227
`
`
`
`
`
`2/1992 Delgado 61 31-
`-- 437/52
`54191331
`~
`
`
`
`
`
`5,162,254 11/1992 Usui et al.
`.. 437/63
`
`
`
`
`
`
`11/1993 Capps
`257/690
`5,266,833
`
`
`
`
`
`
`9/1994 Carson etal.
`...................... 257/686x
`5,347,428
`
`
`
`
`
`
`
`
`FOREIGN PATENT DOCUNIENTS
`
`
`
`
`
`61-35547
`
`61—168951
`
`6246535
`
`63-186457
`
`1—53440
`
`2-36554
`
`W089/04113
`
`
`Japan.
`6/1986
`
`
`Japan.
`11/1986
`
`
`Japan.
`5/1987
`
`
`Japan.
`6/1988
`
`
`Japan.
`9/1989
`
`
`Japan.
`1/1990
`
`
`7/1989 WIPO.
`
`
`
`U.S. PATENT DOCUMENTS
`
`
`3152288 1011964 M1111
`317/99
`
`--------------------------------------
`9‘
`1
`=
`
`
`
`
`
`3,370,203
`2/1968 Kravitz etal
`.. 317/101
`31749334
`-- 317/101
`711973 S191“ ''''"
`3,748,479
`.. 250/208
`7/1973 Lehovec ..
`
`
`
`
`
`
`
`
`415201427
`'1 361/339
`5/1985 Bmthemm C1
`4,525,921
`29/577
`7/1985 Carson et a1.
`
`
`
`
`
`
`4,551,629
`.. 250/578
`11/1985 Carson eta].
`
`
`
`
`
`156/633
`9/1986 Yasumoto eta].
`4,612,083
`
`
`
`
`
`1/1987 Brown et a1.
`............................. 357/74
`4,638,348
`
`
`
`
`
`
`_ 357/74
`415461128
`2/1937
`
`
`
`
`
`4,705,155
`351/403
`11/1937
`
`
`
`357/74
`4,727,410
`2/1988
`
`
`
`
`.. 361/388
`4,764,846
`8/1988
`
`
`
`1/1989
`4,801,992
`357/40
`
`
`
`
`
`4/1989
`.. 437/209
`4,818,728
`
`
`
`
`5/1989
`.. 361/383
`4,833,568
`
`
`
`
`8/1989 Carlson
`4,862,249
`
`
`
`
`
`4,868,712
`9/1989 Woodman ..
`
`
`
`
`
`11/1989 Fisher ......
`.. 437/225
`4,879,258
`
`
`
`
`
`4,894,706
`1/1990 Sato et a1.
`357/72
`
`
`
`
`
`
`
`4,901,136
`2/1990 Neugebauer et al.
`357/75
`
`
`
`
`
`
`4,902,641
`2/1990 Koury, Jr.
`
`
`
`
`
`
`‘
`
`
`
`
`
`
`
`
`
`'
`
`
`1
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 2 of 17
`
`

`
`
`
`
`
`M
`
`
`
`my2u3
`
`
`
`
`
`6m_1M3
`
`LIVw_.nS
`
`
`.m
`5
`
`766:M
`
`
`
`5,J,52
`
`/’
`
`1
` W/p//,
`
`MICRON ET AL. EXHIBIT 1074
`Page 3 of 17
`
`

`
`U.S. Patent
`
`
`
`
`Mar. 26, 1996
`
`
`
`
`
`Sheet 2 of 5
`
`
`5,502,667
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 4 of 17
`
`

`
`U.S. Patent
`
`
`
`
`Mar. 26, 1996
`
`
`
`
`
`Sheet 3 of 5
`
`
`5,502,667
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(M)
`
`15
`
`_
`vj
`
`//////////;//////1
`
`
`
`
`
`A
`
`MICRON ET AL. EXHIBIT 1074
`Page 5 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 4 of 5
`
`5,502,667
`
`jjjjgj
`muuam
`
`'3'
`
`Ii
`
`'8'NEIrlllall
`
`V0.
`
`—mmmm_oo<
`
`hm
`
`O...>n
`
`m4:oo:
`
`
`
`mmaomm»m<u3mwm
`
`Homhmomuuusm
`
`..—.flH.
`
`
`
`z_<p<jj_fj---gxxx}j
`
`80In.:Em_Emowem.mm.
`
`«momuaoomomuuusm
`m<oms
`
`MICRON ET AL. EXHIBIT 1074
`Page 6 of 17
`
`

`
`U.S. Patent
`
`
`
`
`Mar. 26, 1996
`
`
`
`
`
`Sheet 5 of 5
`
`
`5,502,667
`
`
`
`(M)
`.__0. _{D_
`
`
`118
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 7 of 17
`
`

`
`1
`
`INTEGRATED MULTICHIP MEMORY
`
`
`
`MODULE STRUCTURE
`
`
`
`TECHNICAL FIELD
`
`
`
`5,502,667
`
`
`
`2
`
`
`
`
`
`
`
`
`chip memory module structure and fabrication techniques
`presented herein provide such an improvement
`
`
`
`
`
`DISCLOSURE OF INVENTION
`
`
`
`
`
`
`
`The present invention relates in one aspect to high density
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`electronic packaging which permits optimization of device
`
`
`
`
`
`
`
`performance within a given volume. In another aspect the
`invention relates to an integrated multichip memory module
`
`
`
`
`
`
`structure and method of fabrication wherein stacked semi-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`conductor memory chips are integrated by controlling logic
`
`
`
`
`
`
`
`
`such that a more powerful memory architecture having the
`functions of a single, higher level memory chip is presented
`
`
`
`
`
`
`
`to external circuitry.
`
`
`
`
`BACKGROUND ART
`
`
`such as
`integrated circuit devices,
`Conventionally,
`
`
`
`
`
`
`memory devices, have been made from wafers of semicon-
`
`
`
`
`
`
`
`
`ductor material which include a plurality of integrated
`
`
`
`
`
`
`
`circuits. After a wafer is made, the circuits are separated
`
`
`
`
`
`
`
`
`from each other by dicing the wafer into small chips.
`
`
`
`
`
`
`
`
`
`
`Thereafter, the chips are bonded to carriers of various types,
`
`
`
`
`
`
`
`
`electrically interconnected by wires to leads and packaged.
`
`
`
`
`
`
`
`
`
`
`
`
`
`By way of improvement, high density electronic packag-
`
`
`
`
`
`
`
`ing modules having multiple semiconductor chips have
`become popular. For example, U.S. Pat. Nos. 4,525,921 and
`
`
`
`
`
`
`
`
`
`4,646,128 by Carson et al. disclose structure and fabrication
`
`
`
`
`
`
`
`techniques for producing one type of high density electronic
`
`
`
`
`
`
`
`
`processing package. Each of these patents describes a semi-
`
`
`
`
`
`
`
`conductor chip stack consisting of multiple integrated circuit
`
`
`
`
`
`
`
`chips adhesively secured together. A metallized pattern is
`
`
`
`
`
`
`provided on one of the side surfaces of the stack for
`
`
`
`
`
`
`
`
`
`
`
`electrical connection of the stack to external circuitry. This
`
`
`
`
`
`
`
`metallization pattern typically includes both individual con-
`
`
`
`
`
`
`
`tacts and bused contacts. The stack is positioned on an upper
`
`
`
`
`
`
`
`
`surface of a substrate such that electrical contact is made
`
`
`
`
`
`
`
`between the stack metallization pattern and a substrate
`
`
`
`
`
`
`
`surface metallization pattern.
`
`
`
`Traditionally, computer memory systems are assembled
`
`
`
`
`
`
`from many types of memory chips, such as, DRAMs,
`
`
`
`
`
`
`
`
`
`SRAMS, EPROMS and EEPROMS. The number of storage
`
`
`
`
`
`
`devices per memory chip technology generation varies but
`
`
`
`
`
`
`
`
`increases over time with more devices per chip being
`
`
`
`
`
`
`
`
`
`delivered with each succeeding generation, thereby provid-
`
`
`
`
`
`
`
`ing greater memory capacity. When a next generation
`
`
`
`
`
`
`
`memory chip becomes available,
`the number of chips
`
`
`
`
`
`
`
`
`needed to make a given memory system is correspondingly
`
`
`
`
`
`
`reduced. With fewer memory chips needed, the resultant
`
`
`
`
`
`
`
`
`memory system becomes physically smaller.
`
`
`
`
`
`Next generation DRAM memory chips have traditionally
`
`
`
`
`
`
`
`increased by 4><the number of bits compared with current
`
`
`
`
`
`
`
`generation technology. For example, assume that the current
`
`
`
`
`
`
`
`
`generation of memory chips comprises 16 megabit (Mb)
`
`
`
`
`
`
`
`
`chips, then by industry standards the next generation will
`
`
`
`
`
`
`
`
`comprise 64 Mb memory chips. This 4>< advancement from
`
`
`
`
`
`
`one generation of memory chips to the next generation is
`
`
`
`
`
`
`
`
`
`
`
`
`traditionally
`accomplished
`only with
`corresponding
`advancement in semiconductor tool and process technolo-
`
`
`
`
`
`
`gies, for example, sufiicient to attain a 2x reduction in
`
`
`
`
`
`
`
`
`
`surface geometries. Due to this interrelationship, a signifi-
`
`
`
`
`
`
`cant interval of time can pass between generations of_
`
`
`
`
`
`
`
`
`
`memory chips. Therefore, a genuine improvement
`in
`
`
`
`
`
`
`memory system design and fabrication would be attained if
`
`
`
`
`
`
`
`current generation memory chips could be packaged to have
`
`
`
`
`
`
`
`the same functions and physical dimensions of an antici-
`
`
`
`
`
`
`
`pated, next generation memory chip. The integrated multi-
`
`
`
`
`
`
`
`
`
`Briefly summarized, the present invention comprises in
`
`
`
`
`
`
`one aspect an integrated multichip memory module which
`
`
`
`
`
`
`
`appears to external, i.e., next level of packaging, circuitry to
`
`
`
`
`
`
`
`have a single memory chip architecture. The memory mod-
`
`
`
`
`
`
`
`
`ule includes a memory subunit having N memory chips
`
`
`
`
`
`
`
`wherein N§2. Each memory chip of the memory subunit
`
`
`
`
`
`
`
`
`
`has M memory devices wherein Mi-2, along with two
`
`
`
`
`
`
`
`
`substantially parallel planar main surfaces and an edge
`
`
`
`
`
`
`
`
`surface. At least one planar main surface of each memory
`
`
`
`
`
`
`
`
`chip is coupled to a planar main surface of an adjacent
`
`
`
`
`
`
`
`
`memory chip of the memory subunit such that the subunit
`
`
`
`
`
`
`
`
`
`has a stack structure. Logic means is associated with the
`
`
`
`
`
`
`
`
`memory subunit and electrically connected to each of the N
`
`
`
`
`
`
`
`memory chips for coordinating external communication
`
`
`
`
`
`
`with the N memory chips of the memory subunit such that
`
`
`
`
`
`
`
`
`
`an integrated memory structure exists that emulates a single
`
`
`
`
`
`
`
`
`memory chip architecture with NXM memory devices.
`
`
`
`
`
`
`
`In an enhanced aspect, an integrated multichip memory
`
`
`
`
`
`
`
`module is provided wherein N memory chips, each having
`
`
`
`
`
`
`
`M memory devices, are integrated in an architecture which
`
`
`
`
`
`
`
`functionally emulates a single memory chip architecture
`
`
`
`
`
`
`with NXM memory devices. Each memory chip includes two
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substantially parallel planar main surfaces and an edge
`surface. The N memory chips are stacked together to form
`
`
`
`
`
`
`
`
`a subunit having at least one side surface and an end surface.
`
`
`
`
`
`
`
`
`
`
`The at least one side surface of the subunit is defined by the
`
`
`
`
`
`
`
`
`
`edge surfaces of the N memory chips. The end surface of the
`
`
`
`
`
`
`
`
`
`subunit is parallel to the planar main surfaces of the N
`
`
`
`
`
`
`
`
`
`memory chips forming the subunit. At least some of the N
`
`
`
`
`
`
`
`
`memory chips include transfer metallurgy extending from
`
`
`
`
`
`
`
`the chip’s input/output (I/O) pads to the at least one side
`
`
`
`
`
`
`
`
`
`surface of the subunit. A first metallization pattern is dis-
`
`
`
`
`
`
`posed on the subunit’s at least one side surface to electrically
`
`
`
`
`
`
`
`connect with the transfer metallurgy extending thereto. An
`
`
`
`
`
`
`
`
`electrical interface layer, disposed adjacent to the end sur-
`
`
`
`
`
`
`
`
`face of the subunit, also has two substantially parallel planar
`
`
`
`
`
`
`
`
`
`main surfaces and an edge surface. One of the substantially
`
`
`
`
`
`
`
`
`parallel planar main surfaces of the electrical interface layer
`
`
`
`
`
`
`
`
`is coupled to the end surface of the subunit. The edge surface
`
`
`
`
`
`
`
`
`
`
`of the electrical interface layer aligns with the at least one
`
`
`
`
`
`
`
`
`
`
`side surface of the subunit. The electrical interface layer
`
`
`
`
`
`
`
`
`
`includes a second metallization pattern disposed there-
`
`
`
`
`
`
`through which electrically connects with the first metalliza-
`
`
`
`
`
`
`
`
`tion pattern on the at least one side surface of the subunit. A
`
`
`
`
`
`
`
`
`
`logic chip is coupled to the electrical interface layer and
`
`
`
`
`
`
`
`
`electrically connected to the second metallization pattern
`
`
`
`
`
`
`such that the logic chip is electrically connected to the
`
`
`
`
`
`
`
`
`memory chips through the first and second metallization
`
`
`
`
`
`
`
`
`patterns. The logic chip includes logic means for coordinat-
`
`
`
`
`
`
`
`
`
`ing external communication with the N memory chips of the
`
`
`
`
`
`
`
`
`subunit such ‘that an integrated memory structure exists
`
`
`
`
`
`
`
`
`which functionally emulates a single memory chip architec-
`
`
`
`
`
`
`
`ture with N><M memory devices.
`
`
`
`
`
`In another embodiment, a multichip integrated circuit
`
`
`
`
`
`
`package is defined having a plurality of semiconductor chips
`
`
`
`
`
`
`of similar dimensions coupled together in a stack having an
`
`
`
`
`
`
`
`end surface and at least one edge surface. A lead frame is
`
`
`
`
`
`
`
`
`secured to the stack at its end surface. The lead frame
`
`
`
`
`
`
`
`
`
`includes an inner opening extending therethrcugh such that
`
`
`
`
`
`
`
`a portion of the stack’s end surface remains exposed. A
`
`
`
`
`
`
`
`
`
`semiconductor chip of smaller dimensions than the similar
`
`
`
`
`
`
`
`dimensions of the plurality of semiconductor chips forming
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 8 of 17
`
`

`
`5,502,667
`
`3
`
`the stack is also provided. This semiconductor chip is sized
`
`
`
`
`
`
`
`
`so as to reside within the inner opening of the lead frame and
`
`
`
`
`
`
`
`
`
`
`be secured to the portion of the stack’s end surface remain-
`
`
`
`
`
`
`
`
`
`ing exposed. Finally, metallurgy means are provided for
`
`
`
`
`
`
`
`
`electrically interconnecting the plurality of semiconductor
`
`
`
`
`
`
`chips forming the stack, the semiconductor chip of smaller
`
`
`
`
`
`
`
`
`dimensions and the lead frame such that a dense multichip
`
`
`
`
`
`
`
`
`
`integrated circuit package is defined from semiconductor
`
`
`
`
`
`
`chips having different dimensions.
`
`
`
`
`Fabrication processes corresponding to the various
`
`
`
`
`
`
`embodiments of the multichip integrated circuit modulel
`
`
`
`
`
`
`package are also described. A particularly novel process is
`
`
`
`
`
`
`
`presented for facilitating side surface metallization of a
`
`
`
`
`
`
`
`plurality of semiconductor chip subassemblies using a sac-
`
`
`
`
`
`
`
`rificial material disposed between the subassemblies.
`
`
`
`
`
`
`A number of advantages are inherent in an integrated
`
`
`
`
`
`
`
`
`multichip memory module
`structure
`and fabrication
`
`
`
`
`
`
`approach in accordance with the invention. For example, the
`
`
`
`
`
`
`
`
`resultant structure can emulate a next generation memory
`
`
`
`
`
`
`
`chip using readily available current generation memory
`
`
`
`
`
`
`
`chips. A packaged module can have physical dimensions
`
`
`
`
`
`
`
`smaller than industry standards for a next generation
`
`
`
`
`
`
`
`memory chip package. Wiring interfaces between existing
`
`
`
`
`
`
`
`and next generation buses can be contained in a preformed
`
`
`
`
`
`
`
`electrical interface layer which can be manufactured and
`
`
`
`
`
`
`
`tested separately. Logic chip transfer metallurgy to a side of
`
`
`
`
`
`
`
`the structure is eliminated, thereby also eliminating any
`
`
`
`
`
`
`
`special processing and testing for the logic chip. Testing and
`
`
`
`
`
`
`
`
`
`
`bum-in of the logic chip, memory chip subassembly and
`
`
`
`
`
`
`
`
`
`preformed electrical interface layer can be separately con-
`
`
`
`
`
`
`
`ducted, thus identifying a potential defect at a lower level
`
`
`
`
`
`
`
`assembly. The controlling logic chip can reside entirely
`
`
`
`
`
`
`
`
`within an inner opening in the lead frame. Further, any
`
`
`
`
`
`
`
`
`
`number of semiconductor chips can be employed within a
`
`
`
`
`
`
`module’s stack. The number employed depends upon the
`
`
`
`
`
`
`
`
`memory chip architecture selected and the memory module
`
`
`
`
`
`
`
`
`architecture desired. The logic control function can be
`
`
`
`
`
`
`
`
`allocated over one or more chips fitting within the lead frame
`
`
`
`
`
`
`
`
`
`
`opening on the preformed electrical interface layer. Decou-
`
`
`
`
`
`
`
`pling capacitors and resistors can also be placed within the
`
`
`
`
`
`
`
`
`
`lead frame opening and attached to the electrical interface
`
`
`
`
`
`
`
`
`layer.
`
`
`
`
`25
`
`
`
`
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`
`
`These and other objects, advantages and features of the
`
`
`
`
`
`
`
`
`
`present invention will be more readily understood from the
`
`
`
`
`
`
`
`
`following detailed description of certain preferred embodi-
`
`
`
`
`
`
`ments of the present invention, when considered in conjunc-
`
`
`
`
`
`
`
`tion with the accompanying drawings in which:
`
`
`
`
`
`
`FIG. 1 is a perspective view of one embodiment of an
`
`
`
`
`
`integrated multichip memory module pursuant to the present
`
`
`
`
`
`
`
`invention;
`
`FIG. 2 is a cross-sectional elevational view of the inte-
`
`
`
`
`
`
`grated multichip memory module of FIG. 1 taken along lines
`
`
`
`
`
`
`
`
`2—2;
`
`FIG. 3 is a cross—sectional elevational view of an alternate
`
`
`
`
`
`embodiment of an integrated multichip memory module in
`
`
`
`
`
`accordance with the present invention;
`
`
`
`
`
`FIG. 4 is a block diagram schematic of one embodiment
`
`
`
`
`
`
`of a controlling logic circuit for the multichip memory
`
`
`
`
`
`
`
`
`modules of FIGS. 1-3;
`
`
`
`FIG. 5 is an enlarged partial cross-section of one embodi-
`
`
`
`
`
`
`
`ment of the layers disposed between the two opposing planar
`
`
`
`
`
`
`
`
`
`surfaces of adjacent memory chips within an integrated
`
`
`
`
`
`
`
`
`multichip memory module pursuant to the present invention;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4
`
`FIG. 6 is an elevational view of one embodiment of a
`
`
`
`
`
`
`multichip memory subunit and electrical
`interface layer
`
`
`
`
`
`
`
`subassembly in accordance with the present invention; and
`
`
`
`
`
`
`
`FIG. 7 is an elevational view of one embodiment of
`
`
`
`
`
`
`multiple subassemblies of FIG. 6 arranged in a single
`
`
`
`
`
`
`
`extended stack to facilitate side surface metallization pro-
`
`
`
`
`
`
`
`cessing of each subassembly in accordance with a fabrica-
`
`
`
`
`
`
`tion technique pursuant to the present invention.
`
`
`
`
`
`
`
`BEST MODE FOR CARRYING OUT THE
`
`
`
`
`
`INVENTION
`
`
`
`
`An integrated multichip memory module in accordance
`
`
`
`
`
`
`with the invention can be implemented using any one of a
`
`
`
`
`
`
`
`
`variety of available memory chip architectures. By way of
`
`
`
`
`
`
`
`example, the following discussion assumes that four 16 Mb
`
`
`
`
`
`
`
`DRAMs are to be assembled in a memory stack. This
`
`
`
`
`
`
`
`multichip memory module emulates exactly a next genera-
`
`
`
`
`
`
`
`tion memory chip, i.e., a 64 Mb DRAM. This integrated,
`
`
`
`
`
`
`
`function is accomplished by associating a control logic chip
`
`
`
`
`
`
`with the stack of four memory chips. The resultant module
`
`
`
`
`
`
`
`
`
`of four 16 Mb DRAMs plus logic chip can be sized to fit into
`
`
`
`
`
`
`
`
`an industry standard 64 Mb package, or if desired, a smaller
`
`
`
`
`
`
`package. Compared with single memory chips, there are
`
`
`
`
`
`
`
`
`significant processing, manufacturability and cost advan-
`
`
`
`
`
`
`tages to this integrated multichip memory module structure
`
`
`
`
`
`
`
`in accordance with this invention.
`
`
`
`
`
`In the figures, which are not drawn to scale for ease of
`
`
`
`
`
`
`
`
`
`
`understanding, the same reference numbers are throughout
`
`
`
`
`
`
`
`multiple figures to designate the same or similar compo-
`
`
`
`
`
`
`
`nents. FIG. 1 depicts one embodiment of the integrated
`
`
`
`
`
`
`
`multichip memory module, generally denoted 10, pursuant
`
`
`
`
`
`
`
`to the invention. In this embodiment, four memory chips
`
`
`
`
`
`
`
`
`
`(M) 14 are connected in a stack 12 having the shape of a
`
`
`
`
`
`
`
`rectangular parallelepiped. Each memory chip 14 has two
`
`
`
`
`
`
`
`
`substantially parallel planar main surfaces and an edge
`
`
`
`
`
`
`
`
`surface with at
`least one planar main surface of each
`
`
`
`
`
`
`
`
`
`memory chip being coupled to a planar main surface of an
`
`
`
`
`
`
`
`adjacent memory chip in the stack 12. Multiple layers 16
`
`
`
`
`
`
`
`
`
`(see FIG. 5) are disposed between adjacent memory chips
`
`
`
`
`
`
`
`
`14. Each layer 16 contains appropriate transfer metallurgy
`
`
`
`
`
`
`
`15 (FIG. 2) and insulation layers 17A to provide electrical
`
`
`
`
`
`
`
`
`connection to the storage devices of the respective memory
`
`
`
`
`
`
`
`chip. An adhesive layer 17 (FIG. 5) such as a Thermid®
`
`
`
`
`
`
`
`
`polymer (TM of National Starch and Chemical Co.) secures
`
`
`
`
`
`
`
`
`adjacent memory chips 14 together. Disposed along at least
`
`
`
`
`
`
`
`one end surface of stack 12 is a preformed electrical inter-
`
`
`
`
`
`
`
`face layer 18 which has a metallization pattern 28 there-
`
`
`
`
`
`
`
`
`
`
`through.
`In one embodiment, layer 18 comprises a Upilex (or
`
`
`
`
`
`
`
`
`alternative insulator) flex layer wherein plated throughholes
`
`
`
`
`
`
`
`or vias interconnect some thin-film wiring on a top surface
`
`
`
`
`
`
`
`
`of layer 18 and thin-film wiring on a bottom surface of the
`
`
`
`
`
`
`
`
`layer (see, eg., FIG. 2). (There is other top surface thin-film
`
`
`
`
`
`
`
`
`
`wiring 25B which provides for the interconnection of the
`
`
`
`
`
`
`
`
`logic chip 22 and lead frame 32.) Together these wirings
`
`
`
`
`
`
`
`
`
`
`comprise metallization pattern 28, only one thin—filrn wire is
`
`
`
`
`
`
`
`
`shown in phantom in FIG. 1. The metallization pattern
`
`
`
`
`
`
`within electrical interface layer 18 routes, for example, 16
`
`
`
`
`
`
`
`
`Mb wiring from a control logic chip 22 to another metalli-
`
`
`
`
`
`
`
`
`zation pattern 20 disposed on an insulator 21 on at least one
`
`
`
`
`
`
`side surface of stack 12. Only one type of metallization
`
`
`
`
`
`
`
`
`
`
`pattern 20 is depicted in FIG. 1 for clarity. T connects are
`
`
`
`
`
`
`
`employed at the interface between metallization pattern 28
`
`
`
`
`
`
`and metallization pattern 20. If desired, multiple side sur-
`
`
`
`
`
`
`
`
`
`faces of stack 12 could accommodate buses or other wiring
`
`
`
`
`
`
`
`
`MICRON ET AL. EXHIBIT 1074
`Page 9 of 17
`
`

`
`5,502,667
`
`
`
`5
`
`connections to the semiconductor memory chips (M). Stan-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`dard transfer metallurgy 15 is brought out and electrically
`connected to metallization pattern 20 on the at least one side
`
`
`
`
`
`
`
`surface of stack 12. Again, interconnection of transfer met-
`
`
`
`
`
`
`
`allurgy 15 and metallization pattern 20 is achieved using
`
`
`
`
`
`
`
`
`T-connects.
`
`One feature to note is that control logic chip 22 has
`
`
`
`
`
`
`
`
`
`
`dimensions
`smaller
`than the common dimensions of
`
`
`
`
`
`
`
`memory chips 14 forming stack 12. This size difference
`
`
`
`
`
`
`
`
`
`allows control logic chip 22 to be placed within a center
`
`
`
`
`
`
`
`
`
`opening 25 in a lead frame 32 (comprised of the lead 34 and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the insulation/adhesive layer 30) disposed above preformed
`electrical interface layer 18. Lead frame 32, which surrounds
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`logic chip 22, contains multiple leads, with only one lead 34
`being shown. External circuitry connects to module 10 via,
`
`
`
`
`
`
`
`for example, a conventional lead 34. Standard wirebond
`
`
`
`
`
`
`
`technology is used to interconnect the logic chip 22 and
`
`
`
`
`
`
`
`
`memory chip stack 12 to the lead 34. In practice, a wire 31
`
`
`
`
`
`
`
`
`is used to interconnect the lead and a contact pad 25B on the
`
`
`
`
`
`
`
`
`
`surface of interface layer 18. A second wire 31A intercon-
`
`
`
`
`
`
`
`
`nects contact pad 25B and I/O pad 24 on control logic chip
`
`
`
`
`
`
`
`
`
`
`22. (An alternative interconnection technique would have
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wire 31 interconnect lead 34 and logic chip I/O 24.) Lastly,
`wire 26 interconnects I/O pad 24 on control logic chip 22
`
`
`
`
`
`
`
`and contact pad 25A on the surface of interface layer 18. As
`
`
`
`
`
`
`
`
`noted, contact pad 25A on interface layer 18 comprises part
`
`
`
`
`
`
`
`
`of metallization pattern 28. Metallization pattern 28 is
`
`
`
`
`
`
`
`connected to metallization pattern 20 on at least one side
`
`
`
`
`
`
`
`surface of stack 12. In this first embodiment, wires 26, 31,
`
`
`
`
`
`
`
`
`
`and 31A connect to arrays of leads 34 and contact pads 25A
`
`
`
`
`
`
`
`
`
`and 25B. Only three interconnecting wires are depicted in
`
`
`
`
`
`
`
`
`FIG. 1 and FIG. 2. In actual implementation, there is a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plurality of interconnections between logic chips 22, pads
`25A and 25B on interface layer 18, and lead frame 32
`
`
`
`
`
`
`
`
`
`
`including wires 26, 31, and 31A.
`
`
`
`
`
`
`For this example, the 64 Mb and 16 Mb wiring connec-
`
`
`
`
`
`
`tions are also shown in FIG. 2.. In this figure, wires 31 & 31A
`
`
`
`
`
`
`
`
`and lead 34 comprise 64 Mb wiring, while wires 26, 28 and
`
`
`
`
`
`
`
`
`20 comprise 16 Mb wiring. Further, thin-film 16 Mb wiring
`
`
`
`
`
`
`15 is shown above the top planar surface of each memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`chip 14. This wiring 15 represents the transfer metallurgy
`from each memory chip 14 to chip I/O 14A to metallization
`
`
`
`
`
`
`
`
`pattern 20 on the side surface of stack 12. A plurality of
`
`
`
`
`
`
`
`
`
`
`thin—film wirings would typically connect each memory chip
`
`
`
`
`
`
`
`
`to the side surface metallization pattern. FIG. 2 also shows
`
`
`
`
`
`
`
`
`
`a completed package wherein an encapsulant 40 surrounds
`
`
`
`
`
`
`the multichip memory module. Encapsulant 40 can comprise
`
`
`
`
`
`
`
`any conventional encapsulating material. One feature to note
`
`
`
`
`
`
`
`in this example is that external wiring (64 Mb) to integrated
`
`
`
`
`
`
`
`
`
`multichip memory module 10 is separate from intra-module
`
`
`
`
`
`
`wiring, i.e., 16 Mb wiring.
`
`
`
`
`As noted, when packaged the dimensions of an integrated
`
`
`
`
`
`
`
`multichip memory module 10 pursuant to the invention are
`
`
`
`
`
`
`
`such that the module will fit within the target physical
`
`
`
`
`
`
`
`
`
`
`dimensions for a next generation memory chip. This is in
`
`
`
`
`
`
`
`
`part accomplished by the provision of a logic chip 22 which
`
`
`
`
`
`
`
`can reside within center opening 25 in lead frame 32. Very
`
`
`
`
`
`
`
`
`
`little area is required to implement
`the logic circuits
`
`
`
`
`
`
`
`
`
`described below. Therefore, extra area within logic chip 22
`
`
`
`
`
`
`
`
`can be used for customer-specific applications. These appli-
`
`
`
`
`
`
`
`cations include SRAM, psuedostatic RAM, error correction
`
`
`
`
`
`
`
`code, memory handshaking, and array built-in self-testing.
`
`
`
`
`
`
`
`Inclusion of such applications on logic chip 22 could dra-
`
`
`
`
`
`
`
`
`matically improve performance of the chip for customer-
`
`
`
`
`
`
`
`specific uses.
`
`
`The basic method to “fit” an integrated multichip memory
`
`
`
`
`
`
`
`module, comprised of current generation chips, e.g., 16 Mb,
`
`
`
`
`
`
`
`
`
`6
`
`into a plastic package that is smaller in volume than the
`
`
`
`
`
`
`
`
`initial next generation, e.g., 64 Mb,
`industry standard
`
`
`
`
`
`
`
`
`(IEDEC) package is to trade plastic encapsulation material
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`for silicon, i.e., multiple semiconductor chips. Historically
`initial next generation chip packaging grows in length and
`
`
`
`
`
`
`
`
`width proportional
`to next generation chip size. Plastic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`package height, however, has remained constant through
`
`
`
`
`
`
`
`several memory chip technology generations. For a given
`chip technology generation, e.g., 16 Mb, as the fabrication
`
`
`
`
`
`
`
`
`processes and manufacturing tool technology mature there is
`
`
`
`
`
`
`
`usually a complementary reduction in chip length and width,
`
`
`
`
`
`
`
`i.e., the chip size shrinks as the technology matures, with a
`
`
`
`
`
`
`
`
`
`commensurate reduction in plastic packaging size. In gen-
`
`
`
`
`
`
`
`eral, this shrinking proceeds to the point where the next
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`generation chip approximately equals the size of the previ-
`ous, fully mature, generation. Therefore a multichip memory
`
`
`
`
`
`
`
`module that emulates a next generation technology in accor-
`
`
`
`
`
`
`
`dance with the present invention can be readily fabricated to
`
`
`
`
`
`
`
`
`have smaller length and width than the initial single next
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`generation memory chip. The height of the multichip
`memory module plastic package can exactly meet the next
`
`
`
`
`
`
`
`
`
`generation JEDEC height standards by reducing the thick-
`
`
`
`
`
`
`
`ness of the plastic encapsulant and/or reducing the thickness
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of the memory chips comprising the multichip module.
`
`
`
`
`
`
`
`Thereby resulting in a smaller plastic package compared
`
`
`
`
`
`
`wi