United States Patent [19]
`Sakuta et a1.
`
`US005208782A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,208,782
`May 4, 1993
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE HAVING A PLURALITY OF
`NIEMORY BLOCKS AND A LEAD ON CHIP
`(LOC) ARRANGEMENT
`[75] Inventors: Toshiyuki Sakuta; Masamiehi
`Ishihara, both of Hamura; Kazuynki
`Miyazawa, Iruma; Masanori
`Tazunolti, Hamura; Hidetoshi Iwai;
`Hisashi Nakamnra, both of Shin;
`Yasushi Takahashi, Tachikawa;
`Toshio Maeda, Ohme; Hiromi
`Matsuura, Tokorozawa; Ryoichi
`Hori, I-linode; Toshio Sasaki,
`Hachioji; Osamu Sakai, Kodaira;
`Hiroyulti Uchiyama, Fuchuu; Eiji
`Miyamoto; Kazuyoshi Oshima, both
`of Ohme; Yasuhiro Kasama, Tokyo,
`all of Japan
`[73] Assignees: Hitachi, Ltd., Tokyo; Hitachi Vlsi
`Engineering Corp., Kodaira, both of
`Japan
`[21] Appl. No.: 892,708
`[22] Filed:
`May 29, 1992
`
`[63]
`
`Related U.S. Application Data
`Continuation of Ser. No. 478,541, Feb. 9, 1990, aban
`doned.
`Foreign Application Priority Data
`[30]
`Feb. 9, 1989 [JP]
`Japan .................................. .. l-30l96
`Mar. 20, 1989 [JP]
`Japan .................................. .. 1-65839
`
`[51] Int. Cl.5 .............................................. ._ GllC 5/06
`[52] U.S. Cl. ............................... .. 365/230.03; 365/51;
`365/63; 257/784; 257/786
`[58] Field of Search .................... .. 365/51, 63, 230.03;
`357/45, 70
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,809,234 2/ 1989 Kuwashiro ................... .. 365/2300?!
`
`4,855,958 8/1989 Ikeda . . . . . . . . . . . . .
`
`. . . . . . .. 357/45
`
`. 365/230.03
`4,905,201 2/1990 Ohira et a1.
`365/230.03
`4,907,199 3/1990 Dosaka ct a1.
`4,914,630 4/1990 Fujishima ..................... .. 365/230.03
`
`4,930,1XX) 5/ 1990
`4,934,820 6/1990
`4,945,395 7/1990
`4,951,122 8/1990
`4,958,316 9/1990
`4,974,053 11/1990
`4,984,202 1/ 1991
`4,987,474 1/ 1991
`4,989,068 I/ 1991
`5,028,986 7/ 1991
`
`FOREIGN PATENT DOCUMENTS
`
`106693 10/1977 Japan .
`
`OTHER PUBLICATIONS
`“Manufacturers Groping for 16M DRAM ‘Speci?ca
`tions Toward the Sample Delivery in 1990”, Nikkei
`Micro Device, Mar. 1, 1988, pp. 67-81.
`Primary Examiner-Joseph L. Dixon
`Assistant Examiner-Jack A. Lane
`Attorney, Agent, or Firm-Antonelli, Terry, Stout 8t
`Kraus
`ABSTRACT
`[57]
`A semiconductor integrated circuit memory structure is
`provided which uses macro~cellulated circuit blocks
`that can permit a very large storage capability (for ex
`ample, on the order of 64 Mbits in a DRAM) on a single
`chip. To achieve, this, a plurality of macro-cellulated
`memory blocks can be provided, with each of the mem
`ory blocks including a memory array as well as addi
`tional circuitry such as address selection circuits and
`input/ output circuits. Other peripheral circuits are pro
`vided on the chip which are common to the plurality of
`macro-cell memory blocks. The macro-cell memory
`blocks themselves can be formed in an array so that
`their combined storage capacity will form the large
`overall storage capacity of the chip. The combination of
`the macro-cell memory blocks and the common periph
`eral circuitry for controlling the memory blocks permits
`a faster and more efficient refreshing operation for a
`DRAM. This is enhanced by at LOC (Lead On Chip)
`arrangement used in conjunction with the memory
`blocks.
`
`28 Claims, 34 Drawing Sheets
`
`MICRON ET AL. EXHIBIT 1067
`Page 1 of 59
`
`

`
`U.S. Patent
`
`May 4, 1993
`
`Sheet 1 of 34
`
`5,208,782
`
`MICRON ET AL. EXHIBIT 1067
`Page 2 of 59
`
`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 2 of 34
`
`5,208,782
`
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`MICRON ET AL. EXHIBIT 1067
`Page 3 of 59
`
`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 3 of 34
`
`5,208,782
`
`FIG. 3
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`MICRON ET AL. EXHIBIT 1067
`Page 4 of 59
`
`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 4 of 34
`
`5,208,782
`
`FIG. 4
`
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`
`MICRON ET AL. EXHIBIT 1067
`Page 5 of 59
`
`

`
`U.S. Patent
`
`May 4, 1993
`
`Sheet 5 of 34
`
`5,208,782
`
`FIG. 5A
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`MICRON ET AL. EXHIBIT 1067
`Page 6 of 59
`
`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 6 of 34
`
`5,208,782
`
`FIG. 5B
`
`CHIP
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`
`MICRON ET AL. EXHIBIT 1067
`Page 7 of 59
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`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 7 of 34
`
`5,208,782
`
`FIG. 5C
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`
`MICRON ET AL. EXHIBIT 1067
`Page 8 of 59
`
`

`
`US. Patent
`
`May 4, 1993
`
`Sheet 8 of 34
`
`5,208,782
`
`FIG. 6_
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`MICRON ET AL. EXHIBIT 1067
`Page 9 of 59
`
`

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`US. Patent
`
`May 4, 1993
`
`Sheet 9 of 34
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`5,208,782
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`MICRON ET AL. EXHIBIT 1067
`Page 10 of 59
`
`

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`US. Patent
`
`May 4, 1993
`
`Sheet 10 of 34
`
`5,208,782
`
`FIG. 8
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`MICRON ET AL. EXHIBIT 1067
`Page 11 of 59
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`US. Patent
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`May 4, 1993
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`MICRON ET AL. EXHIBIT 1067
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`May 4, 1993
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`MICRON ET AL. EXHIBIT 1067
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`US.‘ Patent
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`May 4, 1993
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`MICRON ET AL. EXHIBIT 1067
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`MICRON ET AL. EXHIBIT 1067
`Page 17 of 59
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`US. Patent
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`May 4, 1993
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`MICRON ET AL. EXHIBIT 1067
`Page 18 of 59
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`U.S. Patent
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`May 4, 1993
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`Sheet 18 of 34
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`MICRON ET AL. EXHIBIT 1067
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`MICRON ET AL. EXHIBIT 1067
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`SEMICONDUCIOR INTEGRATED CIRCUIT‘
`DEVICE HAVING A PLURALITY OF MEMORY
`BLOCKS AND A LEAD ON CHIP (LOC)
`ARRANGEMENT
`
`This application is a continuation of application Ser.
`No. 478,541, filed on Feb. 9, 1990, abandoned.
`BACKGROUND OF THE INVENTION
`
`l0
`
`the operation speed due to the aforementioned signal
`delay. In other words, a new technology different from
`the techniques used in the prior art for about 1 Mbit or
`4 Mbits is required for realizing the large storage capac-
`ity of about 64 Mbits.
`In order to improve the degree of integration of the
`semiconductor memory device, on the other hand, it is
`necessary to reduce the size of the memory cell and the
`width of the wiring lines such as the word shunting
`lines. In the DRAM of l6 Mbits, for example, it is ex-
`pected that the word shunting lines have a width of
`about 0.6 to 0.8 pm. The word shunting lines are fre-
`quently made of aluminum. In case the electric wiring
`lines are made of thin aluminum, they can easily be
`broken by the so-called “electro-migration phenomena”
`(which will be shortly referred to as “EMD"), in which
`wiring metal will migrate while exchanging kinetic
`energy with the carriers. We have also found another
`problem that the wiring materials are broken by the
`so-called “stress migration” (which will be shortly re-
`ferred to as “SMD”), in which a strain is caused in the
`wiring materials by the stress coming from the inter-
`layer insulating films.
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide a
`semiconductor
`integrated circuit device which is
`equipped with a semiconductor memory circuit having
`a high storage capacity.
`Another object of the present invention is to provide
`a semiconductor integrated circuit device which com-
`prises a semiconductor memory circuit given a large
`storage capacity while speeding up the operation.
`Still another object of the present invention is to
`provide a method of efficiently relieving a defect of the
`semiconductor memory circuit given a large storage
`capacity.
`A further object of the present invention is to provide
`a semiconductor memory circuit which can prevent the
`EMD and SMD of the word shunting lines for the
`purpose of achieving high integration.
`To achieve these and other objects, a semiconductor
`memory device having a large storage capacity is con-
`structed by providing a plurality of macro-cellulated
`circuit blocks each including a memory array, an ad-
`dress selection circuit for the memory array, and a data
`input/output circuit. In the vicinity of the aforemen-
`tioned macro cells, therc are arranged external input-
`/output bonding pads, of which the bonding pads for
`feeding a signal are bonded with a coating wire by
`extending a common LOC (Lead on Chip) lead frame.
`In the memory cells, the word line backing lines and the
`bit lines are so rnulti-layered that the adjacent wiring
`lines may belong to different layers. The word lines
`and/or bit lines are alternately equipped at their ends
`with drivers and unit sense amplifiers. The number and
`operation time of the operation circuits are made differ-
`ent between a normal mode and a refresh mode. On
`condition that no defective bit is present at an address,
`the output of a non-defective portion of the two mem-
`ory chips is validated, or only the non-defective portion
`is accessed to. Such plural ones of the aforementioned
`defective chips which use only the non-defective por-
`tion are packaged in one package to provide an appar-
`ently complete product. The output signals of three or
`more odd memory chips or blocks having no defect at
`an address are outputted through a majority decision
`logic circuit.
`
`invention relates to a semiconductor
`The present
`integrated circuit device and a defect relieving method
`therefor and, more particularly, to technologies which
`are effective when used in a dynamic RAM (i.e., Ran-
`dom Access Memory) having a large storage capacity
`such as 64 Mbits, although the invention is not limited
`to this, and a defect relieving method therefor.
`There has recently been developed a dynamic RAM
`(which may be referred to as “DRAM”) which has a
`large storage capacity of about 16 Mbits. This dynamic
`RAM is exemplified on pages 67 to 81 of “Nikkei Micro
`Device” published on Mar.
`1, 1988 by NIKKEI
`McGRAW-HILL.
`A semiconductor memory device such as the DRAM I
`using MlSFETs includes a memory cell array having a
`plurality of memory cells arranged in a matrix form. In
`case data is to be written in or read out from an arbitrary
`memory cell of the DRAM, a row address decoder and
`a column address decoder select the row and column
`corresponding to address signals coming from the out-
`side to address that memory cell. In response to the
`selection signals from the row address decoder, the
`word driver drives the word line of the row to be se-
`lected to a selection level. The aforementioned word
`line acts as the gate electrode of the selected MISFET
`of the memory cell. The aforementioned gate electrode
`acts as a mask for forming the source or drain electrode
`of the selected MISFET by an ion implantation. The
`aforementioned gate electrode is made of polycrystal-
`line silicon, for example, because it has to stand the heat
`of the heat treatment after the ion implantation.
`To attain a higher degree of integration of the afore-
`mentioned semiconductor memory device, the memory
`cell array becomes larger so that the word lines become
`longer. Since the polycrystalline silicon has a high resis-
`tance, the word lines take an extremely high resistance
`so that the CR time constant is enlarged. This causes a
`delay in the signal transmission time from the word
`driver. Thus, it is possible to adopt the technology, by
`which word shunting lines made of a material having a
`low resistance such as aluminum are disposed close to
`and in parallel with the aforementioned word lines
`made of polycrystalline silicon so that the transmission
`delay of word line drive signals may be reduced by
`connecting the aforementioned word shunting lines and
`the aforementioned word lines.
`Incidentally, the word shunting lines are described in
`Japanese Patent Laid-Open No. l06693/ 1977.
`In accordance with the aforementioned large storage
`capacity, the memory chips are naturally large-sized.
`Accordingly,
`in a dynamic_ RAM having its storage
`capacity enlarged to about 64 Mbits, the signal transmis-
`sion speed is dropped as the wiring length is increased
`by making the elements (e.g. the wiring layer and the
`circuit elements) finer and by having the wiring lines
`lugged around-the chip. As a result, the DRAM in-
`tended to achieve the aforementioned high storage ca-
`pacity has to take into special consideration the drop in
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`According to the aforementioned means, a plurality
`of macro-cellulated memory circuits having the RAM
`function are used to construct the semiconductor mem-
`ory circuit having a large storage capacity so that the
`layout can be simplified and rationalized. The LOC
`leads are extended close to the aforementioned macro
`cells and bonded with the coating wires so that the
`signals can be inputted/outputted at a high speed. The
`memory cells can be arranged in high density by multi-
`layering the word line backing lines and the bit lines and
`by providing the two ends of the word lines and/or bit
`lines alternately with the drivers and the unit sense
`amplifiers. The numbers and operation times of the
`circuits are made different between the normal mode
`and the refresh mode so that the power consumption
`can be reduced. By using the non-defective portions of
`the two defective chips, moreover, one apparently com-
`plete memory chip can be formed. The defective bits
`can be invalidated by taking a majority decision of odd
`bits. The yield of the RAM can be enhanced by packag-
`ing those defective chips in a package.
`In another representative of the invention to be dis-
`closed herein,
`the adjacent word shunting lines are
`made of vertically offset different layers.
`The total undesired loads to be driven by the word
`drivers, such as the parasitic capacities or wiring resis-
`tors of the simultaneously selected ones of the laminated
`word shunting lines of the semiconductor memory de-
`vice are always equal at the selection step of each word
`line. In case the word shunting lines are made of two
`layers and in case an even number of word lines are
`simultaneously selected, the word shunting lines of the
`upper layer and the word shunting lines of the lower
`layer are paired so that one or more pairs of word shunt-
`ing lines are selected.
`Since the adjacent word shunting lines are formed of
`upper and lower different layers through an insulating
`film, it becomes unnecessary to form a spacing for the
`insulation between the aforementioned adjacent word
`shunting lines. As a result, the width of the word shunt-
`ing lines can be increased to the aforementioned spacing
`or more, for example, and an improvement in the resis-
`tance to the EMD or SMD can be achieved.
`If the adjacent word shunting lines are made of verti-
`cally different layers, as described above, the undesired
`loads of the word shunting lines of the lower layer are
`higher than those of the word shunting lines of the
`upper layer. In case the memory cell array is divided
`into a plurality of memory mats, the word shunting lines
`are driven, if simultaneously selected in each memory
`mat, by the word driver in accordance with the selec-
`tion signals of the address decoder. The aforementioned
`address decoder having the selection logic to keep con-
`stant the total loads of the plural word shunting lines to
`be simultaneously selected keeps constant the loads to
`be driven by the word driver, even in any addressing
`operation, to stabilize the accessing operation and war-
`rant the high-speed accms.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a fundamental block diagram showing one
`embodiment of the dynamic RAM of about 64 Mbits
`according to the present invention;
`FIG. 2 is a block diagram showing an embodiment of
`the dynamic RAM according to the present invention
`for implementing the arrangement shown in FIG. 1;
`FIG. 3 presents a circuit block showing a semicon-
`ductor integrated circuit device according to the pres-
`
`4
`cut invention and a fundamental layout showing one
`embodiment of the arrangement of the corresponding
`bonding pads;
`FIG. 4 presents a fundamental layout of the afore-
`mentioned semiconductor integrated circuit device and
`a pattern diagram showing one embodiment of the cor-
`responding LOC leads;
`FIGS. 5A to 5C are schematic pattern diagrams
`showing another embodiment of the aforementioned
`semiconductor chips and the LOC leads;
`FIG. 6 is an arrangement diagram showing the bond-
`ing pads according to another embodiment of the mac-
`ro-cellulated memory blocks according to the present
`invention;
`FIG. 7 is a fundamental layout diagram showing one
`embodiment of the semiconductor integrated circuit
`device using the memory group of FIG. 6;
`FIG. 8 is a block diagram showing one embodiment
`of one memory block to be macro-cellulated;
`FIG.-9 is a block diagram showing another embodi-
`ment of the memory block to be macro-cellulated;
`FIG. 10 is a schematic waveform chart for explaining
`the refreshing operations;
`FIG. 11 is a block diagram for explaining one em-
`bodiment of the address assignment of RAM in the
`embodiment of FIG. 3;
`FIG. 12 is a block diagram for explaining one em-
`bodiment of the refreshing operations of the dynamic
`RAM according to the present invention;
`FIG. 13 is a schematic circuit diagram showing one
`embodiment of the power down circuit shown in FIG.
`9;
`
`FIG. 14 is a section showing the element structure of
`one embodiment of the memory cell to be used in the
`dynamic RAM according to the present invention;
`FIG. 15 is a pattern diagram showing one embodi-
`ment of the connection portions between the word lines
`and the word shunting wiring lines;
`FIG. 16 is a schematic circuit diagram showing one
`embodiment of the memory cell array according to the
`present invention;
`FIG. 17 is a schematic circuit diagram showing an-
`other embodiment of the memory cell array according
`to the present invention;
`FIG. 18 is a section showing the element structure
`according to another embodiment of the memory cell;
`FIG. 19A is a layout showing one embodiment of the
`word lines and their drivers of the memory cell array
`according to the present invention;
`FIG. 19B is a layout showing another embodiment of
`the word lines and their drivers of the memory cell
`array according to the present invention;
`FIG. 20A is a layout showing another embodiment of
`the word lines and their drivers of the memory cell
`array according to the present invention;
`FIG. 20B is a layout showing another embodiment of
`the word lines and their drivers of the memory cell
`array according to the present invention;
`FIG. 20C is a layout showing another embodiment of
`the word lines and their drivers of the memory cell
`array according to the present invention;
`FIG. 21 is a schematic block diagram for explaining
`one embodiment of the defect relieving method accord-
`ing to the present invention;
`FIG. 22 is a schematic block diagram for explaining
`another embodiment of the defect relieving method
`according to the present invention;
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`MICRON ET AL. EXHIBIT 1067
`Page 37 of 59
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`5
`FIG. 23 is a schematic block diagram for explaining
`another embodiment of the defect relieving method
`according to the present invention;
`FIG. 24 is a schematic block diagram for explaining
`still mother embodiment of the defect relieving method 5
`according to the present invention;
`FIG. 25 is a schematic block diagram for explaining
`still another embodiment of the defect relieving method
`according to the present invention;
`FIG. 26 is a top plan view showing one embodiment 10
`of the multi package of stack type;
`FIGS. 27(A-D) are an enlarged perspective view of
`FIG. 26;
`FIG. 28 is a longitudinal section showing one exam-
`ple of the vertically different arrangement structure of 15
`the word shunting lines in the DRAM according to one
`embodiment of the present invention;
`FIG. 29 is a block diagram showing the whole struc-
`ture of the DRAM of FIG. 28;
`FIG. 30 is a top plan view showing a major portion of 20
`the memory mat of the DRAM;
`FIG. 31 is a section showing the memory cell portion
`of the major portion of the memory mat shown in FIG.
`30;
`FIG. 32 is a longitudinal section showing an essential 25
`portion of the DRAM having the stack type storage
`capacity element according to another embodiment of
`the present invention; and
`FIG. 33 is a longitudinal section showing the essential
`portion of the DRAM having the trench type storage
`capacity element according to still another embodiment
`of the present invention.
`DETAILED DESCRIPTION
`
`30
`
`FIG. 1 is a fundamental block diagram showing one
`embodiment of a dynamic RAM having a storage ca-
`pacity as large as about 64 Mbits, to which the present
`invention is applied.
`This embodiment performs the following devices in
`the arrangement of the memory array portion con-
`structing the _RAM and the peripheral portion for se-
`lecting the addresses of the former. The devices prevent
`the delay in the operating speed according to the elon-
`gation of the signal propagation delay time, which
`might otherwise be inevitable caused by elongating the
`various wiring lengths of control signals or memory
`array drive signals due to the increase in the chip size
`accompanying the increased capacity of the memory.
`The major circuit block of FIG. 1 are individually
`drawn in accordance with the geometrical arrangement
`of the practical semiconductor chip.
`The RAM of this embodiment is constructed such
`that a plurality of macro-cellulated memory blocks are
`arranged in a matrix form. One macro-cellulated mem-
`ory block is made to have a storage capacity of about 4
`Mbits. The shown embodiment is made to have a large
`storage capacity of about 64 Mbits as a whole by array-
`ing sixteen macro—ce1lulated memory blocks in four
`rows and in four columns.
`Each macro-cellulated memory block is equipped
`with: an address selector composed of address decoders
`and word line drivers of rows and columns for receiv-
`ing address signals fed through shared timing/address
`generators; a memory array; an internal timing genera-
`tor for generating time-series timing pulses necessary
`for the internal operations in accordance with an opera-
`tion mode; and an input/output circuit for writing/-
`reading data in and out of a selected memory cell. The
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`memory blocks specified above are matrix-arranged
`together with above-specified control circuit (i.e., the
`timing and address generator). This control circuit ex-
`changes signals with the individual memory blocks
`through signal buses. One embodiment of a control
`arrangement of the timing and address generator is
`shown in FIG. 2.
`Therefore, the dynamic RAM of this embodiment
`looks like a semiconductor memory device of board
`structure, in which one macro-cellulated memory block
`is deemed as one RAM.
`However, the overall RAM of this embodiment is
`constructed of one semiconductor integrated circuit
`and is quite different from the aforementioned structure
`in which the packaging substrate of the aforementioned
`board structure is merely replaced by a semiconductor
`substrate. This is because the semiconductor integrated
`circuit device includes a variety of technical problems,
`which are not experienced in the semiconductor mem-
`ory device of the board structure, such as the restriction
`on the chip size, as well as problems with the wiring
`layer, with power consumption, and with defect relief.
`In other words, one semiconductor integrated circuit
`device such as shown in FIG. 1 cannot be constructed
`before the aforementioned various technical problems
`are solved.
`In this embodiment, the overall layout and its control
`are simplified by macro-cellulating the memory block
`having the aforementioned memory functions. In short,
`the dynamic RAM having a scale of 64 Mbits can be
`formed by designing macro-cells having a storage ca-
`pacity of about 4 Mbits and by arranging the macro-
`cells in the number of 4X4.
`In the aforementioned control circuit (i.e., the timing
`and address generator of FIG. 1), moreover, the opera-
`tion mode is decided to form corresponding major tim-
`ing signals, and address signals are divided into internal
`address signals to be fed to the individual memory
`blocks and decoded memory block selection signals so
`that they are fed to macro-cellulated memory blocks
`through the aforementioned signal buses. The control
`circuit is equipped with a refresh control circuit includ-
`ing a refresh address generator for refreshing opera-
`tions.
`By taking this structure, the macro-cellulated mem-
`ory block can be made to have such a simplified circuit
`structure as in constructed of memory cells arranged in
`a matrix form, a selector and a data input/output circuit
`therefor. In the macro-cellulated memory block of this
`embodiment, more specifically,
`it is unnecessary, as
`opposed to a case of each DRAM being packaged in the
`memory device of the board structure, to provide an
`operation mode decision circuit, a corresponding timing
`signal generator (such as shown in FIG. 1), and a re-
`fresh control circuit including a refresh address genera-
`tor.
`
`In this embodiment, the power-supply voltage is set
`at a relatively low level such as about 3.3 V, although
`not limited thereto, so as to cope with the drops of the
`breakdown voltage and power consumption of the ele-
`ments due to the reduction of the element structure.
`This power-supply voltage may be established either by
`the structure, in which a power-supply circuit for drop-
`ping the voltage of about 5 V received from the outside
`is disposed inside, or by supplying the aforementioned
`voltage of about 3.3 V from the outside. In this case, the
`circuit requiring the selection level of the word line or
`the like or the level elevated with respect to the power-
`
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`MICRON ET AL. EXHIBIT 1067
`Page 38 of 59
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`

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`7
`supply voltage such as the selection signal for selecting
`a shared sense amplifier may be exemplified by a boot-
`strap circuit or operated with a voltage boosted in ad-
`vance.
`
`In order to further reduce the power consumption,
`the internal operation voltage may be dropped from the
`aforementioned voltage of about 3.3 V to 2 V or 1.5 V.
`If the circuit is operated with the aforementioned volt-
`age as low as 1.5 V, it can be easily backed up by a
`battery.
`FIG. 2 is a block diagram showing one embodiment
`of a control arrangement for the dynamic RAM accord-
`ing to the present invention.
`The individual circuit blocks of FIG. 2 are formed in
`one semiconductor substrate. The RAM of this embodi-
`ment has the aforementioned large capacity of about 64
`Mbits and is constructed of one semiconductor inte-
`grated circuit device, as has been described hereinbe-
`fore. Only three of the macro-cellulated memory blocks
`are shown for purposes of drawing simplification. Thus,
`the external terminals include an address signal terminal
`Ai (e.g., A0 to A12 in the address multiplex system), a
`row address strobe signal terminal ‘RT, a column ad-
`dress strcLbe_signal terminal C76, a write enable signal
`terminal WE and data signal terminals Din and Dout.
`An address signal is fed from the address signal termi-
`nal Ai to an address control circuit ADC contained in
`the control circuit. A row address strobe signal is fed
`from the terminal fi§ and is introduced into a row
`pre-timing generator RPTG. This row pre-timing gen-
`erator RPTG has its output signal fed to the aforemen-
`tioned address control circuit ADC, an operation mode
`decision circuit RDC for operation modes such as a
`normal mode, a refresh mode or a counter test mode,
`and a control circuit CONT2 including a generator for
`generating a memory block selection signal and major
`timing signals according to the operation mode and a
`refresh address counter. A column address strobe signal
`is fed from the terminal CE and is introduced into a
`column pre-timing generator CPTG. This column pre-
`timing generator CPTG has its output signal fed to the
`aforementioned address control circuit ADC, operation
`mode decision circuit RDC and control circuit
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`§_9_NT2. A write enable signal is fed from the terminal
`WE and is introduced into its pre-timing generator
`WPTG. This pre-timing generator WPTG has its out-
`put signal fed to the aforementioned address control
`circuit ADC, control circuit CONT2 and operation
`mode decision circuit RDC.
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`The address control circuit ADC usgs_t_he aforemen-
`tioned address strobe signals 'RTS and CAS to fetch the
`row and column address signals fed time—serially from
`the external terminal Ai. The address control circuit
`ADC inputs its specific address signals to a control
`circuit CONT1 and its remaining address signals to
`address buffers XAB and YAB. The address buffers
`XAB and