United States Patent [191
`Itoh et al.
`
`IlllllllllllllIllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`
`US005160998A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,160,998
`Nov. 3, 1992
`
`[54] SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`[75] Inventors: Junichi Itoh, Inagi; Kazuyuki Kurita,
`Yokohama, both of Japan
`[73] Assignee: Fujitsu Limited, Kanagawa, Japan
`[21] App]. No.: 780,564
`[22] Filed:
`Oct. 21, 1991
`
`[63]
`
`Related US. Application Data
`Continuation of Ser. No. 233,108, Aug. 15, 1988, aban
`doned.
`Foreign Application Priority Data
`[30]
`Aug. 18, 1937 [JP]
`Japan .............................. .. 62-203483
`
`_ [51] Int. Cl.5 ........................................... .. H01L 29/34
`
`[52] US. Cl. . . . . . . . . . . . . . . . .
`
`. . . . . .. 257/760; 257/633
`
`[58] Field of Search . . . . . . .
`
`. . . .. 357/ 71, 54, 52, 40,
`357/65
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,135,954 1/1979 Chang et a1. ................... .. 357/54 X
`
`4,365,264 12/1982 Mukai et al. . . . . . . . . .
`4,446,194 5/1984 Candelaria et a1. .
`
`. . . .. 357/52 X
`.... .. 357/54
`
`4,455,568 6/1984 Shiota . . . . . . . . . . . . . .
`
`. . . .. 357/54
`
`4,654,689 3/1987 Fujii . . . . . . . . . . . . .
`
`. . . .. 357/40
`
`4,825,277 4/1989 Mattox et a]. .................. .. 357/54 X
`
`FOREIGN PATENT DOCUMENTS
`
`0152794 8/1985 European Pat. Off. ............ .. 357/71
`0252179Al 1/1988 European Pat. Off. .
`51-117887 10/1976 Japan .
`52-28870 3/1977 Japan .
`52-115785 9/1977 Japan .
`55-19850 2/1980 Japan .
`57-45931 3/1982 Japan .
`0190043 11/1983 Japan ................................... .. 357/71
`61-279132 12/1986 Japan .
`
`OTHER PUBLICATIONS
`Ghandhi, S. VLSI Fabrication Principles, John Wiley
`and Sons, 1983, pp. 582-585.
`Claassen, W. A. P. “Ion Bombardment-Induced Me
`chanical Stress in Plasma-Enhanced Deposited Silicon
`Nitride and Silicon Oxynitride Films.” Plasma Chemis
`
`try and Plasma Processing, vol. 7, No. 1 (Mar. 1987), pp.
`109-124.
`Machida, Katsuyuki and Hideo Oikawa. “New Planari
`zation Technology Using Bias-ECR Plasma Deposi
`tion.” Japanese Journal of Applied Physics. supplements
`17th Conf. on Solid State Devices and Materials Aug.
`25-27, 1985, pp. 329-332.
`Patent Abstracts of Japan, vol. 6, No. 119 (E-l16) [997],
`Jul. 3 1982; and JP-A-57 45 931 (Fujitsu K. K.) Mar. 16,
`1982.
`11, No. 138
`Patent Abstracts of Japan, vol.
`(E-503)[2585], May 2, 1987; and JP-A-61 279 132
`(Sony Corp.) Dec. 9, 1986.
`Extended Abstracts, vol. 87-1, No. 1, Spring 1987, pp.
`366-367, No. 254, Philiadelphia, Pa. U.S.; M. Doki et
`al.: “ECR Plasma CVD of Insulator Films-Low Tem
`perature Process for Ulsi-”.
`Patent Abstracts of Japan, vol. 11, No. 390 (15-567)
`[2837], Dec. 19, 1987; and JP-A-62 154 642 (Matsushita
`Electronics Corp.) Sep. 7, 1987.
`Primary Examiner-Andrew J. James
`Assistant Examiner-Sara W. Crane
`Attorney, Agent, or Firm-Nikaido, Marmelstein,
`Murray & Oram
`ABSTRACT
`[57]
`A semiconductor device including a semiconductor
`substrate; a metal wiring layer formed on the semicon
`ductor substrate; a ?rst insulation layer formed on the
`metal wiring layer, the ?rst insulation layer being
`formed by a tensile stress insulation layer having a con
`tracting characteristic relative to the substrate; and a
`second insulation layer formed on the ?rst insulation
`layer, the second insulation layer being formed by a
`compressive stress insulation layer having an expanding
`characteristic relative to the substrate. The tensile stress
`- insulation layer is produced by thermal chemical vapor
`deposition or plasma assisted chemical vapor deposition
`which is performed in a discharge frequency range
`higher than 2 megahertz; and the compressive stress
`insulation layer is produced by plasma assisted chemical
`vapor deposition which is performed in a discharge
`frequency range lower than 2 megahertz.
`
`5 Claims, 6 Drawing Sheets
`
`43.2
`
`33
`
`32
`
`422
`421
`
`412 411
`
`31
`
`MICRON ET AL. EXHIBIT 1050
`Page 1 of 12
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`

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`US. Patent
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`Nov. 3, 1992
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`Sheet 1 of 6
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`5,160,998
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`MICRON ET AL. EXHIBIT 1050
`Page 2 of 12
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`US. Patent
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`Nov. 3, 1992
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`Sheet 2 of 6
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`5,160,998
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`MICRON ET AL. EXHIBIT 1050
`Page 3 of 12
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`

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`US. Patent
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`Nov. 3, 1992
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`Sheet 3 of 6
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`5,160,998
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`MICRON ET AL. EXHIBIT 1050
`Page 4 of 12
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`

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`US. Patent
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`Nov. 3, 1992
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`Sheet 4 of 6
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`MICRON ET AL. EXHIBIT 1050
`Page 5 of 12
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`

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`US. Patent
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`Nov. 3, 1992
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`Sheet 5 of 6
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`MICRON ET AL. EXHIBIT 1050
`Page 6 of 12
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`US. Patent
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`Nov. 3, 1992
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`Sheet 6 of 6
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`5,160,998
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`MICRON ET AL. EXHIBIT 1050
`Page 7 of 12
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`

`
`SEMICONDUCTOR DEVICE AND METHOD OF
`MANUFACTURING THE SAME
`
`This application is a continuation of application Ser.
`No. 233,108 ?led Aug. 15, 1988, abandoned.
`
`III
`
`BACKGROUND OF THE INVENTION
`(1) Field of the Invention
`The present invention relates to a semiconductor
`device and a method of manufacturing the same. More
`particularly, it relates to an improvement of a semicon
`ductor device having metal wiring layers and insulation
`layers formed on the metal wiring layers, and an im
`provement of the method of manufacturing the same.
`(2) Description of the Related Art
`Generally, in the conventional semiconductor device
`of the above type, the insulation layers formed on the
`metal wiring layers (e.g., aluminum wiring layers) are
`produced by chemical vapor deposition using insulation
`material such as phosphor silicated glass (PSG).
`In this method, however, during the formation of the
`above insulation layers, problems have arisen such as a
`disconnection of the metal wiring layers due to stress
`migration due to the effect of stress generated in the
`insulation layers, and cracks in the insulation layers.
`The present invention is intended to solve the above
`mentioned problems, and the main object of the present
`invention is to effectively prevent not only the discon
`nection of the metal wiring layers due to stress migra
`tion but also a generation of cracks in the insulation
`layers.
`
`15
`
`20
`
`25
`
`SUMMARY OF THE INVENTION
`To attain the above-mentioned object, according to
`one aspect of the present invention, there is provided a
`semiconductor device comprising a semiconductor sub
`strate; a metal wiring layer formed on the semiconduc
`tor substrate; a ?rst insulation layer formed on the metal
`wiring layer, the ?rst insulation layer being formed by a
`tensile stress insulation layer having a contracting char
`acteristic relative to the substrate; and a second insula
`tion layer formed on the ?rst insulation layer, the sec
`ond insulation layer being formed by a compressive
`stress insulation layer having an expanding characteris
`tic relative to the substrate.
`Also, according to another aspect of the present in
`vention, there is provided a semiconductor device com
`prising a semiconductor substrate; a plurality of metal
`wiring layers formed on the semiconductor substrate,
`the plurality of metal wiring layers comprising one or
`more lower side metal wiring layers having a small
`wiring width and one or more upper side metal wiring
`layers having a large wiring width; one or more ?rst
`insulation layers formed on the respective lower side
`metal wiring layers , each of the ?rst insulation layers
`being formed by a tensile stress insulation layer having
`a contracting characteristic relative to the substrate;
`and one or more second insulation layers formed on the
`respective upper side metal wiring layers, each of the
`second insulation layers being formed by a compressive
`stress insulation layer having an expanding characteris
`tic relative to the substrate.
`In addition, according to the present invention, there
`are provided methods for manufacturing the above
`mentioned semiconductor devices.
`As above-mentioned, the tensile stress insulation
`layer has a contracting characteristic relative to the
`
`35
`
`45
`
`55
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`65
`
`1
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`5,160,998
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`2
`substrate, and thus, when the tensile stress insulation
`layer T is formed on the semiconductor substrate S as
`shown in FIG. 1, the tensile stress insulation layer T
`causes the substrate S to bend in a direction such that
`the insulation layer T contracts relative to the substrate
`S (i.e., a direction such that the insulation layer T com- ,
`presses the metal wiring layer M formed on the sub
`strate S).
`On the other hand, the compressive stress insulation
`layer has an expanding characteristic relative to the
`substrate, and thus, when the compressive stress insula~
`tion layer C is formed on the semiconductor substrate S
`as shown in FIG. 2, the compressive stress insulation
`layer C causes the substrate S to bend in a direction such
`that the insulation layer C expands relative to the sub
`strate S (i.e., a direction such that the metal wiring layer
`M formed on the substrate S is expanded together with
`the insulation layer C when the metal wiring layer is
`heated by a current ?owing therethrough).
`Thus, according to one aspect of the present inven
`tion, by forming the tensile stress insulation layer T on
`the metal wiring layer M as the ?rst insulation layer, the
`insulation layer T applies stress to the metal wiring
`layer M, to compress the metal wiring layer as shown in
`FIG. 3, and as a result, a disconnection of the metal
`wiring layer due to stress migration is prevented. Also,
`by forming the compressive stress insulation layer C on
`the ?rst insulation layer T as the second insulation layer,
`as shown in FIG. 4, the compressive stress insulation
`layer tends to expand together with the expansion of the
`metal wiring layer when the metal wiring layer is
`heated, and thus the stress applied by the metal wiring
`layer to the insulation layer at that time is reduced, and
`as a result, a generation of cracks in the insulation layer
`is prevented.
`Also, according to another aspect of the present in
`vention, by forming the tensile stress insulation layers
`on the respective lower side metal wiring layers having
`a small wiring width (e.g., on the ?rst and the second
`metal wiring layers), a disconnection of the metal wir
`ing layers having a small wiring width due to stress
`migration is prevented. Also, by forming the compres
`sive stress insulation layers on the respective upper side
`metal wiring layers having a large wiring width (e.g.,
`on the third and the fourth metal wiring layers), a gen
`eration of cracks in the insulation layers due to the
`expansion of the metal wiring layers having a large
`wiring width is prevented. In this connection, with
`regard to the metal wiring layers having a large wiring
`width, a disconnection thereof due to stress migration
`need not be considered.
`As described in detail below, the tensile stress insula
`tion layer may be produced by thermal chemical vapor
`deposition (thermal CVD) or plasma assisted chemical
`vapor deposition (plasma CVD) performed in a dis
`charge frequency range higher than 2 megahertz. On
`the other hand, the compressive stress insulation layer
`may be produced by plasma assisted chemical vapor
`deposition (plasma CVD) performed in the discharge
`frequency range lower than 2 megahertz. Also, when
`the above tensile stress insulation layer or compressive
`stress insulation layer is formed by a particular plasma
`assisted chemical vapor deposition such that the above
`plasma is produced by electron cyclotron resonance
`(ECR plasma CVD), the surface of the corresponding
`insulation layer can be made flat, and thus ensure a high
`reliability of the metal wiring layers formed on the
`?attened surfaces of the insulation layers.
`
`MICRON ET AL. EXHIBIT 1050
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`4
`tion of the metal wiring layer 31. Then, as shown in
`In this connection, US Pat. No. 4,446,194 discloses a
`method of forming a dielectric layer having a compres
`FIG. 5(c), a compressive stress insulation layer 412 is
`sive stress (corresponding to compressive stress insula
`formed as a second insulation layer on the tensile stress
`tion layer) on the metal layer and forming a dielectric
`insulation layer 411. In this connection, the compressive
`layer substantially free of compressive stress (corre
`stress insulation layer 412 expands together with the
`sponding to the tensile stress insulation layer) on the
`metal wiring layer 31 when the metal wiring layer is _
`compressive stress insulation layer, to prevent a forma
`heated by a current ?owing therethrough, due to the
`tion of voids in the metal layers.
`expanding characteristic thereof relative to the sub
`strate, and thus stress applied by the metal wiring layer
`But, as shown in the experimental data described in
`detail below, a semiconductor device according to the
`to the insulation layer at that time is reduced, and as a
`present invention (i.e., a semiconductor device compris
`result, a generation of ‘cracks in the insulation layer is
`prevented.
`ing a tensile stress insulation layer formed on the metal
`layer and a compressive stress insulation layer formed
`In this connection, the tensile stress insulation layer
`on the tensile stress insulation layer) effectively pre
`411 can be formed by thermal chemical vapor deposi
`vents both a disconnection of the metal layers due to
`tion (thermal CVD) or plasma assisted chemical vapor
`deposition (plasma CVD). When the thermal CVD
`stress migration and a generation of cracks in the insula
`tion layers, compared with the device disclosed in the
`method is used, the insulation material such as phosphor
`above U.S.P. Namely, according to present invention,
`silicated glass (PSG) or silicon dioxide (SlOz) is depos
`the above-mentioned particular advantages can be ob
`ited on the metal wiring layer under the condition of a
`tained, which cannot be expected from the above
`reduced atmospheric pressure or standard atmospheric
`U.S.P.
`pressure, and a processing temperature range higher
`than 200° C., preferably from 300° C. to 450° C. When
`the plasma CVD method is used, the insulation material
`(the reaction gas) such as the above PSG, SiOg, SiON,
`Si3N4 or BPSG (boron-phosphor silicated glass), is de
`posited on the metal wiring layer by supplying a high
`frequency power having the discharge frequency range
`higher than 2 megahertz (e.g., 13.56 megahertz) be
`tween ?at electrodes arranged, for example, in parallel,
`one of which electrodes is connected to the substrate,
`under the processing temperature range of from 200' C.
`to 450° C.
`The plasma CVD method is used for forming the
`compressive stress insulation layer 412, and the insula
`tion material (the reaction gas) such as the above PSG,
`SiOg, SiON, Si3N4, or BPSG is deposited on the ?rst
`insulation layer by supplying a high frequency power
`having a discharge frequency range lower than 2 mega
`hertz (e.g., 200 kilohertz) between the above electrodes,
`under a processing temperature range of from 200° C. to
`450° C.
`Note, the above plasma CVD is of a type other than
`a plasma CVD wherein the plasma is produced by elec
`tron cyclotron resonance (ECR plasma CVD) as de
`scribed below.
`FIG. 6 is a diagram showing how the value of the
`stress generated in the insulation layer produced by the
`plasma CVD is changed in accordance with a change in
`the discharge frequency of the high frequency power
`supplied from a high frequency generator connected
`between the above electrodes used in the plasma CVD
`system. In FIG. 6, the abscissa corresponds to the dis
`charge frequency, and the ordinate corresponds to the
`value of the stress (using 10'' dyne/cmz, where n=8 for
`PSG, and n=9 for Si3N4, as a unit) generated in the
`insulation layer produced by the plasma CVD. This
`plasma CVD was performed by using the insulation
`material (reaction gas) of the above PSG and Si3N4.
`The value of the tensile stress generated in the insula
`tion layer is represented as a positive value, and the
`value of the compressive stress generated in the insula
`tion layer is represented as a negative value.
`The value of the stress becomes zero at the point
`where the discharge frequency is 2 megahertz, and the
`value of above tensile stress increases in accordance
`with the increase of the discharge frequency in the
`frequency range higher than 2 megahertz. On the other
`hand, the value of the above compressive stress in
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a drawing explaining a characteristic of the
`tensile stress insulation layer;
`FIG. 2 is a drawing explaining a characteristic of the
`compressive stress insulation layer;
`FIG. 3 is a drawing showing the tensile stress insula
`tion layer formed on the metal wiring layer as a ?rst
`insulation layer;
`FIG. 4 is a drawing showing the compressive stress
`insulation layer formed on the ?rst insulation layer as
`the second insulation layer;
`FIGS. 5(a) to 5(e) are drawings showing a process for
`manufacturing a semiconductor device according to a
`?rst embodiment of the present invention;
`FIG. 6 is a diagram showing how the value of the
`stress generated in the insulation layer produced by the
`plasma CVD is changed in accordance with the change
`of discharge frequency used in the plasma CVD system;
`40
`FIGS. 7(a) to 7(d’) are drawings showing a process
`for manufacturing semiconductor devices according to
`second and third embodiments of the present invention;
`FIGS. 8(a) to 8(h’) are drawings showing a process
`for manufacturing a semiconductor device according to
`a fourth embodiment of the present invention;
`FIG. 9 is a diagram showing experimental data re
`garding the generation of stress migration in various
`cases; and
`FIG. 10 is a diagram showing experimental data re
`garding the generation of cracks in the insulation layers
`in various cases.
`
`45
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`50
`
`55
`
`65
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIGS. 5(a) to 5(e) show a process for manufacturing
`a semiconductor device according to a ?rst embodi
`ment of the present invention. First, as shown in FIG.
`5(a), a ?rst metal wiring layer (e.g., aluminum wiring
`layer) 31 is formed on a semiconductor substrate 1 (e.g.,
`a silicon substrate) via a silicon insulation ?lm 2 (e.g., a
`silicon dioxide (SiOZ) ?lm). Next, as shown in FIG.
`5(b), a tensile stress insulation layer 411 is formed as a
`?rst insulation layer on the ?rst metal wiring layer 31.
`The tensile stress insulation layer 411 functions to com
`press the metal wiring layer 31, due to the contracting
`characteristic thereof relative to the substrate, and thus
`prevents stress migration which will cause a disconnec
`
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`creases in accordance with a decrease of the discharge
`frequency in the frequency range lower than 2 mega
`hertz. Namely, the tensile stress insulation layer is
`formed when the plasma CVD is performed at the dis
`charge frequency range higher than 2 megahertz, and
`the compressive stress insulation layer is formed at the
`discharge frequency range lower than 2 megahertz.
`These conditions remain unchanged even when the
`above ECR plasma CVD is adopted, instead of another _
`type of plasma CVD, for forming the insulation layer.
`10
`Then, as shown in FIG. 5(a'), a second metal wiring
`layer 32 is formed on the second insulation layer 412.
`When the above~mentioned steps are repeated, a tensile
`stress insulation layer 421 and a compressive stress insu
`lation layer 422 are successively formed on the second
`metal wiring layer 32, and a third metal wiring layer 33
`is formed on the above insulation layer 422 correspond
`ing to the second insulation layer.
`Then, in the above embodiment, the compressive
`stress insulation layer 432 is formed as a cover on the
`third metal wiring layer 33, as shown in FIG. 5(e), and
`subsequently, an anneal processing for the semiconduc
`tor device is carried out for about half an hour under a
`temperature of, for example, 450° C.
`FIGS. 7(a) to 7(d') show a process for manufacturing
`semiconductor devices according to second and third
`embodiments of the present invention; the step shown in
`FIG. 7(a) corresponds to that of the above FIG. 5(a).
`Next, in the second embodiment of the present inven
`tion, as shown in FIG. 7(b), a tensile stress insulation
`layer 411' is formed on the ?rst metal layer 31 as the ?rst
`insulation layer. This insulation layer 411' may be
`formed by the same means as used to form the tensile
`stress insulation layer 411 in the ?rst embodiment.
`Then, as shown in FIG. 7(c), a compressive stress insu
`lation layer 412’ is formed as the second insulation layer
`on the ?rst insulation layer 411'. The insulation layer
`412' is formed so that the surface thereof is made ?at.
`In this connection, the insulation layer 412' having
`the ?attened surface is formed by the above-mentioned
`ECR plasma CVD method.
`In this case, this ECR plasma CVD is carried out
`under the condition that the microwave power for pro
`ducing the ECR Plasma is, for example, 800 watts, and
`the discharge frequency and the output of the high
`frequency bias power applied between one electrode
`connected to the substrate and the other electrode (e.g.,
`the earth electrode) are, for example, 400 kilohertz and
`50 to 100 watts, respectively. Namely, as shown in FIG.
`6, even when the above ECR plasma CVD is adopted,
`the compressive stress insulation layer may be produced
`in a discharge frequency range of the above bias power
`which is lower than 2 megahertz. Under this condition,
`the insulation layer 412' is produced by using an insula
`tion material such as SiO2, PSG, SiON, Si3N4 or BPSG.
`Accordingly, the surface of the insulation layer 412‘
`may be ?attened, and then, as shown in FIG. 7(d), a
`second metal wiring layer 32 formed on the ?attened
`surface of the insulation layer 412'. Further, the above
`steps for forming the ?rst and second insulation layers
`60
`and the metal wiring layer may be successively repeated
`a predetermined number of times.
`Also, in the third embodiment of the present inven
`tion, after the ?rst step shown in FIG. 7(a), as shown in
`FIG. 7(b'), a tensile stress insulation layer 411" is
`formed as the ?rst insulation layer on the ?rst metal
`wiring layer 31, in such a manner that the surface of the
`insulation layer 411” is made ?at.
`
`6
`As above-mentioned, the insulation layer 411" having
`a ?attened surface, is formed by the above ECR plasma
`CVD method. In this case, this ECR plasma CVD is
`carried out under the condition that the above micro
`wave power for producing the ECR plasma is, for ex
`ample, 800 watts, and the discharge frequency and the
`output of a high frequency bias power applied between
`the above electrodes, one of which electrodes is con
`nected to the substrate, are, for example, 13.56 mega
`hertz and 50 to 100 watts, respectively. Namely, as
`shown in FIG. 6, even when the above ECR plasma
`CVD is adopted, the tensile stress insulation layer may
`be produced in the discharge frequency range of the
`above bias power, which is higher than 2 megahertz.
`Under this condition, the insulation layer 411” is pro
`duced by using the insulation material such as PSG,
`SiOZ, SiON, Si3N4 or BPSG.
`Then, as shown in FIG. 7(c'), a compressive stress
`insulation layer 412" is formed as the second insulation
`layer on the ?attened surface of the insulation layer
`411". The insulation layer 412" may be formed by the
`same means used to form the compressive stress insula
`tion layer 412 in the ?rst embodiment. The surface of
`the insulation layer 412", which is formed on the ?at
`tened surface of the insulation layer 411" also may be
`?attened. Then, as shown in FIG. 7(d’), a second metal
`wiring layer 32 is formed on the ?attened surface of the
`insulation layer 412". Further, the above steps for form
`ing the ?rst and second insulation layers and the metal
`wiring layer can be successively repeated a predeter
`mined number of times.
`Thus, according to the second and third embodi
`ments of the present invention, since each of the metal
`wiring layers is formed on the ?attened surface of the
`corresponding insulation layer, a high reliability of the
`metal wiring layers is ensured.
`FIGS. 8(a) to 8(h’) show a process for manufacturing
`a semiconductor device according to a fourth embodi
`ment of the present invention. In this embodiment, a
`plurality of metal wiring layers are provided, the tensile
`stress insulation layer is formed on each of lower side
`metal wiring layers having a small wiring width, and
`the compressive stress insulation layer is formed on
`each of upper side metal wiring layers having a large
`wiring width.
`Namely, in this embodiment, the tensile stress insula
`tion interlayers 41 and 42 are formed on the ?rst and
`second metal wiring layers 31 and 32 having small wir
`ing widths l1 and 12, respectively, to prevent disconnec
`tion of the metal wiring layers having the small wiring
`widths due to stress migration. In this connection, the
`tensile stress insulation layers may be formed by the
`same means used to form the tensile stress insulation
`layers in the above ?rst embodiment.
`Also, the compressive stress insulation layers (inter
`layers and a cover) 43, 44, and 45 are formed on the
`third, fourth, and ?fth metal wiring layers 33, 34, and 35
`having large wiring widths l3, l4, and 15, respectively. In
`this connection, it is not necessary to consider discon
`nection of the metal wiring layers having the large
`wiring widths 13 to 15, due to stress migration. Accord
`ingly, as above-mentioned, the compressive stress insu
`lation layers are formed on the metal wiring layers
`having the large wiring widths, to prevent the genera
`tion of cracks in the insulation layers, due to expansion
`of the metal wiring layers having the large wiring
`widths. The compressive stress insulation layers also
`may be formed by the same means used to form the
`
`45
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`50
`
`55
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`65
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`MICRON ET AL. EXHIBIT 1050
`Page 10 of 12
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`

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`15
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`25
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`5,160,998
`7
`8
`compressive stress insulation layers in the above ?rst
`layers is formed only by the tensile stress insulation
`embodiment.
`layer produced by thermal CVD, and marks “O”
`In this connection, in the above semiconductor de
`along a line “d” correspond to test data in the case
`vice having a plurality of metal wiring layers, one or
`wherein each of the insulation interlayers is formed only
`more metal wiring layers having the small wiring
`by the compressive stress insulation layer produced by
`widths (e.g., signal lines) are formed with a high wiring
`plasma CVD. Further, marks “El” along a line “b”
`density as the lower side metal wiring layers (in the
`correspond to test data in the case wherein each of the ’
`insulation interlayers comprises the compressive stress
`above case, as the ?rst and second metal wiring layers),
`and the remaining metal wiring layers having the large
`insulation layer as the ?rst insulation layer and the ten
`wiring widths (e.g., power supply lines) are formed
`sile stress insulation layer formed on the compressive
`with a low wiring density as the upper side metal wiring
`stress insulation layer as the second insulation layer, as
`layers (in the above case, as the third to ?fth metal
`shown in the above US. Pat. No. 4,446,194, and marks
`wiring layers).
`“A” along a line “a” correspond to test data in the case
`wherein each of the insulation interlayers comprises the
`In FIGS. 8(a) to 8(h’), the steps shown in FIG. 8(a)
`and FIG. 8(b) correspond to those of FIG. 5(a) and
`tensile stress insulation layer as the ?rst insulation layer
`FIG. 5(b), respectively.
`and the compressive stress insulation layer formed on
`Next, as shown in FIG. 8(0), the second metal wiring
`the tensile stress insulation layer as the second insulation
`layer 32 having the wiring width 12 is formed on the
`layer, as in the present invention.
`tensile stress insulation interlayer 41, and as shown in
`As shown in FIG. 9 it is apparent that the construc
`FIG. 8(d), the tensile stress insulation interlayer 42 is
`tion according to the present invention is remarkably
`effective for preventing stress migration, compared to
`again formed on the metal wiring layer 32. Next, as
`shown in FIG. 8(e), the third metal wiring layer 33
`other cases.
`having the wiring width 13, which is larger than the
`FIG. 10 shows experimental data regarding the gen
`‘above 11, and 12, is formed on the insulation interlayer
`eration of cracks in the insulation layers in various
`42, and as shown in FIG. 8(/), the compressive stress
`cases.
`insulation interlayer 43 is then formed on the metal
`In FIG. 10, test data I corresponds to the case
`wiring layer 33. Next, as shown in FIG. 8(g), the fourth
`wherein the insulation interlayers formed on the ?rst,
`metal wiring layer 34 having the wiring width 14, which
`second, and third metal wiring layers are all formed
`only by the tensile stress insulation layers T, and only
`is also larger than 11, and 12, is formed on the insulation
`interlayer 43. The above steps are repeated a predeter
`the cover formed on the fourth metal wiring layer is
`formed by the compressive stress insulation layer C.
`mined number of times, and ?nally, as shown in FIG.
`8(h), the compressive stress insulation layer 45 is formed
`Also, test data III corresponds to the case wherein the
`as the cover on the ?fth metal wiring layer 35 having,
`insulation interlayers formed on the ?rst and second
`for example, the wiring width 15 which is also larger
`metal wiring layers are formed only by the tensile stress
`than 11, and 12.
`insulation layers T, and the insulation interlayer formed
`FIG. 8(h') shows another typical construction of the
`on the third metal wiring layer comprises the compres
`semiconductor device according to the above fourth
`sive stress insulation layer C as a ?rst insulation layer
`embodiment of the present invention. This semiconduc
`3-1 of the corresponding insulation interlayer and the
`tor device comprises four metal wiring layers including
`tensile stress insulation layer T formed on the ?rst insu
`two lower side metal wiring layers (i.e., the ?rst and
`lation layer 3-1 as a second insulation layer 3-2 of the
`second metal wiring layers 31 and 32 having small wir
`corresponding insulation interlayer, as shown in the
`ing widths l1’ and 12', respectively) and two upper side
`above U.S.P., and the cover formed on the fourth metal
`metal wiring layers (i.e., the third and fourth metal
`wiring layer is formed by the compressive stress insula
`wiring layers 33 and 34 having large wiring widths l3’
`tion layer C. These test data I and III show that, accord
`and 14’, respectively). The tensile stress insulation inter
`ing to the above constructions, it is impossible to pre
`layers 41 and 42 are formed on the above lower side
`vent the generation of cracks in the insulation layers, as
`metal wiring layers 31 and 32, respectively, and the
`shown by marks “X”.
`compressive stress insulation layers (an interlayer and a
`On the other hand, test data II corresponds to the
`cover) 43 and 44 are formed on the above upper side
`case wherein the insulation interlayers formed on the
`metal wiring layers 33 and 34, respectively. The tensile
`?rst and second metal wiring layers (i.e., the metal wir
`ing layers having the small wiring width) are formed by
`stress insulation layers and the compressive stress insu
`the tensile stress insulation layers T, and the insulation
`lation layers may be formed by the same means used to
`form the tensile stress insulation layers and the compres
`interlayer formed on the third metal wiring layer and
`sive stress insulation layers in the above ?rst embodi
`the cover formed on the fourth metal wiring layer (i.e.,
`the insulation inter