MICRON ET AL. EXHIBIT 1040
`
`Page 1 of 345
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`MICRON ET AL. EXHIBIT 1040
`Page 1 of 345
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`

`
`SILICON PROCESSING
`FOR
`THE VLSI ERA
`VOLUMEl:
`PROCESS TECHNOLOGY
`
`MICRON ET AL. EXHIBIT 1040
`Page 2 of 345
`
`

`
`.I
`
`SILICON PROCESSING
`FOR
`THE VLSI ERA
`
`VOLUMEl:
`
`PROCESS TECHNOLOGY
`
`STANLEY WOLF Ph.D.
`Professor, Department of Electrical Engineering
`California State University, Long Beach
`Long Beach. California
`and
`Instructor, Engineering Exrension. University of California, Irvine
`
`RICHARD N. TAUBER Ph.D.
`Manager of VI.SI Fabrication
`TRW- Microelectronics Cenrer
`Redondo Beach, California
`and
`Instructor, Engineering Extension, University of'California, Irvine
`
`lATIICE
`PRESS
`Sunset Beach, California
`
`MICRON ET AL. EXHIBIT 1040
`Page 3 of 345
`
`

`
`DISCLAIMER
`
`This publication is based on sources and infonnation believed to be reliable, but the authors and
`disclaim any warranty or liability based on or relating to the contents of this
`Lattice Press
`publication.
`
`Published by:
`
`Lattic:e Press
`Post Office Box 340
`Sunset Beach, California 90742, U.S.A.
`
`Cover design by Roy Montibon and Donald Strout, Visionary Art Resources, Inc., Santa Ana, CA.
`
`Copyright © 1986 by Lattice Press
`All rights reserved. No part of this book may be reproduced or transmitted in any fonn or by any
`means, electronic or mechanical, including photocopying, recording or by any information storage
`and retrieval system without written permission from the publisher, except for the inclusion of
`brief quotations in a review.
`
`Library or C.ongress Cataloging in Publication Data
`Wolf, Stanley and Tauber, Richard N.
`
`Silicon Processing for the VLSI Era
`Volume 1 : Process Technology
`
`Includes Index
`1. Integrated "circuits~ Very large scale
`integration. z.· Silicon.
`I. Title
`
`86·081923
`
`987654
`
`PRINTED INTIIE UNTIED STATES OF AMERICA
`
`To my wife, Carrol Ann,
`and my children, Jennifer Laura and Stanley Charles Ross
`
`Stanley Wolf
`
`To my wife, Barbara
`
`Richard N. Tauber
`
`MICRON ET AL. EXHIBIT 1040
`Page 4 of 345
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`

`
`PREFACE
`
`SILICON PROCESSING FOR THE VLSI ERA is a text designed to provide a
`comprehensive and up-to-date treatment of this important and rapidly changing field. The text
`will consist of two volumes of which this book is i:he first, subtitled, Process Technology.
`Volume 2, subtitled, Manufacturing Technology is scheduled for publication in 1988. In this
`first volume, the individual processes utilized in the fabrication of silicon VLSI circuits are
`covered in depth (e.g. epitaxial growth, chemical vapor and physical vapor deposition of
`amorphous and polycrystalline films, thermal oxidation of silicon, diffusion. ion implantation,
`microlithograpby, and etching processes). In addition. chapters are also provided on technical
`subjects that are common to many of the individual processes, such as vacuum technofogy,
`properties of thin films, material characterization for VLSI, and the structured design of
`experiments for process optimization. The topics covered in the book are listed in more detail in
`In Volume 2, Manufacturing Technology, other issues related to VLSI
`the Table of Contents.
`fabrication such as process integration, process simulation, manufacturing yield, VLSI
`manufacturing facilities, assembly, packaging, and testing will be covered.
`The purpose of writing this text was to provide professionals involved in the
`microelectronics industry with a single source that offers a complete overview of the technology
`associated with the manufacrure of silicon integrated circuits. Other texts on the subject are
`available only in the form of specialized books (i.e. that treat just a small subset of all of the
`processes), or in the form of edited volumes (i.e. books in which a group of authors each
`contributes a small portion of the contents). Such edited volumes cypically suffer from a lack of
`unity in the presented material from chapter-to-chapter, as well as an unevenness in writing style
`In addition, in multi-disciplinary fields, such as microelectronic
`and level of presentation.
`fabrication, it is difficult for most readers to follow technical arguments in such books, especially
`if the information is presented without defining each technical "buzzword" as it is frrst introduced.
`In our book we hope to overcome such drawbacks by treating the subject of VI.SI fabrication
`from a unified and more pedagogical. viewpoint. and by being careful to define technical terms
`when they are first used. The result is intended to be a user friendly book for workers who have
`come to the semiconductor industry after having been trained in but one of the many traditional
`technical disciplines.
`-
`'
`An important technical breaktln'ough has occurred in publishing, that the authors also felt
`could be exploited in creating a unique book on silicon processing. That is, revolutionary
`electronic publishing techniques have recently become available, which can cut the time required
`to produce a published book from a finished manuscript This task traditionally took 15-18
`months, but can be now reduced to less than 4 months. If traditional techniques are used to
`produce books in such fast-breaking fields as VLSI fabrication, these books automatically
`possess a built-in obsolescence, even upon being first published. The authors took advantage
`of the rapid produclion techniques, and were able to successfully meet the reduced production(cid:173)
`time schedule. As a result. lhey were able to include infonnation contained in technical journals
`vii
`
`MICRON ET AL. EXHIBIT 1040
`Page 5 of 345
`
`

`
`extended to Mark Miscione for bringing valuable technical input on the subject of the physics of
`microlithogii!.phy, to Susan CUny for donating SEM photographs, and to Andrew Coulson for
`creating some of the drawings. Ada Mae Hardeman, of the Engineering Extension of the
`University of California, Irvine is owed special thanks for helping to make a success of the
`seminar from which this book grew. Otto Gruneberg, ofQBI, Inc. was also a benefactor of the
`project. He graciously agreed to share his exhlbition space with Lattice Press at Semicon-West,
`1986, where the book made its debut
`Superlative computer support and access to computer resources was generously made
`available by Donald E. Carlile, Harry T. Hayes, and Dale Lambertson of the Personal Computer
`Support Section of the Electronic Systems Group of TRW. Henry Nicholas was a computer
`expert and friend who lit the fue of inspiration that led to the undertaking of the project. The
`management of the Electronics Systems Group and the Microelectronics Center of TRW,
`including most notably Dr. Barry Dunbridge and Phillip Reid, are warmly thanked for providing a
`supportive environment, conducive to producing such an intensive technical project They made
`available technical literature and other resources to the authors, especially S. Wolf, who was able
`to avail himself of this generosiJY while writing during a Sabbatical leave from his reaching
`duties at California State University, Long Beach. Roy Montibon and Donald Strmlt of
`Visionary Art Resources, Inc., Santa Ana, CA designed the cover. Finally, we wish to thank
`Shirley Rome, Carrol Ann Wolf, and Barbara Tauber for typing the manuscript.
`
`Stanley Wolf and Richard N. Tauber
`
`P.S. Additional copies of the book can be obtained from:
`
`Lattice Press,
`P.O. Box 340-V
`Sunset Beach, CA, 90742
`
`An order form, for your convenience, is provided on the final leaf of the book.
`
`viii
`
`PREFACE
`
`and conferences which was available within four months of the book's publication date. Earlier
`books written on silicon processing, unfortunately, suffer from having had to undergo an 15-18
`month production cycle. This is tlu! first book on the subject in which such time-delay effects
`have been eliminaledfrom the prodaction process!
`Written for the professional, the book belongs on the bookshelf of workers in several
`microelectronic disciplines. Microelectronic fabrication engiMers who seek to develop a more
`complete perspective of the subject, or who are new to the field, will find it invaluable.
`Integrated circuit designers, test engineers, and integraJed circuit equipmenJ designers, who must
`understand VI.SI processing issues to effectively interface with the fabrication environment, will
`also find it a uniquely useful reference. The boOk should also be very suitable as a text for
`graduate-level courses on silicon processing techniques, offered to students of electrical engin(cid:173)
`eering, applied physics, and materials science. It is assumed that such students already possess a
`basic familiarity with semicOnductor device physics. Problems are included at the end of each
`chapter to assist readers in gauging how well they have assimilated the material in the text
`The book is an outgrowth of an intensive seminar conducted by the authors through the
`In the fU"St three years that it
`Engineering Extension of the University of California, Irvine.
`was offered, over three hundred engineers and managers from more than 75 companies and
`government agencies, enrolled in the coUJSe. Its fine reputation is attested to by the fact that
`many firms have sent participants each time the course has been offered, presumably based on the
`recommendations of earlier enrollees.
`In setting out to create a comprehensive text on VLSI fabrication, the aulhors each
`contributed a set of unique and complementary skills to the project.
`Professor Wolr's
`proficiency as a teacher and writer were utilized to produce a clearly written and logically
`organized book. Some of this expertise was gained in authoring an earlier beSt-selling text
`Electronic Measurements and Laboratory Practice, Prentice-Hall, 1983. Dr. Tauber brought a
`technical expertise acquired from his long involvement in the semiconductor industry. He used
`this background to insure that the most important topics of VLSI fabrication were addressed, and
`that the information was up-to-date and presented in a technically correct fashion. Note that for
`over twenty years, Dr. Tauber has held positions at Bell Telephone Laboratories, Xerox, And
`Hughes Aircraft Company. Currently he directs advanced VLSI Fabrication efforts at the
`Microelectronics Center of TRW. The labor of the writing effort was divided between the
`authors in the following manner: Professor Wolf was responsible for writing Chapters 1, 2, 3,
`9, 10, 12, 13, 15, 16, 17, and 18, and Dr. Tauber undertook the writing of Chapters 4, 5, 7, 8,
`11, and 14. Material for Chap. 6 was jointly contributed by Andrew R. Coulson and nr:Tauber.
`A book of this length and diversity would not have been possible without lhe indirect and
`direct assistance of many other workers. To begin with, virtually all of the information presented
`in this text is based on the research efforts of a countless number of scientists and engineers.
`Their contributions are recognized to a small degree by citing some of their articles in the
`references given at' the end of each chapter. The direct help came in a variety of forms, and was
`generously provided by many people. The text is a much better work as a result of this aid, and
`the authors express heartfelt thanks to those who gave' of their time, energy, and intellect.
`Each of the chapters was reviewed after the writing was completed. The engineers and
`scientists who participated· in this review were numerous. Special thanks are given to Leonard
`Braun and Ethelyn Motley, who provided extensive and incisive editing services. We also thank
`Warren Flack, Stephen Franz, Kenneth Tokunaga, Dean Denison, Simon Prussin, and Vitus
`Matare for their critical reviews. Simon Prussin also provided clarification of many concepts
`duri11g the course of numerous technical discussions with the authors, and can be rightly
`considered as bei11g the technical underpining of Chapters 1, 2, 8, and 9. Extra thanks are also
`
`MICRON ET AL. EXHIBIT 1040
`Page 6 of 345
`
`

`
`PREFACE
`
`PROLOGUE
`
`CONTENTS
`
`vii
`
`xxi
`
`1. SILICON: SINGLE-CRYSTAL GROWTH AND WAFERING
`
`• TERMINOLOGY OF CRYSTAL STRUC11JRE, I
`- MANUFACTIJRE OF SINGLE-CRYSTAL SILICON, 5
`From Raw Material to Electro11ic Grade Polysilicon
`CZOCHRALSKI (CZ) CRYSTAL GROwrH, 8
`Czochroiski Crystal Growth Seq~Unce
`/ncorporalion of /mpun'tJ'e.r into the Crystal (Normal Freezing)
`Modijicatioru Encolllltered to Nornwl Freezing in CZ Growth
`Czoclvalski Silicon Growing Equipment
`Malysis of Czochralski Sl1lcon l11 Ingot Form
`Measuri11g O:rygen a"d Carbon. in Silicon Using Infrared Absorbance Spectroscopy
`- FLOAT-ZONE SINGLE-CRYSTAL SlllCON, 21
`- FROM INGOT TO FINISHED WAFER: SUCING; ETCHING; POLISHING, 23
`• SPECIFICATIONS OF Sill CON WAFERS FOR VLSI, 26
`- TRENDS IN SILICON CRYSTAL GROwrH AND VLSI WAFERS, 30
`
`2. CRYSTALLINE DEFECTS, THERMAL PROCESSING,
`AND GETTERING
`
`36
`
`CRYSTALLINE DEFECTS IN SiLICON, 37
`Point Defects
`One·DimeruioiUJl Defects (Dislocalions)
`Area Defects (Stad:ing Faults)
`Bulk Defecl.l Qlld Precipitation
`INFLUENCE OF DEFECTS ON DEVICE PROPERTIES, 51
`LeakJJge Currents il'l pn JunctiOI1S
`Collector·Emitter Le.aJ:age in Bipolar Transistors
`Minority Carrier U{£tinr.es
`Gate OxitU Quality
`Tltreshold Voltage Colllrol
`Wafer Resistance to Warpage
`
`MICRON ET AL. EXHIBIT 1040
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`
`

`
`CONTENTS
`
`CONTENTS
`
`xili
`
`124
`
`- OIARACfERIZATION OF CRYSTAL DEFECTS, 55
`- TIIERMAL PROCESSING, 56
`Rapid The.rmal Processing (RTP) .
`- OXYGEN IN SJUCON, 59
`- GETI'ERING, 61
`Basic Gettering Pinciples
`Extrinsic Getteri11g
`lntrituic Getterhtg
`
`3. VACUUM TECHNOLOGY FOR VLSI APPLICATIONS
`
`73
`
`- FUNDAMENTAL CONCEPTS OF GASES AND VACUUMS, 73
`Presswe Uflits
`Pres:riUe RtJ11ges
`Metlll Free Palh tllld Gas Flow Regimes
`- LANGUAGE OF GAS /SOLID INTERACTIONS, 77
`- TERMINOLOGY OF VACUUM PRODUCTION AND PUMPS, 78
`- ROUGHING PUMPS, 85
`Oil..Seoled Rotary MechtJIIicol Pumps
`PIIIPip Oils
`Roots Pump:
`- HIGH VACUUM PUMPS t DIFFUSION PUMPS, 89
`- HIGH VACUUM PUMPS II: CRYOGENIC PUMPS, 92
`- HIGH VACUUM PUMPS ill: TURBOMOLECULAR PUMPS, 95
`- SPECIFICATION OF VACUUM PUMPS FOR VLSI, 97
`- TOTAL PRESSURE MEASUREMENT, 97
`- :MEASUREMENTS OF PARTIAL PRESSURE: Residual Gas Analyzers, 101
`Operaliort of Residual Gas Analyzers (RGA)
`RGAz 011d Non-High Vac&UU~~ Applicatior~:: Differential Pwnping
`lr~terpretalio11 of RGA Spectra
`RGA SpecifJ.Calior~ List
`- HIGH-GAS FLOW VACUUM ENVIRONMENTS IN YLsi PROCESSING, 104
`MediiUII tl1ld Low-Vacwun Systems
`Throttled High-Va&11.1U11 Systems
`
`4. BASICS OF THIN FILMS
`
`109
`
`- THIN FILM GROWTH, 110
`- STRUCTURE OF THIN FILMS, 111
`- MECHANICAL PROPERTIES OF THIN FILMS, 113
`
`Stress in Thin Films
`Other Mecluutical Properties
`- ELECTRICAL PROPERTIES OF METALLIC THIN FILMS, 118
`Electrical TrlUisport in Thill Films
`
`5. SILICON EPITAXIAL FILM GROWTH
`
`-FUNDAMENTALS OFEPITAXIALDEPOSIDON, 125
`The Grove Epita:dol Modd
`Gas PluJse Mass Trtm.r{er
`Atotrdstic Model Of EpitaxWI Growth
`- OIEMICAL REACTIONS USED IN SILICON EPITAXY, 133
`- DOPINGOFEPITAXIALFILMS,I36
`Inte/'IJioMl Dopi11g
`Amodoping and Solid-Stale. Diffusion
`- DEFECTS IN EPITAXIAL FILMS, 139
`Defects lrr.du.ce.d Dwing Epilaxlal Deposition mtd their Nu.ckation Mechanis1113
`Tt.chralque:s for Redudng Defects in Epitaxial Films
`- PROCESS CONSIDERATIONS FOR EPITAXIAL DEPOSIDON, 142
`Paltern Shift, Distortion, tJIId WMIIDIU'
`- EPITAXIALDEPOSIDONEQUIPMENT, 145
`- OIARACTERIZATION OF EPITAXIAL FILMS, 147
`Optical Inspectiort of Epittuial Films
`ELectrical Chara&terizallon
`EpltaxUll Film Tllicbess Mea.rUTements
`lnfrtJ1'ed Reflectance MeaJwe~Mfll T1u:M.iques
`- SJUCON ON INSULATORS, 151
`Silicon 011 Sapphire
`Silicon on OtMr InslllaJors
`- MOLECULARBEAMEPITAXYOFSILICON,I56
`
`6. CHEMICAL VAPOR DEPOSITION OF AMORPHOUS
`AND POLYCRYSTALLINE FILMS
`
`161
`
`- BASIC ASPECTS OF OIEMICAL VAPOR DEPOSIDON, 162
`OIEMICAL VAPOR DEPOSIDON SYSTEMS, 164
`Compor~effls of Geturic CVD Systems
`TermiMlogy ofCVD Reactor De:igrt
`~osplteric Pre:swe CVD Reactors
`Low-Pre:uwe CVD Reactor:
`PlMma-ENt.QIICed CVD: Physics; Clu.mistry; a11d ReaciOr C011figuralio1U
`Photon-INlMCed CVD Reactors
`- POLYCRYSTALLINE SJUCON: PROPERTIES AND CVD DEPOSIDON, 175
`Properties of Poly:iUcon Fi1nu
`CVD of POI)'silicon
`Dopiltg Teclr.l'liqus for Poly:ill'con
`O:xidalion of Polysilicot~
`- PROPERTIES AND DEPOSIDON OF CVD SiOz FilMS, 182
`CMmicol ReactiofU for CVD Formalion
`Step Coverage of CVD Si02
`U'ftdoped CVD Si02
`
`MICRON ET AL. EXHIBIT 1040
`Page 8 of 345
`
`

`
`xiv
`
`CONTENTS
`
`CONTENTS
`
`Phosplr.osilicaJe Glass
`Boroplr.osphosilictJJe Glass
`- PROPERTIES AND CVD OF SILICON NITRIDE FilMS, 191
`- OTIIER FilMS DEPOSITED BY CVD (OXYNITRIDES and SIPOS), 195
`
`7. THERMAL OXIDATION OF SINGLE-CRYSTAL SILICON 198
`
`-PROPERTIES OF SILICA GLASS, 199
`- OXIDATION KINETICS, 200
`The L~ear-Porabolic Model
`- TilE INITIAL OXIDATION STAGE, 207
`Growth o[Titin O:ddu
`- TIIERMAL NITRIDATION OF SILICON AND Si02, 210
`- FACTORS WHICH AFFECT TilE OXIDATION RATE, 211
`O:ddation Growth RaJes: Crystal OrierltaJion Dependence
`O:x:ldaJion Growth RaJes: Dopwll Effects
`O:ddaJion Growth Rates: Water (H20) Dependertee
`Oxidation Growth Rales: Chlorine Dependence
`O:ddalitm growth Rales: PressJUe Effects
`Oxidation Growth RaJes: Plasma and Photon Effects
`- MASKING PROPERTIES OF TI!ERMALL Y GROWN SiO,, 219
`- PROPERTIES OF TilE Si /Si02 INTERFACE AND OXIDE TRAPS, 220
`lnlerface Trap Cluuge
`FW!d O::dde Charge
`Mobik Ionic Charge
`O:xlde. Trapped Charge
`NaJure of the Si JSi02 Interface
`- STRESS IN Si02, 228
`- DOPANT IMPURITY RJIDISTRIBUTION DURING OXIDATION, 228
`- OXIDATION SYSTEMS, 230
`HorizorttoJ Fllnflk:es
`Sw[iended Loading System3
`Vertical FIUrtaces
`- MEASUREMENT OF OXIDE TlllCKNESS, 234
`
`8. DIFFUSION IN SILICON
`
`242
`
`- MATIIEMATICS OF DIFFUSION, 242
`FicJ:.r First Law
`Ficb Second Law
`Solidiort.r to Fidu Second Law
`CortcerttrtJlion Depertdl.nce of the Diffwion Coefficient
`- TEMPERATURE DEPENDENCE OF TilE DIFFUSION COEFFICIENT, 250
`- DIFFUSION CONSTANTS OF TilE SUBSTITUTIONAL
`IMPURITIES: B; As; and P, 251
`ATsenlc Dijfwion
`
`Bor011 Di/fwlo11
`Phospltbrus DijJIUion
`- ATOMISTIC MODELS OF DIFFUSION IN SILICON, 256
`The VacaltC)I Model
`The Vactlllcy-lnterstitial Model
`-DIFFUSION IN POLYCRYSTALLINE SILICON, 261
`- DIFFUSION IN Si02, 262
`ANOMALOUS DIFFUSION EFFECTS IN SILICON, 262
`Emitter Push F/fe.ct
`Lmeral Dif[11.1lon Un.di!.r O:xidl. Wi,.dows
`Diffusion in. an Oxidizing Ambient
`- DIFFUSION SYSTEMS AND DIFFUSION SOURCES, 264
`Gaseous Sourcu
`Liquid SoiiTces
`Solid Sources
`- MEASUREMENT TECHNIQUES FOR DIFFUSED LAYERS, 267
`Sheet Resistillity Measurenumts
`JIUJctiort Depth MeasUTemenls
`Dopirtg Profile MeasUTemertts
`
`,'
`
`~I
`
`9. ION IMPLANTATION FOR VLSI
`
`280
`
`- ADVANTAGES (AND PROBLEMS) OF ION-IMPLANI ATION, 282
`- IMPURITY PROFILES OF IMPLANTED IONS, 283
`Definitiort.r AssociaJed with Ion lmplarttalion Profiles
`Theory oflort Stopping
`Models for Predictirtg lmplantaJiort Profiles in Amorphous Solids
`Implanting inlo Single·Crystal Materials: Clu1111Jellng
`BoltzmtVIn Transport Equation 0/ld. Monte·Carlo Approaches to Calculating Profiles
`- ION IMPLANTATION DAMAGE AND DAMAGE ANNEALING IN SILICON, 295
`/mplantaliort DamtJge in Silicon
`Electrical Activation tutd /mpltV!tation DanllJge ANiealing
`- ION IMPLANTATION EQUIPMENT, 309
`CompOMnts of art fort Implantatiort System
`Ion /mplalller Types
`fort lmplarttatiort Equipment LimitaJions
`Ion Implantation Safety ColiSide.raJiort.r
`-CHARACTERIZATION OF ION IMPLANIATIONS, 318
`Measuremelll oflmplafltation Dose and Dose Uniformity
`Measweme.nt of/mplllllltJJiort Depth. Profiles
`MeasJUement oflmpltV!taJion Damage and Damage Annealing Efficacy
`-ION IMPLANTATION PROCESS CONSIDERATIONS, 321
`Selecting Masking l..ayer Material artd Thickness
`/mplarttirtg Through Swrfat:e I..ayers
`Shallow IU11Ctio11 Formation by lon·lmplantation
`Multiple lmplantaJio!IS
`
`MICRON ET AL. EXHIBIT 1040
`Page 9 of 345
`
`

`
`CONTENTS
`
`CONTENTS
`
`xvii
`
`10. ALUMINUM TIDN FILMS AND
`PHYSICAL VAPOR DEPOSITION IN VLSI
`
`331
`
`• ALUMINUM THIN FILMS IN VLS~ 332
`SPUITER DEPOSIIION OF THIN FILMS FOR VLSJ, 335
`Properties of Glow-Discluuges
`Physics of SpWterhtg
`SpJllter Deposited Film Growth
`Radio-freqruncy (RF) SpWtering
`Magnetron SpuJtering
`Bia.r SpUUerittg
`SpuJter Deposition Equlpme.nt
`Co~rclal Sputtering System ConjigwaJions
`Process Corui'tkraJions U. Sputter Deposition
`Reactive SpuJterlng
`FuJwe TreNb in SpuJter Deposition
`- PHYSICAL VAPOR DEPOSIIION BY EVAPORATION, 374
`EvaporaJion Basics
`EvaporaUon Methods
`EWiporaJion Process Conslderatioru
`- METAL FILM TIIICKNESS MEASUREMENT, 380
`
`11. REFRACTORY METALS and THEIR SILICIDES in VLSI
`
`384
`
`• CANDIDATE SILICIDES FOR VLSJ APPUCATIONS, 386
`Silicide Resistivities
`SILICIDE FORMATION, 388
`Direct Metallwgicol Retu:tlon
`Co-EvoporaJiofl
`Spulter Deposition: Co-Spllltering ONi SpuJ.tering from Composile Targets
`Chemical Vapor Deposition
`STRESS IN SJLJCIDES, 394
`OXIDATION OF SILICIDES, 395
`PROCESS INTERACTION, 397
`SELF-AUGNED SILICIDE (SALICIDE) TECHNOLOGY, 397
`REFRACTORY METAL INTERCONNECTIONS FOR VLSJ, 399
`Deposition of CVD T~mgsien
`Selective Deposition of Tl.mgsten
`Properties of CVD TUllgsleltfor VLSI Colllacl.s
`Futwe Trends
`
`12. LITHOGRAPHY 1: OPTICAL PHOTORESISTS -
`MATERIAL PROPERTIES AND PROCESS TECHNOLOGY 407
`
`- BASIC PHOTORESIST TERMINOLOGY, 407
`
`PHOTORESIST MATERIAL PARAMETERS, 409
`ResoliUiofl
`Se~tslti.,ity
`Etcll Reslstmtce QIJd Tltermal Stability
`A.dlusion
`Solith Content QIJd Viscosity
`PartlcJllales tmd Metals ConJelll
`Flash Point aJtd TLV Ratltig
`Proceu LatltJUU., Consislertey, QIJd Sllelf-Life
`.OPTICAL PHOTORESIST MATERIAL TYPES, 418
`Postive OptU:al Pllotoresists
`lfegaliYe Optical Pllotoresl.!ts
`Image Rwersal of Positive Resist
`Mllltilayer Resist Processes
`Cofltrast Enhancement Layer.1
`lnorgQIJic Resists
`Dry-De11elopable Resists
`Mid-UV orad Deep-UV Resists
`PhotosensitiYe Polylmides
`PHOTORESIST PROCESSING, 429
`Resist Processing: Deh.ydratio11 BaJ:ing QIJd Priming
`Resist Processirtg: Coating
`Resist Proce.rsing: Soft-BaJ:e
`Resist Processing: Exposure
`Resist Processing: DeYelopmenJ
`Resist Processiflg: After De11elop Inspection (JIJd Linewldth Measureme~tt
`Resist Processing: Post Bail. ami Deep UV Hardening
`PHOTORESIST SELECTION, 454
`
`·'
`:>
`
`13. LITHOGRAPHY II:
`OPTICAL ALIGNERS AND PHOTOMASKS
`
`459
`
`OPTICS OF MICROUTHOGRAPHY, 460
`Dif/ractlofl, Coherence, NJUMrical Aperture, and ResolllJ.ion
`Modlllaliofl TrON/er FU11Ction.
`OPTICAL ME1HODS OF TRANSFERRING PATTERNS
`TO A WAFER: OPTICAL ALIGNERS, 468
`Light So~~.rces (JIJd Liglll Meters for Optical Aligners
`Contact Prilltlng
`Prcuimity Prillting
`Projection. Pdntiflg: ScO!Uiing Aligners and Steppers
`PATTERN REGISTRATION, 473
`Automatic Alignment
`- MASK AND RETICLE FABRICATION, 476
`Glass Quality and Preparation
`Glass Coaling (CIIro~M)
`
`MICRON ET AL. EXHIBIT 1040
`Page 10 of 345
`
`

`
`X'Yiii
`
`CONTENTS
`
`CONTENTS
`
`xlx
`
`Mark Imaging (Resist Application and Processing)
`Pattern Generation (Optical tJJJd Electron-Beam)
`Mask and Retick Defects tJJJd tMir Repair
`Pellide:r
`Crilical Dimen.sio" tJJJd Registration Inspection of Masks and Reticles
`
`14o ADVANCED LITHOGRAPHY
`
`493
`
`0 ELECfRON BEAMLI1HOGRAPHY, 493
`Electron Beam Systems
`Writl"g Strategies
`Electron Scatteri"g in Resists
`Resist Dewlopment
`Prozjmity Effect:~
`0 X-RAY Ll1HOGRAPHY, 504
`X-Ray Sowce:r
`X-Ray Masks
`X-Ray Resists
`- ION BEAMLI1HOGRAPHY, 510
`
`15o WET PROCESSING: CLEANiNG; ETCHING; LIFT-OFF 514
`
`-WAFER CLEANING, 516
`Sources of Cont12minaJion
`Wt(er Clea~~ing Procedwes
`- TERMINOLOGY OF ETCHING, 520
`Bias, TolertuU:e, Etch Rate, tJJJd Anisotropy
`Selectivity, Overetch, tJJJd Featwe-sU.e Conlrol
`De.termilfing Required Selectivity with Respect to S~tbstrate, Sf:r
`Determining Req~tired Sekctivlty with Respect to Mask, Sfm
`Loading Effects
`- WET ETCHING TECHNOLOGY, 529
`Wet EtciWig Silicon
`Wet Etching Silicort Dio:Pde
`Wet Etching Sllicort Nitride
`Wet Etching Alwninwn
`- LIFT-OFF TECHNOLOGY FOR PATTERNING, 535
`
`16o DRY ETCHiNG FOR VLSI
`
`539
`
`BASIC PHYSICS AND CHEMISTRY OF PLASMA ETCHING, 542
`The Reactive Gas Glow Discharge
`Electrical Aspects of Glow Discharges
`
`Heterogeneou (SIU{ace) Reaction CotUiderations
`Parameter Control in Plasma Processes
`
`ETCHING SILICON AND Si02 m CF4 1021Rz, 541
`Fluorine-to-Carbon Ratio Model
`- ANISOTROPIC ETCHING AND CONTROL OF EDGE PROFILE, 552
`- DRY ETCHING VARIOUS TYPES OF THIN FilMS, 555
`Silicon Dioxide (Si02)
`Silicon Nitride
`P olysilicofl
`Refractory Metal Silit:ides and Polycides
`Alwniflum and Aluminum Alloys
`Organic Films
`- PROCESS MONITORING AND END POINT DETECTION, 565
`Laser Reflectomdry tJJJd Laser Reflet:ltJJJCe
`Optical Emission Spectroscopy
`M03s Spectroscopy
`- DRY ETCHING EQUIPMENT CONFIGURATIONS, 568
`Commercial Dry Etch System Configwalions
`Comparison of Single Wafer and Batch Dry Etchers
`-. PROCESSING ISSUES RELATED TO DRY ETCHING, 574
`Plasma Etching Safety Con.sideraJioru
`Uniformity tl1ld Reproducibility Considerations
`Contaminatiofl and D12mage of EICMd SJUfaces
`Process Gares for Dry Etching
`
`17o MATERIAL CHARACTERIZATION TECHNIQUES
`FOR VLSI FABRICATION
`
`586
`
`- WHAT ARE WE TRYING TO DETECT, AND HOW IS IT DONE?, 586
`Energy Regimes tJJJd &ergy LeYels in MaJerlal CllaracterU.ation.
`Dejiflitions of Material Characterization Terminology
`VacuiUI'I ReqW.remeltl;r of Compositional Analysis
`MICROSCOPY FOR VLS! MORPHOLOGY, 589
`Optical Microscopes
`Scanning Electrotl Microscopes (SEM)
`Transmission Electron Microscopy
`- ELECfRON IX-RAY COMPOSITIONAL ANALYSIS TECHNIQUES, 599
`Auger Emission Spectroscopy
`X-Ray Emissiot~ Spectrocopy
`X-Ray Photodectrofl Spectroscopy (XPS, ESCA)
`X-Ray PluorescefiCe
`- IONBEAMEXCITEDCOMPOSITIONALANALYSIS, 606
`Secondary-Iofl Mass Spectroscopy (SIMS)
`Laser Iofl Mass Spectroscopy (UMS)
`RuJ.Mr/ord BaclucaJtering Spectroscopy (RllS)
`
`MICRON ET AL. EXHIBIT 1040
`Page 11 of 345
`
`

`
`""
`
`CONTENTS
`
`CRYSTALLOGRAPIDC STRUCTURE ANALYSIS, 610
`X·Ray Diffraction
`X-Ray Lang Topograplry
`Nelllron Activation Analysis (NAA)
`- SUMMARY OF CHARACTERIZATION TECHNIQUE CAPABILITIES, 612
`SUGGESTIONS FOR HOW TO ACCOMPUSH AN EFFECTIVE ANALYSIS, 614
`
`18. STRUCTURED APPROACH to DESIGN of EXPERIMENTS
`FOR PROCESS OPTIMIZATION
`
`618
`
`- FUNDAMENTALS OF STATISTICS, 619
`Samples, PopulalioM, MeaJU, Variance, aJJd Sttmdard Deviolion
`Pooled Varia~~ee aNi Degrees of Freedom
`Normal DistribuJions
`Distributions of Averages, t-Distriblllions, tJIId Confider~ce Levels
`- DESIGN OF EXPERIMENTS: BASIC DEFINITIONS, 625
`- CHARACI'ERISTICS OF FACTORIAL EXPERIMENTS, 627
`- STRATEGY OF DESIGNING EXPERIMENTS, 632
`- DESIGNING and ANAL Y2ING 2-LEVEL FULL-FACTORIAL EXPERIMENTS, 634
`Method for Designing 2-Uvel Fllll-FtU:toriol &:perim.en.ts
`Analysis of tile Measwred Data
`- SCREENING EXPERIMENTS, 641
`- RESPONSE SURFACES, 643
`
`APPENDICES
`
`I. MATERIAL PROPERTIES OF SIUCON at 300"K
`2. PHYSICAL CONSTANTS
`3. ARRIIENllJS RELATIONSIDP
`
`INDEX.
`
`647
`648
`649
`
`651
`
`PROLOGUE
`
`Since the creation of the flrst integrated circuit in 1960, there has been an ever increasing
`density of devices manufacturable on semiconductor substrates. Silicon technology has remained
`the domip.ant force in integrated circuit fabrication and is likely to retain this position for the
`forseeable future. The number of devices manufactured on a chip exceeded the generally accepted
`definition of very large scale integration, or VLSI (i.e. more than 100,000 devices per chip),
`somewhere in the mid-70's (Fig. 1a). By 1986, this number had, in fact, grown to over
`1 million devices per chip. The increasing device count was accompanied by a shrinking
`minimum feature size (Fig. 1b), which is expected to be smaller than 1 ~m before 1990.
`Progress in VLSI manufacruring technology seems likely to continue to proceed in this manner,
`and even further reductions in the unit cost per function, and in the power-delay product of VLSI
`devices, are projected. The entire adventure of VLSI represents a remarkable application of
`scientific knowledge to the requirements of technology, and this book represents an enthusiastic
`report on the state-of-the-art of VLSI silicon processing, as practiced at the time of publication.
`Figure 2 illustrates the sequence of steps that occurs in the course of manufacturing an
`integrated circuit. These steps can be grouped into two phases: 1) the design phase; and b) the
`fabrication phase. This book is concerned only with the fabrication phase of this undertaking,
`but it is useful to briefly outline the steps of the design phase. This provides a context which
`allows the reader to perceive the role of silicon processing. within tbe totality of integrated circuit
`manufacturing. Readers wishing to explore steps of the design phase in further detail, are referred
`to other technical literature, including tbe texts listed in Refs. 1-3 at the end of this prologue.
`In tbe design phase of this sequence, the desired functions and necessary operating
`specifications of the circuit are initially decided upon. The chip is then designed from the "top
`··~--------------------,--,
`
`~··
`
`0
`
`CECRE.lS!; BY ABOUT
`,...,.EAR
`
`!S,.ml
`
`·~'
`
`'"'
`
`1~a.~,--'-T,,.\;"-'-;,;i;,";-'--;,.~";-'-o.,.!;;,.-'-,;;.;;-, -'-;,.~.;-'-,!,gs5
`a ) .
`YEAA OF IHTROOUCTION
`
`1110
`
`11115
`
`b>
`
`Fig. 1 (a) Increase in the number of transistors per microprocessor chip versus year of
`introduction, for a variety of B·bit and 16 bit microprocessors, and (b) The decrease in minimum
`device feature size versus time on integrated circuits.
`x>d
`
`MICRON ET AL. EXHIBIT 1040
`Page 12 of 345
`
`

`
`PROLOGUE
`xxli
`down". That is, the required large junctional blocks are fl.rst identified. Next, their sub-bloc~
`are selected, and then the logic gates needed to implement the sub-bloc~s are chosen. Ea~h logtc
`gate is designed by appropriately connecting devices (transistors, and m some ~ases reststor~ as
`well) that are ultimately slated for fabrication on the Si wafers .. Upon comple~ng these vartous
`levels of design, each is cllecked to insure that correct functionahty has been achi_eved. When the
`designers are satisfied that each level of the design is corr~t. test llec~ors, that wdl be used to test
`the manufactured circuits, are generated froiD. the scllemauc of the logtc gates.
`.
`The circuit is then layed out. The layout consists of sets of patterns that Wlll be transferred
`to the silicon wafer. The patterns correspond to device regions, or interconnect stru_crures, an~
`such patterns are sequentially transferred to the wafers through the us~ of photolithographtc
`processes and a set of masks, as part of the wafer fabrication sequence (Ftg. 4a). The result of
`each pattern transfer step is a set of features created on the wafer surface. These features are
`Objective/Specification
`
`PROLOGUE
`xxiii
`generally either in the form of: a) an etched opening in a film (or region of the substrate); orb) a
`panerned feature of a film present on the surface (e.g. an interconnect line or pad). After the
`openings (or windows) are created by the pattern transfer step, either: a) controlled quantities of
`dopant are added to the silicon substrate through the openings, or b) another layer is deposited
`that makes contact to the underlying layer through the opening. In any case, device regions,
`and structures lhat interconnect device regions, are produced by the patterning processes and
`associated fabrication steps. A cross-section of a completed device, resulting from having carried
`out a sequence of such fabrication steps is shown in Fig. 4b.
`The creation of the layout proceeds from the "bottom up". That is, a variety of typical
`devices are ftrst layed out Then, a set of cells representing the required primitive logic gates
`are created by interconnecting appropriate devices. Next, sub-blocks are generated by connecting
`these logic gates, and finally the functional blocks are layed out by connecting the sub-blocks.
`Power busses, clock-lines, input-output pads requiied by the circuit design are also incorporated
`during the layout process. The completed layout is then subjected to a set of design rule checks
`a~d propagaJion. delay simulatioM to verify that correct implementation of the circuit has been
`
`Floor Plan
`
`DESIGN
`Architectura1,
`Logic, Circuit
`
`Verification
`of Above
`Design Steps
`
`Logic Schematic
`=l:>- ':::[J-
`
`~ p
`
`Circuit Schematic
`
`DESIGN
`Layout Verification
`and
`Delay Extraction
`
`Masks
`
`(Fp
`
`CRYSTAL
`GROWTH
`
`Fig. 2 Steps required for the manufacture of very large scale integr.ued circuits (VLSI).
`
`Fig. 3 The fabrication process sequence of integrated circuits.
`
`.
`
`SOURCE
`10t TO 106
`,.