IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`Application
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`12/491655
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`33:? °r 371 (C) 07-04-2009
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`Utility
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`Application
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`Customer
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`Status:
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`Final Rejection Mailed
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`Status Date:
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`11-18-2010
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`Examiner Name: DICKEY, THOMAS L
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`Location:
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`ELECTRONIC
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`Group Art Unit:
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`2826
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`Confirmation
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`6949
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`Attorney Docket
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`0907043DS961
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`Class / Subclass: 257/777
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`-
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`US 2010-0172197 A1
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`07-08-2010
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`Location Date:
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`Publication
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`Earliest
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`Publication
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`Patent
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`First Named
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`Inventor:
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`Glenn J. Leedy ,
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`Parkland, FL (US)
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`Issue Date of
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`Patent:
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`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`RESPONSE
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`Responsive to the prior Office Action, please amend this application as follows.
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`MICRON ET AL. EXHIBIT 1032
`Page 1 of 22
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`IN THE CLAIMS
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`1. (Currently amended)
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`An integrated circuit structure comprising:
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`a first substrate comprising a first surfacehaving interconnect contacts;
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`a second substrate comprising a first surface having interconnect contacts; and
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`a bond layer between the first surface of the first substrate and the first surface of
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`the second substrate, comprising:
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`a plurality of bonds fonned from the interconnect contacts of the first
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`surfaces of the first and second substrates and forming portions of signal paths
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`between the first surface of the second substrate and the first surface of the first
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`substrate; and,
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`at least one bond formed between the first surfaces of the first and second
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`substrates and not forming portions of a signal path between the first surfaces of
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`the first and second substrates, wherein at least one of the first substrate and
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`second substrate is substantially flexible and at least one of the first substrate and
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`the second substrate is.a semiconductor substrate.
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`2. (Currently amended)
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`The structure of claim 1, wherein the second
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`substrate is one of a thinned monocrystalline semiconductor substrate and a thinned
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`polycrystalline semiconductor substrate.
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`3. (Previously presented)
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`The structure ofclaim I, wherein circuitry
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`is formed on the second substrate comprising one ofactive circuitry and passive circuitry.
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`MICRON ET AL. EXHIBIT 1032
`Page 2 of 22
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`4. (Previously presented)
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`The structure of claim 1, wherein circuitry
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`is formed on the second substrate comprising both active circuitry and passive circuitry.
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`5. (Previously presented)
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`The structure ofclaim 1, wherein the first
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`substrate is a substrate having circuitry formed thereon.
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`6. (Previously presented)
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`The structure of claim 5, wherein the
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`circuitry of the first substrate is one of active circuitry and passive circuitry.
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`7. (Previously presented)
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`The structure of claim 5, wherein the
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`circuitry of the first substrate comprises both active circuitry and passive circuitry.
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`8. (Previously presented)
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`The structure of claim 1, further comprising:
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive pathsformed between said lirst of said at least one additional
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`thinned substrate and at least one of said first and second substrates and also between
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`each additional thinned substrate and at least one of said substrates of the integrated
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`9. (Previously presented)
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`The structure of claim 8, wherein at least
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`two of the first, the second and the at least one additional thinned substrates are formed
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`I using a different process technology, wherein the different process technology is selected
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`MICRON ET AL. EXHIBIT 1032
`Page 3 of 22
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`from the group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric
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`and Giant Magneto Resistance.
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`10. (Previously presented)
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`The structure of claim 8, wherein at least
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`one of the first, the second and the at least one additional thinned substrates comprises a
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`microprocessor.
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`l I. (Previously presented)
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`The structure of claim 8, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`at least one substrate ofthe first, the second and the at least one additional
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`thinned substrates has logic circuitry formed thereon that performs tests on the at least
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`one substrate that has memory circuitry formed thereon.
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`12. (Previously presented)
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`The structure of claim 8, wherein at least
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`one substrate of the first, the second and the at least one additional thinned substrates has
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`memory circuitry formed thereon, the memory circuitry having a plurality of memory
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`locations, wherein at least one memory location ofthe plurality ofmemory locations is
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`used for sparing and wherein data from the at least one memory location on the at least
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`one substrate having memory circuitry formed thereon is used instead of data from a
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`defective memory location on the at least one substrate that has memory circuitry formed
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`thereon.
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`13. (Previously presented)
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`The structure of claim 8, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`MICRON ET AL. EXHIBIT 1032
`Page 4 of 22
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has logic circuitry formed thereon that performs programmable gate
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`line address assignment with respect to the at least one substrate having memory circuitry
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`14. (Previously presented)
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`The structure of claim 8, further comprising
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`a plurality of interior vertical interconnections that traverse at least one of the first, the
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`15. (Previously presented)
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`The structure of claim 8, wherein
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`information processing is performed on data routed between the circuitry of at least two
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`ofthe first, the second and the at least one additional thinned substrates.
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`16. (Previously presented)
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`The structure of claim 8, wherein at least
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`one of the first, the second and the at least one additional thinned substrates has
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`reconfiguration circuitry.
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`17. (Previously presented)
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`The structure of claim 8, wherein at least
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`one of the first, the second, and the at least one additional thinned substrates has logic
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`circuitry formed thereon for performing at least one function from the group consisting
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`of: virtual memory management, ECC, indirect addressing, content addressing, data
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`compression, data decompression, graphics acceleration, audio encoding, audio decoding,
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`video encoding, video decoding, voice recognition, handwriting recognition, power
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`management and database processing.
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`MICRON ET AL. EXHIBIT 1032
`Page 5 of 22
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`18. (Previously presented)
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`The structure of claim 8, further
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`a memory array having a plurality of memory storage cells, a plurality of
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`data lines, and a plurality of gate lines, each memory storage cell stores a data value and
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`has circuitry for coupling the data valueito one ofthe plurality ofdata lines in response to
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`receiving a gate control signal from one of the plurality ofgate lines;
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`circuitry that generates the gate control signal in response to receiving an
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`_ address, including means for mapping addresses to gate lines; and
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`a controller that determines if one of the plurality of memory cells is
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`defective and alters said mapping to remove references to the one of the plurality of
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`memory cells that is defective.
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`19. (Previously presented)
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`The structure of claim 8, further
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality of data lines and a plurality of gate lines on each memory
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data valueand has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one of the plurality of gate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
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`address assignments for at least one gate line ofthe plurality of gate lines and wherein the
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`MICRON ET AL. EXHIBIT 1032
`Page 6 of 22
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`address assignments for determining which of the plurality of gate lines is selected for
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`each programmed address assignment; and
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`controller substrate logic that determines if one memory cell of the array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`lines to remove references to the gate line that causes the defective memory cell to couple
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`a data value to one ofthe plurality ofdata lines.
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`20. (Previously presented)
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`The structure of claim 19, wherein the '
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`controller substrate logic:
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`tests the array of memory cells periodically to determine ifone ofthe
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`array of memory cells is defective; and
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality of data lines.
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`21. (Previously presented),
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`The structure of claim 19, further
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`programmable logic to prevent the use of data values from the plurality of
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality of data lines.
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`22. (Previously presented)
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`The structure ofclaim 19, wherein the array
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`of memory cells are arranged within physical space in a physical order and are arranged
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`within an address space in a logical order and wherein the physical order of at least one
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`memory cell is different than the logical order of the at least one memory cell.
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`MICRON ET AL. EXHIBIT 1032
`Page 7 of 22
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`23. (Previously presented)
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`The structure ofclaim 19, wherein:
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`the logic circuitry of the at least one controller substrate is tested by an
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
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`a functional testing of a substantial portion of the array of memory cells.
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`24. (Previously presented)
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`The structure of claim 19, wherein the logic
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`circuitry of the at least one controller substrate performs functional testing of a
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`substantial portion of the array of memory cells.
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`25. (Previously presented)
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`The structure ofclaim 19, wherein the
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`controller substrate logic is further configured to:
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`prevent the use of at least one defective gate line; and
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`26. (Previously presented)
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`The structure of claim 19, wherein the
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`controller substrate logic is further configured to prevent the use of at least one defective
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`gate line.
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`27. (Previously presented)
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`The structure of claim I9, wherein the logic
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`circuitry of the at least one controller substrate can perform all functional testing of the
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`array of memory cells ofthe at least one memory substrate.
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`MICRON ET AL. EXHIBIT 1032
`Page 8 of 22
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`28. (Previously presented)
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`The structure of claim 1, wherein the first
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`substrate is a non-semiconductor material.
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`29. (Currently amended)
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`An integrated circuit structure comprising:
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`a first substrate having topside and bottomside surfaces, wherein the
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`topside surface of the first substrate has interconnect contacts;
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`a second substrate having topside and bottomside surfaces, wherein the
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`bottomside surface of the second substrate has interconnect contacts; and
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`a bond layer between the topside surface of the first substrate and the
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`bottomside surface of the second substrates comprising:
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`a plurality of bonds formed from the interconnect contacts forming
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`conductive paths between the topside of the first substrate and the bottomside ofthe
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`second substrate; and,
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`at least one bond formed between the topside of the first substrate and the
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`bottomside of the second substrate forming at least one: of a non-conductive contact; and
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`a conductive contact not formed from one of said interconnect contacts;
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`wherein at least one of the first substrate and the second substrate is
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`substantially flexible and at least one of the first and second substrates is a semiconductor
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`substrate.
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`30. (Previously presented)
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`The integrated circuit structure of claim 29,
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`wherein selected ones of said interconnect contacts of said topside surface of said first
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`substrate are in electrical contact with selected ones of the interconnect contacts of said
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`bottomside surface ofsaid second substrate so as to form said electrical connections.
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`MICRON ET AL. EXHIBIT 1032
`Page 9 of 22
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`31. (Currently amended)
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`An integrated circuit structure comprising:
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`a first substrate having a first and second surface;
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`a second substrate having a first and second surface, wherein said second
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`surfaces of the first and second substrates are opposite to said first surfaces;
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`a plurality of bondg:__q—fermed—_contacts between the first surface of the first
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`substrate and the first surface of the second substrate;
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`wherein at least one of said contacts is a signal path conductive contact
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`and at least another one of said contacts is one of: a signal path conductive contact; a
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`non~signal path conductive contact; and a non—conductive contact;
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`wherein at least one of the first substrate and second substrate is substantially
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`flexible and at least one of the first substrate and the second substrate is a semiconductor
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`substrate.
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`comprising:
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`32. (Previously presented)
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`The structure of claim 29, further
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive paths formed between said first of said at least one additional
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`thinned substrate and at least one of said first and second substrates and also between
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`each additional thinned substrate and at least one of said substrates of the integrated
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`circuit structure.
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`MICRON ET AL. EXHIBIT 1032
`Page 10 of 22
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`33. (Previously presented)
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`The structure ofclaim 32, further
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality of data lines and a plurality of gate lines on each memory
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`comprising:
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`substrate;
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data value and has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one ofthe plurality ofgate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
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`address assignments for at least one gate line of the plurality of gate lines and wherein the
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`address assignments for determining which of the plurality of gate lines is selected for
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`each programmed addressassignment; and
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`controller substrate logic that determines if one memory cell of the array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`lines to remove references to the gate line that causes the defective memory cell to couple
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`a data value to one of the plurality of data lines.
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`34. (Previously presented)
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`The structure of claim 33, wherein the
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`controller substrate logic:
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`tests the array of memory cells periodically to determine if one ofthe
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`array of memory cells is defective; and
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`MICRON ET AL. EXHIBIT 1032
`Page 11 of 22
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality of data lines.
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`35. (Previously presented)
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`The structure of claim 33, further
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`comprising:
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`programmable logic to prevent the use ofdata values from the plurality of
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality ofdata lines.
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`36. (Previously presented)
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`The structure of claim 33, wherein the array
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`of memory cells are arranged within physical space in a physical order and are arranged
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`within an address space in a logical order and wherein the physical order of at least one
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`memory cell is different than the logical order of the at least one memory cell.
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`37. (Previously presented)
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`The structure ofclaim 33, wherein:
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`the logic circuitry ofthe at least one controller substrate is tested by an
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`external means; and
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
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`a functional testing of a substantial portion of the array of memory cells.
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`38. (Previously presented)
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`The structure of claim 33, wherein the logic
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`circuitry of the at least one controller substrate performs functional testing of a
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`substantial portion of the array of memory cells.
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`MICRON ET AL. EXHIBIT 1032
`Page 12 of 22
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`39. (Previously presented)
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`The structure of claim 33, wherein the
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`controller substrate logic is further configured to:
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`prevent the use of at least one defective gate line; and
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`40. (Previously presented)
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`The structure of claim 33, wherein the
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`controller substrate logic is further configured to prevent the use of at least one defective
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`gate line.
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`41. (Previously presented)
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`The structure ofclaim 33, wherein the logic’
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`circuitry of the at least one controller substrate can perform all functional testing of the
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`array of memory cells of the at least one memory substrate.
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`42. (Previously presented)
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`The structure of claim 1, wherein the second
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`substrate is thinned to about 50 microns or less.
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`43. (Previously presented)
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`The structure ofclaim 29, wherein the
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`second substrate is thinned to about 50 microns or less.
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`44. (Previously presented)
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`The structure of claim 31, wherein the
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`second substrate is thinned to about 50 microns or less.
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`45. (Previously presented)
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`The structure of claim 1, wherein the first
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`substrate and the second substrate are the same size or overlap each other completely.
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`MICRON ET AL. EXHIBIT 1032
`Page 13 of 22
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`446. (Previously presented)
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`The structure of claim 29, wherein the first
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`substrate and the second substrate are the same size or overlap each other completely.
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`47. (Previously presented)
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`The structure of claim 3 1, wherein the first
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`substrate and the second substrate are the same size or overlap each other completely.
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`48. (Previously presented)
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`The integrated circuit structure of claim 1,
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`wherein at least one of the first and second substrates is at least one of the following: less
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`than about 10 microns in thickness; substantially flexible; and comprises a dielectric layer
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`with a stress of about 5 x 108 dynes/cmz or less.
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`49. (Previously presented)
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`The integrated circuit structure ofclaim 29,
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`wherein at least one of the first and second substrates is at least one of the following: less
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`than about 10 microns in thickness; substantially flexible; and comprises a dielectric layer
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`with a stress of about 5 x 108 dynes/cmz or less.
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`50. (Previously presented)
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`The integrated circuit structure of claim 31,
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`wherein at least one of the first and second substrates is at least one of the following: less '
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`than about 10 microns in thickness; substantially flexible; and comprises a dielectric layer
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`with a stress of about 5 x 108 dynes/cm’ or less.
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`51. (Previously presented)
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`The structure of claim 1, wherein each of the
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`first substrate and the second substrate comprises said first surface thereof and a second
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`surface thereof, said second surface thereof being opposite to said said first surface
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`thereof, wherein at least one of the first and second substrates is a thinned substrate, and
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`wherein the second surface ofsaid thinned substrate is a polished surface.
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`MICRON ET AL. EXHIBIT 1032
`Page 14 of 22
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`52. (Previously presented)
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`The structure of claim 29, wherein the
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`53. (Previously presented)
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`The structure ofclaim 3 I, wherein at least
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`one of the first and second substrates is a thinned substrate, and wherein the second
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`surface of said thinned substrate is a polished surface.
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`54. (Currently amended)
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`The structure of claim I, wherein at least
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`two of: the first substrate is a non-semiconductor material; the second substrate is~feFmed
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`efcomprises at least one dielectric witha stress of about 5 x 108 dynes/cmz or less; the
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`dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate
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`has one of logic circuitry and memory circuitry formed thereon; at least one conductive
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`path passes through a substrate and is insulated by an insulation material from said
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`substrate; at least one of the first and second substrates is a monocrystalline
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`55. (Currently amended)
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`The structure of claim I, wherein at least
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`three of: the first substrate is a nomsemiconductor material; the second substrate is
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`fermedefcomprises at least one dielectric with a stress of about 5 x 108 dynes/cmz or
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`less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second
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`conductive path passes through a substrate and is insulated by an insulation material from
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`said substrate; at least one of the first and second substrates is a monocrystalline
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`56. (Currently amended)
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`The structure of claim 1, wherein at least
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`four of: the first substrate is a non-semiconductor material; the second substrate isfermed
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`efcomprises at least one dielectric with a stress of about 5 x 108 dynes/cmz or less; the
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`dielectric is at least one ofsilicon dioxide and an oxide ofsilicon; the second substrate
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`MICRON ET AL. EXHIBIT 1032
`Page 15 of 22
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`path passes through a substrate and is insulated by an insulation material from said
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`57. (Currently amended)
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`The structure of claim 29, wherein at least
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`efcomprises at least one dielectric with a stress ofabout 5 x I08 dynes/cm2 or less; the
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`dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate
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`path passes through a substrate and is insulated by an insulation material from said
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`substrate; at least one of the first and second substrates is a monocgstalline
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`58. (Currently amended)
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`The structure of claim 29, wherein at least
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`three of: the flrst substrate is a non-semiconductor material; the second substrate is
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`£ei=med—e£comprises at least one dielectric with a stress of about 5 x 108 dynes/cm2 or
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`less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second
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`substrate has one of logic circuitry and memory circuitry formed thereon; at least one
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`conductive path passes through a substrate and is insulated by an insulation material from
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`said substrate; at least one of the first and second substrates is a monocmstalline
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`59. (Currently amended)
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`The structure of claim 29, wherein at least
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`four of: the first substrate is a non-semiconductor material; the second substrate is-fer-med
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`efcomprises at least one dielectric with a stress ofabout 5 x 108 dynes/cmz or less; the
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`dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate
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`has one of logic circuitry and memory circuitry formed thereon; at least one conductive
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`path passes through a substrate and is insulated by an insulation material from said
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`substrate; at least one of the first and second substrates is a monocrystalline
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`MICRON ET AL. EXHIBIT 1032
`Page 16 of 22
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`60. (Currently amended)
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`The structure of claim 31, wherein at least
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`two of: the first substrate is a non-semiconductor material; the second substrate isfermed
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`et-‘comprises at least one dielectric with a stress of about 5 x 108 dynes/cmz or less; the
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`dielectric is at least one of silicon dioxi