IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`In re application of
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`LEEDY
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`Atty. Docket
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`090316-3DS-II
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`Serial: 12/405,234
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`Group Art Unit: 2822
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`Filed: 03/ 17/2009
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`Examiner: Tsz K. Chiu
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`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`RESPONSE
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`Responsive to the prior Office Action, please amend this application as follows.
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`MICRON ET AL. EXHIBIT 1026
`Page 1 of 16
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`IN THE CLAIMS:
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`1. (Currently amended) A stacked integrated circuit comprising:
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`a circuit substrate;
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`a first integrated circuit having circuitry formed on a front surface thereof, the front
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`surface being bonded to the circuit substrate; and
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`one or more additional integrated circuits each having circuitry formed on respective
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`from surfaces thereof, each additional integrated circuit being bonded by the front surface thereof
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`to a back surface of an adjacent integrated circuit;
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`wherein at least one of the first integrated circuit and the one or more additional
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`integrated circuits is substantially flexible and comprises a substantially flexible semiconductor
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`substrate made from a semiconductor wafer thinned by at least one of abrasion, etching and
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`parting, and subsequently polished to form a polished surface w%mw
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`2. (Currently amended) The apparatus ofelaimflyclaim 4], wherein the circuit substrate is an
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`integrated» circuit substrate having circuitry formed on a front surface thereof wherein the front
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`surfaces of the integrated circuit substrate and the first integrated circuit are bonded together.
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`3. (Original) The apparatus ofclaim 2, further comprising a thermal diffusion bond joining the
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`integrated circuit substrate and the tirst integrated circuit.
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`MICRON ET AL. EXHIBIT 1026
`Page 2 of 16
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`4. (Original) The apparatus ofclaim 2, further comprising thermal diffusion bonds joining each
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`additional integrated circuit to an adjacent integrated circuit.
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`5. (Currently amended) The apparatus of elaim—l—,—claim 41, further comprising a second
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`integrated circuit and vertical interconnects connecting circuitry ofthe first integrated circuit and
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`circuitry of the second integrated circuit, wherein a plurality of interconnects are closely arrayed
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`to form a group of interconnects.
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`6. (Original) The apparatus of claim 5,wherein a group of interconnects extends continuously
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`between multiple integrated circuits.
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`7. (Original) The apparatus of claim 5, wherein the interconnects are formed at least in part by a
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`thermal diffusion bond.
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`8. (Currently amended) The apparatus of eiaim——1~,—claim 41 , wherein the first integrated circuit
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`and the additional integrated circuit are formed with one of single crystal semiconductor material
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`and polycrystalline semiconductor material.
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`9, (Currently amended) The apparatus ofelaim—4~,—claim 41 further comprising a second
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`integrated circuit, wherein one ofthe first and additional integrated circuits are formed using a
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`different process technology than another of the first and second integrated circuits, the different
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`process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM,
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`EEPROM, Ferroelectric and Giant Magneto Resistance.
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`MICRON ET AL. EXHIBIT 1026
`Page 3 of 16
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`10. (Currently amended) The apparatus of e-laim—4—,—claim 41, wherein at least one of the first and
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`additional integrated circuits comprises a microprocessor.
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`1 1. (Currently amended) The apparatus of el-sim—17claim 41, further comprising at least one
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`memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic
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`integrated circuit performs testing of the at least one memory integrated circuit.
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`12. (Currently amended) The apparatus of elaim—l,—clairn 41, further comprising at least one
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`memory integrated circuit having multiple memory locations including at least one memory
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`location used for sparing, wherein data from the at least one memory location on the at least one
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`memory integrated circuit is used instead ofdata from a defective memory location on the at
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`least one memory integrated circuit.
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`13. (Currently amended) The apparatus ol‘elaim~l~,—claim 41, further comprising at least one
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`memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic
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`integrated circuit performs programmable gate line address assignment with respect to the at
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`least one memory integrated circuit.
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`14. (Currently amended) The apparatus of elaim-l;—claim 41, wherein a plurality of interior
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`vertical interconnections traverse at least one of the integrated circuits.
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`MICRON ET AL. EXHIBIT 1026
`Page 4 of 16
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`15. (Currently amended) The apparatus of e—laim—lTclaim 41 further comprising a second
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`integrated circuit, wherein continuous vertical interconnections connect circuitry of the first and
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`second integrated circuits.
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`16. (Currently amended) The apparatus of ela~im—l-,-claim 41, further comprising a second
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`integrated circuit, wherein information processing is performed on data routed between circuitry
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`on the first and second integrated circuits.
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`17. (Currently amended) The apparatus of elai-m—l,—claim 4], wherein at least one integrated
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`circuit has reconfiguration circuitry.
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`I8. (Currently amended) The apparatus of e—laim—l,—claim 41, further comprising at least one logic
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`integrated circuit having logic for performing at least one of the following functions: virtual
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`memory management, ECC, indirect addressing, content addressing, data compression, data
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`decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video
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`decoding, voice recognition, handwriting recognition, power management and database
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`processing.
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`19. (Currently amended) The apparatus ofelaim—l,—c|aim 4 I, further comprising:
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`a memory array having a plurality of memory cells, a plurality ofdata lines, and a
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`plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for
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`coupling that data value to one of said data lines in response to a gate control signal on one of
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`said gate lines;
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`MICRON ET AL. EXHIBIT 1026
`Page 5 of 16
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`circuitry for generating a gate control signal in response to an address, including means
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`for mapping addresses to gate lines; and
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`a controller for determining that one of said memory cells is defective and for altering
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`said mapping to eliminate references to said one of said memory cells.
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`20. (Currently amended) The apparatus ofelaim-l»,~claim 41, further comprising:
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`one or more controller integrated circuits;
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`one or more memory integrated circuits;
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`a plurality of data lines and a plurality ofgate lines on each memory integrated circuit;
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`an array of memory cells on each memory integrated circuit, each memory cell storing a data
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`value and comprising circuitry for coupling that data value to one of said data lines in response
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`to the selection ofone of said gate lines;
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`a gate line selection circuit for enabling a gate line for a memory operation, said gate line
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`selection circuit comprising programmable gates to receive address assignments for one or more
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`of said gate lines, said address assignments for determining which of said gate lines is selected
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`for each programmed address assignment; and
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`controller logic for determining that one of said array memory cells is defective and for
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`altering in at least one instance said address assignments of said gate lines to eliminate references
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`to that gate line that causes that defective memory cell to couple a data value to one of said data
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`lines.
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`21 . (Original) The apparatus of claim 20, wherein said controller logic tests said memory cells
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`periodically to determine if any of said memory cells is defective and wherein said controller
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`MICRON ET AL. EXHIBIT 1026
`Page 6 of 16
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`eliminates references in said address assignments to gate lines that cause said detected defective
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`memory cells to couple data values to said data lines.
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`22. (Original) The apparatus of claim 20, further comprising programmable logic to prevent the
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`use of data values from data lines when gate lines ‘cause said detected defective memory cells to
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`couple data values to said data lines.
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`23. (Original) The apparatus of claim 20, wherein said memory cells are arranged within
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`physical spacein a physical order and are arranged within an address space in a logical order,
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`wherein said physical order of at least one memory cell is different than the logical order of that
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`memory cell.
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`,.
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`24. (Original) The apparatus of claim 20, wherein external testing of the controller logic together
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`with testing by the controller logic ofthe memory cells achieves a functional testing ofa
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`preponderance of the memory cells.
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`25. (Original) The apparatus ofclaim 20, wherein testing by the controller logic ofthe memory
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`cells substantially reduces or eliminates the need for external testing of the memory cells of the
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`one or more memory integrated circuits.
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`26. (Original) The apparatus ofclaim 20 wherein altering said address assignments comprises
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`preventing the use of at least one defective gate line and replacing references to memory cells
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`MICRON ET AL. EXHIBIT 1026
`Page 7 of 16
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`addressed using said defective gate line with references to spare memory cells addressed using a
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`spare gate line.
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`27. (Currently amended) The apparatus ofelaim—l,—claim 41, wherein the first integrated circuit
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`is fabricated using one process technology, and the one or more additional integrated circuits are
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`fabricated using a different process technology.
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`3 ::..__—C_
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`28. (Currently amended) The apparatus ofelaim-l—claim 41 wherein at least one ofthe
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`integrated circuits has a thickness ofone of 10 microns or less and 50 microns or less.
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`29. (Previously presented) The apparatus of claim 1, wherein at least one ofthe integrated
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`circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one ofa
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`silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about
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`5 X lO8 dynes/cmz or less.
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`30. (Currently amended) The apparatus ofelaim—l,—c|aim 41 wherein the first integrated circuit
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`is formed on a monocrystalline semiconductor substrate.
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`31. (Currently amended) The apparatus ofelaim—l,—claim 41, wherein at least one conductive
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`path pass through the monocrystalline semiconductor substrate and is insulated by an insulation
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`material from said monocrystalline semiconductor substrate.
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`MICRON ET AL. EXHIBIT 1026
`Page 8 of 16
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`32. (Currently amended) The apparatus of e—laim—l-,—claim 41. wherein a back surface of the first
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`integrated circuit is polished.
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`33. (Currently amended) The apparatus of claim-1-,-claim 41, further comprising a second
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`integrated circuit and vertical interconnects connecting at least two of said circuit substrate, said
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`34. (Previously presented) The apparatus ofclaim 33, wherein the insulating portion surrounding
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`35. (Previously presented) The apparatus ofclaim 33, wherein at least one ofthe following: the
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`comprises a dielectric material having a stress ofS x 108 dynes/cmz or less; one ofthe first
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`process technology than another of the first and second integrated circuits, the different process
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`technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM,'
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`EEPROM, Ferroelectric and Giant Magneto Resistance; at least one of the first integrated circuit
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`circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit
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`MICRON ET AL. EXHIBIT 1026
`Page 9 of 16
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`interconnections traverse at least one of the integrated circuits; continuous vertical
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`interconnections connect circuitry of the first and second integrated circuits; information
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`processing is performed on data routed between circuitry on the first and second integrated
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`circuits; at least one integrated circuit has reconfiguration circuitry; vertical interconnects
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`connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect
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`comprising a conductive center portion and a insulating portion surrounding the conductive
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`center portion, the insulating portion comprising a dielectric having stress of5 x 108 dynes/cmz
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`or less; at least one ofthe circuit substrate and the first integrated circuit is substantially flexible;
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`at least one of the circuit substrate and the first integrated circuit comprises a dielectric layer with
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`a stress ofabout 5 x 108 dynes/cmz or less.
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`36. (Previously presented) The apparatus ofclaim 33, wherein at least two ofthe following: the
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`insulating portion surrounding the conductive center portion of said vertical interconnects
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`comprises a dielectric material having a stress of5 x 108 dynes/cmz or less; one ofthe first
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`integrated circuit and the one or more additional integrated circuits is formed using a different
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`process technology than another of thelfirst and second integrated circuits, the different process
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`technology being selected from a group consisting ofDRAM, SRAM, FLASH, EPROM,
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`EEPROM, Ferroelectric and Giant Magneto Resistance; at least one of the first integrated circuit
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`and the one or more additional integrated circuits comprises a microprocessor; the first integrated
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`circuit and the one or more additional integrated circuits comprise at least one memory integrated
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`circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit
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`performs testing ofthe at least one memory integrated circuit; a plurality of interior vertical
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`10
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`MICRON ET AL. EXHIBIT 1026
`Page 10 of 16
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`interconnections traverse at least one of the integrated circuits; continuous vertical
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`interconnections connect circuitry of the first and second integrated circuits; information
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`processing is performed on data routed between circuitry on the first and second integrated
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`circuits; at least one integrated circuit has reconfiguration circuitry; vertical interconnects
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`connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect
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`comprising a conductive center portion and a insulating portion surrounding the conductive
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`center portion, the insulating portion comprising a dielectric having stress of5 x 108 dynes/cmz
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`or less; at least one of the circuit substrate and the first integrated circuit is substantially flexible;
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`at least one of the circuit substrate and the first integrated circuit comprises adielectric layer with
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`a stress of about 5 x I08 dynes/cmz or less.
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`37. (Currently amended) The apparatus of claim 33, wherein at least three ofthe following: the
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`insulating portion surrounding the conductive center portion of said vertical interconnects
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`comprises a dielectric material having a stress of5 x I08 dynes/cmz or less; one of the first
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`integrated circuit and the one or more additional integrated circuits is. formed using a different
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`process technology than another of the first and second integrated circuits, the different process
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`technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM,
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`EEPROM, Ferroelectric and Giant Magneto Resistance; at least one ofthe first integrated circuit
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`and the one or more additional integrated circuits comprises a microprocessor; the first integrated
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`circuit and the one or more additional integrated circuits comprise at least one memory integrated
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`circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit
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`performs testing of the at least one memory integrated circuit; a plurality of interior vertical
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`interconnections traverse at least one of the integrated circuits; continuous vertical
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`ll
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`MICRON ET AL. EXHIBIT 1026
`Page 11 of 16
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`interconnections connect circuitry_of the first and second integrated circuits; information
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`processing is performed on data routed between circuitry on the first and second integrated
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`circuits; at least one integrated circuit has reconfiguration circuitry; vertical interconnects
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`connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect
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`comprising a conductive center portion and a insulating portion surrounding the conductive
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`center portion, the insulating portion comprising a dielectric having stress of 5 x 108 dynes/cmz
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`or less; at least one ofthe circuit substrate and the first integrated circuit is substantially flexible;
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`at least one ofthe circuit substrate and the first integrated circuit comprises a dielectric layer with
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`a stress ofabout 5 x 108 dynes/cmz or less.
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`33. (Currently amended) The apparatus ofelaim~1-;-claim 41 further comprising vertical
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`interconnects connecting the circuit substrate and circuitry of the first integrated circuit, each
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`vertical interconnect comprising a conductive center portion and a insulating portion surrounding
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`the conductive center portion, the insulating portion comprising a dielectric having stress of5 x
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`108 dynes/cm2 or less.
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`39. (Currently amended) The apparatus ofelaim—l~,—clain1 41), wherein at least one ofthe circuit
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`substrate and the first integrated circuit is substantially flexible.
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`40. (Previously presented) The apparatus ofclaim 39, wherein the at least one ofthe circuit
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`substrate and the first integrated circuit comprises a dielectric layer with a stress of about 5 )4
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`I03 dynes/cmz or less.
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`MICRON ET AL. EXHIBIT 1026
`Page 12 of 16
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`41. (New) The apparatus of claim 29, wherein the at least one of the first integrated circuit and
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`the one or more additional integrated circuits comprises integrated circuitry defining an
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`integrated circuit die having an area, wherein the substrate of the at least one of the first
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`integrated circuit and the one or more additional integrated circuits extends throughout at least a
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`substantial portion ofthe area ofthe integrated circuit die.
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`42. (New) The apparatus of claim 41, wherein the substantially flexible semiconductor substrate
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`is one thinned by parting the semiconductor substrate at a parting layer comprising implanted
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`MICRON ET AL. EXHIBIT 1026
`Page 13 of 16
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`The prior Office Action has been carefully considered. Reconsideration in view of the
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`foregoing amendments and the present remarks is respectfully requested.
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`REMARKS
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`Claims 1-40 were rejected as being anticipated by Leedy. The claims have been amended
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`to more clearly distinguish over the cited reference. Reconsideration is respectfully requested.
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`In particular, the claims have been amended to recite in part a substantially flexible
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`semiconductor substrate. No such feature is taught or suggested by Leedy.
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`Leedy (FIG. 8) discloses a flexible layer made up of a huge number of tiny
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`semiconductor islands embedded within dielectric. Each semiconductor island corresponds to a
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`device such as a transistor. That flexible layer is not believed to be a “substrate” within the
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`reasonable commonly-accepted meaning of that term. Certainly that flexible layer cannot be
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`considered to be a “semiconductor substrate,” since structural integrity of the flexible layer,
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`which is the function of a substrate to provide, derives not from semiconductor material but
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`Considering a single one of the tiny islands of semiconductor material, nor is such an
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`island believed to be a “substrate” within the reasonable commonly-accepted meaning of that
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`term. Moreover, given the minute dimensions of such an island, the island of semiconductor
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`itself is not flexible as claimed; rather, it is rigid.
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`14
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`MICRON ET AL. EXHIBIT 1026
`Page 14 of 16
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`Accordingly, the claims as amended are believed to patentably define over the cited
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`Moreover, numerous features of the dependent claims alleged to be shown by Leedy are
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`not in fact shown by Leedy. None of the features relating to memory integrated circuits are
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`believed to be taught or suggested by Leedy. That is, while Leedy may teach one particular
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`embodiment of a stacked integrated circuit (FIG. 8), it does not teach or suggest the features of at
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`least dependent claims 11-13, 18-26 and 35-37.
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`Lccdy (FIG. 3 lb) docs teach “control and/or mcmory logic 712, 713
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`fabricated as part
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`of [an] MD] circuit membrane display 700.” This embodiment of Leedy is unrelated to the
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`stacked integrated circuit embodiment of FIG. 8 of Leedy. Beyond this bare mention of memory
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`fabricated as part of a planar display, Leedy does not contain any teachings relevant to the
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`foregoing dependent claims.
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`New dependent claims including claim 40 have been added, claim 40 reciting a flexible
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`semiconductor substrate that extends throughout at least a substantial portion of an integrated
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`circuit die. Such a feature, as already discussed, is clearly not taught or suggested by Leedy,
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`which instead teaches the opposite.
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`MICRON ET AL. EXHIBIT 1026
`Page 15 of 16
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`If any further amendment or clarification is believed to be required, Applicant requests
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`that the Examiner contact the undersigned at (408) 674-0271 in order to expedite prosecution of
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`the present application.
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`Respectfully submitted,
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`/Michael J. Ure/
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`Michael J. Ure, Reg. 33,089
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`Dated: 7/30/2012
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`MICRON ET AL. EXHIBIT 1026
`Page 16 of 16