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`BUWS D01’-INE SHECKER
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`FHX NO.
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`85"-‘°-338934
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`CERTIFICATE OF FACSIMILE TRANSMISSION
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`I-Hsmgsy CERTIFY THAT THIS CORRESPONDENCE IS BEING FBCSIMILE TRANSMITTED TO THE‘.
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`PATENT AND TRADEMARK OFFICE ON THE DATE SHOWN BELOW.
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`Name of person signing certification:
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`Sharon E. Ryan
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`Date:
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`Signature:
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`’£4'—-'-v-vs.-I 2»-
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`Attorney's Docket No. 11033533151
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`1,0 I L
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`Group Art Unit: 2822
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`Examiner: Collins, D.
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`In re Patent Application of
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`Glenn J. Leedy
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`Application No.: 08/835,190
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`Filed: April 4, 1997
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`For: THREE DIMENSIONAL
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`STRUCTURE MEMORY
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`Assistant Commissioner for Patents
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`Washington, D.C. 20231
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`Sir:
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`The following remarks are responsive to the Office Action of August 21, 1998.
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`The Officc Action of August 21, 1998 has been carefully considered. Reconsideration
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`REMARKS
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`and allowance of the application in view of the following Remarks is respectfully requested.
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`The Office Action states in Paragraph 5 thereof, "Applicant's arguments with respect to
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`claims 1, 3-23, 25-30, and 62-107 have been considered but are moot in View of the new
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`ground(s) of rejection. New references disclosing multilayer interconnection systems have
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`been added."
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`In other respects the Office Action would appear to be substantially the same as the
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`MICRON ET AL. EXHIBIT 1025
`Page 1 of 9
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`SEP-11-98 FRI 10:33 All
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`BUPNS DOHNE Sl-JEGKER
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`FHX NO. 8502338934
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`Application Serial No. 08/835,190
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`Attorney’s Docket No. 008442-057
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`Page 2
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`previous Office Action of January 28, 1998. Applicant submits that the newly-cited references
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`of Miller and Bureau (cited by Applicant in the Disclosure Statement of September 19, 1997)
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`are not especially germane to the claimed invention, nor is Finnila, cited by Applicant in a
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`subsequent disclosure statement of July 23, 1998. Applicant further maintains that the claimed
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`invention is not taught or suggested by Yasumoto, for reasons set forth hereafter.
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`First in regard to Miller, Miller does not relate to the stacking of integrated circuit
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`wafers but rather relates to stacking of printed circuit board modules. Note, for example, col.
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`3, lines 47-54:
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`Fig. 5 is a perspective view of a stack comprising identical modules 10-
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`1, 10-2 and 10-3 mounted on mother board '20, with connectors 50 serving both
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`as spacers and as means for interconnecting opposing connecting areas on the
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`modules and mother board. Such connectors can be the stacking connectors or
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`elastorncric connectors described above, or other suitable connectors.
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`Bolting together printed circuit boards as in Miller is far afield from the claimed
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`invention.
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`In regard to Bureau. Bureau discloses depositing a layer of polyimidc onto a substrate
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`(column 4, last sentence). A multi—layer metallpolyrner electrical interconnection system is
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`then built up layer by layer. Chips are then installed to form a 2-D circuit structure. Multiple
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`2-D structures may be joined to form a 3-D circuit structure using an intervening "stencil" or
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`frame. As illustrated in the figures of Bureau, the stencil surrounds each individual chip.
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`Although not mentioned in Bureau, typically with such a structure an underfilling technique
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`would be used in which a resin is injected so as to fill the remaining spaces between the chips
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`and stencil and the polymeric substrate. Such underfilling is typically required to overcome
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`the effects of CTE (coefticient of thermal expansion) mismatch. Bureau fails to teach or
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`suggest the claimed invention.
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`Furthermore, Finnila, cited by Applicant fails to teach or suggest the claimed invention.
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`MICRON ET AL. EXHIBIT 1025
`Page 2 of 9
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`SEP-ll-98 FRI 10:34 fill
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`BURNS DOHNE SWECKER
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`FGX NO. B5fl9.33B934
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`Application Serial No. 08/835,190
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`Attorncy’s Docket No. 008442-057
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`Page 3
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`Finnila teaches forming a silicon device layer on top of an insulating layer (so-called
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`Silicon-On—Insu1ator, or $01); i.c. , Finnila uses SOI substrate processing techniques to achieve
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`an isolated semiconductor layer on a rigid, standard-thickness substrate. He subsequently thins
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`the substrate, but always keeps the thinned substrate bonded to a rigid substrate, such as the
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`temporary substrate (26) or the permanent substrate (structure 1 or 42).
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`processing.
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`In Finnila, all device processing (thermal oxide formation, doping, annealing, contact
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`drive-in, etc.) is performed before the SOI substrate is thinned. The only steps that Finnila
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`performs after the SOI substrate is thinned are metallization and dielectric deposition
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`It should be made clear that although he says that "conventional processing steps"
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`(5:31-36) are used, these steps are highly restricted due to the requirement that processing
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`temperatures be limited to less than 132°C, which is the melting point of Indium. Furthermore,
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`based on typical characteristic of available waxes, the "wax" or bonding layer (24, 514-5) used
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`to temporarily hold the SOI wafer for thinning and backside processing has a maximum
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`temperature of 200°C. Applicant knows of no waxes that would be compatible with llZl.Cl.1lll'J'1
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`processing of dielectric deposition or vacuum dry etching (called RIE) due to outgassing
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`(which would cause the temporarily restrained substrate to delaminate from the holding
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`substrate 26) or temperature (typically in excess of 350°C for oxide and nitrides). Presumably,
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`Finnila is using spin-on glass dielectric with very low curing temperatures and wet etch
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`processing. The aluminum film of the aluminum I/O bond pads applied to the last circuit layer
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`necessary 1"or wiring bonding (5134-35). however, can only be deposited through a sputtering
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`process step which is a vacuum process step; Applicant knows of no "wax" which can
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`withstand vacuum processing without outgassing which would delaminate the thinned
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`substrate.
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`Finnila does not indicate a need to use low-stress dielectrics. Furthermore, the
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`dielectrics he is using (thermal oxide or spin—on glass) are known to have very high
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`compressive stresses in excess of 1 x 10"’ dynes cm’, which would be sufficient to cause the
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`semieonductor layer to delaminate from the “wax" or the Indium bump with epoxy unclcrfill.
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`MICRON ET AL. EXHIBIT 1025
`Page 3 of 9
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`SE_P-l1-98 FRI 10:34 All
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`BUR“? DUANE SNECKER
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`FAX N0. 8507338934
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 4
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`Serious doubt is therefore cast on the workability of Finnila.
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`Unlike Miller and Bureau, Finnila docs teach forming an interconnect that passes
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`In other respects, however, the method of Finnila is far
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`different from that of the present invention. Finnila does not teach or suggest the claimed
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`sequence of bonding two substrates by themial diffusion bonding, thinning one of the bonded
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`substrates, and performing backside processing of the thinned substrate to form pass—throughs
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`and contacts. Moreover, Finnila contains no suggestion of forming a semiconductor memory
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`controller on one substrate and a semiconductor memory array on a separate substrate as
`recited in Claim 1.
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`Hence, none of the foregoing references lends substantial strength or suppoit to the
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`primary reference, Yasumoto.
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`As explained in the previous response. the bonding and interconnect methods.
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`especially, of the invention of Claim 1 are far different from those of the prior art. In
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`accordance with the invention, bonding occurs by thennal diffusion bonding. As described in
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`the specification, various metals commonly used in semiconductor processing are particularly
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`amenable to thermal diffusion bonding in which complementary surfaces are bonded together
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`through the application of heat and pressure. A requirement for thermal diffusion bonding is
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`that the complementary surfaces be highly planar. This degree of planarity is achieved using a
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`semiconductor processing technique of only recent origin known as Chemical Mechanical
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`Polishing, or CMP. The materials and methods used to perform thermal diffusion bonding as
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`described and claimed are fully compatible with existing semiconductor processing techniques.
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`Hence, a bonding step may be followed by further semiconductor processing, which may in
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`turned be followed by a further bonding step. etc. A three-dimensional device stack having a
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`large number of device layers may thereby be produced. Furthermore, three-dimensional
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`processing is performed at the wafer level as opposed to at the chip level. The number of work
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`pieces to be handled is therefore greatly reduced, typically several hundred-fold, as compared
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`to thrcc—dimensio11al processing techniques performed at the chip level.
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`MICRON ET AL. EXHIBIT 1025
`Page 4 of 9
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`SF'P-ll-98 FRI 10:35 All
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`BURW DORNE SI-JECKER
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`Fl’-ix N0. 8509338934
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`Application Serial No. 08/835,190
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`Attorn:y’s Docket No. 008442-057
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`Page 5
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`Yasumoto perfomls bonding together offlnirhed chips to form three-dimensional
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`structures. (Yasurnoto, col. 10, lines 6~17; col. 13, lines 38-40.) Further conventional
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`semiconductor processing steps (which are invariably performed in wafer form) are not
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`contemplated, but rather are precluded. In Yasumoto. bonding depends upon an adhesive resin
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`layer. This layer is intended to address the planarity problem, which could not have been
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`addressed by CMP, since the reference predates by nearly a decade the advent of CMP. (The
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`use of such adhesive resin layers would, by itself, be likely to preclude further conventional
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`semiconductor processing of a three-dimensional structure in that such layers cannot, in
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`general, tolerate the high levels of heat associated with typical semiconductor processes.)
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`Also in accordance with the invention, interconnects are formed that pass entirely
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`(Specification, page 15. step
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`through whole substrates. This interconnect structure is referred to in the specification as fine-
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`grain vertical interconnect. As further described in the specification, such fine grain Vertical
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`interconnects are formed by thinning and backside processing of :1 preceding substrate and
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`complementary frontside processing of a succeeding substrate,
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`'3). followed by bonding of the backside and complementary frontside. This sequence may be
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`repeated an arbitrary number of times to produce :1 stacked IC of 10 layers, 20 layers or more.
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`With the exception of Finnila, none of the references teach or suggests an interconnect
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`that passes through a substrate. Accordingly, all of the references are limited to two circuit
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`layers where those circuit layers are formed within a substrate. Yasumoto (col. 12, lines 60-64)
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`alludes to the possibility of a three-dimensional semiconductor structure having four or more
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`multilayer structure portions obtained when two or more of the multilayer structural portions
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`118 are provided between two outer multilayer structural portions 24 and 24'. The
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`intermediate circuit layers of such a structure, however, are not formed within a substrate but
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`rather are thin-l'1lm transistor layers formed an a substrate with the substrate being
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`subsequently removed. (Yasurnoto, Figure 7 and 3. Interconnects 112 and 134 pass through 3
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`TFT device layer but do not pass through a substrate, the substrate having been removed.)
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`Only in the case of the two outer multilayer structural portions 24 and 24' is the circuit layer
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`MICRON ET AL. EXHIBIT 1025
`Page 5 of 9
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`SEVP-11-B8 FRI 10:35 All
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`BURN‘? DUANE SHECKER
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`FHX N0.
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`-6502338934
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`formed within the substrate.
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`Application Serial No. 081835.190
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`Attorncy’s Docket No. 008442-057
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`Page 6
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`The following table identifies for each figure in Yasumoto the substrates shown in that
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`In no instance does an interconnect pass through the substrate.
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`figure.
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`TABLE I
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`YASUMOTO FIGURE
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`F: ure 2
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`Fl-
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`12.12-
`26, 26'
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`60, 60‘
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`Figure 6(g)
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`84 (multilayer structure not shown:
`cal. 11, lines 6-7)
`12 12-
`26.
`_.._. . "mm
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`The same analysis applies equally to each of the secondary references.
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`A fine-grain interconnect structure passing through a substrate can only be formed if
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`the substrate is very thin. A small hole (less then 1 um) might be formed in a conventional
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`thick substrate, but the apcct ratio of the hole would be so large (e.g.. 75:1 to 350:1) as to
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`make filling the hole with metal impossible using known techniques. Of the cited references,
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`Sanders was cited as disclosing a multiple chip package with thinned semiconductor chips
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`using a grinding disk to remove material. Sanders, however, teaches backside circuit thinning
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`(in die form, not wafer form) for the purpose of cooling. None of the references teaches or
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`suggests the formation of a fine-grain vertical interconnect through a substrate in the manru.-.1‘ of
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`claim 1.
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`The technique of Yasumoto, besides being limited to only two device-bearing
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`MICRON ET AL. EXHIBIT 1025
`Page 6 of 9
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`SEP-ll-98 FRI 10:38 All
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`BURN DURNE Sl-IECKER
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`FAX N0. 8502338934
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`Application Serial No. 08/835,190
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`Attorney/’s Docket No. 008442-057
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`Page 7
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`substrates. is limited in various other important respects. Referring to Figure 4 and 5 of
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`Yasutnoto, for example. the only way to provide for connection to a threedimensional
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`structure of the type disclosed in Yasumoto is for one layer to have a larger extent than another
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`layer. A portion of the surface of the larger layer therefore remains exposed, allowing bond
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`pads to be formed thereon. The bond pads may be wire bonded to leads of an MCM (multi-
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`In the case of the present invention, as recited in claim
`chip module) package, for example.
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`96, bond pads are formed on the backside of a final thinned substrate. The resulting multilayer
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`structure is therefore comparable. in size and bond pad layout, to a single conventional
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`integrated circuit, compatible with existing single-chip packages.
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`Another problem not discussed in Yasumoto is that of film stress. Semiconductor films
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`are not stress-free but exhibit certain stress levels depending on many factors including
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`material, deposition technique, etc. A thick film exhibits proportionally greater stress than a
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`thin film. Stress is relieved either by bending or cracking -— i.e., either the substrate gives or
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`the film gives. Using conventional highc1'—strcss dielectric films of silicon dioxide and silicon
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`nitride (commonly used in conventional memory circuit fabrication), the technique of
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`Yasumoto would likely be limited to no more than three layers as shown in Figure 8.
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`Additional layers would be likely to cause peeling apart of the layers at the adhesive interface.
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`In the case of the present invention, on the other hand, low—stress dielectrics (less than
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`5 x 10“ dynes (ctr?) are used as described on page 14 of the present specification and further
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`described in U.S. Patent 5,354,695 of the present inventor. Stress buildup and consequent
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`bending or cracking is therefore avoided. The number of layers is not stress-limited.
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`A summary of some of the most salient differences between Yasutnoto and the present
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`invention, together with an indication of where that difference is reflected in the claims. is
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`presented in the following table:
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`MICRON ET AL. EXHIBIT 1025
`Page 7 of 9
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`SEP-11-98 FRI 10:37 All
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`EUR“! DOHNE SLIECKER
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`FAX N0. 8509338934
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 8
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`YASUMOTO
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`Begin with chip (die) having
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`topmost adhesive layer. with
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`contacts through adhesive
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`Prepare additional chip (die)
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`having adhesive layer, device
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`layer. then substrate, with
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`contacts through adhesive layer
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`and device layer; band together
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`with previous chip, adhesive
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`layer first.
`Remove substrate
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`Repeat preparing. bonding and
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`removing steps for as many
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`(stress, adhesive degradation
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`from heat) allow.
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`Bond additional chip (die),
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`leave substrate; either first chip
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`or last chip must have larger
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`area to allow for bond pads.
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`TABLE II
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`
`RELEVANT CLAIM
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`LANGUAGE
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`...wherein said substrates are
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`semiconductor wafers...
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`(claims 95, I02); .. .formed
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`using low—stress dielectric...
`(claims 97. 104)
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`...saicl bonding is thermal
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`diffusion bonding of the lirst
`substrate to the second
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`substrate... (claims 1, 62)
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`...the backside of one of said
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`substrates is thinned and then
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`processed to form
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`interconnections that pass
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`through said substrate and to
`form contacts on the backside
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`of said substrate... (claims 1.
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`62)
`M
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`.. .bonding at least one
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`additional substrate to the
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`stacked IC substrate. .. (claims
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`14 and 65)
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`...forrning bond pads on the
`backside of the final
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`substrate... (claims 98, 105)
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`...dicing at resulting stacked
`wafer into individual stacked
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`10;... (claims 96, 103)
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`PRESENT INVENTION
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`Begin with wafer fabricated
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`using low—stress dielectrics
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`Bond additional wafer
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`(fabricated using low-stress
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`dielectrics) to previous wafer
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`by thermal diffusion bonding,
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`e.g., metal thermal diffusion
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`bonding.
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`Thin backside of additional
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`wafer, process backside to
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`Repeat bonding and thinning
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`steps for as many wafers as
`desired.
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`Form bond pads on backside of
`final wafer.
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`Dice wafer stack into 3D chips.
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`MICRON ET AL. EXHIBIT 1025
`Page 8 of 9
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`SEP-"11~BB FRI 10:37 All
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`BURNS DUANE SNECKER
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`FAX N0. 85172338934
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`Application Serial No. 08/835,190
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`Attorney’s Docket No. 008442-057
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`Page 9
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`Claim 62 has previously been amended to recite thinning substrates on which integrated
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`circuits are formed to form thinned substrates, facilitating forrnation of interconnects, and
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`performing backside processing of the substrates. Thinning of a substrate is technically very
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`different from removing a substrate. As recited in claim 75, in the preferred embodiment of the
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`present invention, a substrate is thinned such that a thin device layer remains. Devices within
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`this device layer are formed within a portion of the substrate, which may be monocrystalline
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`silicon, for example. High«qua.lity transistors result. Where devices are formed on (not within)
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`a substrate which is later removed, as in Yasumoto, the device layer, because it is not part of
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`the substrate, remains when the substrate is removed. However, the quality of the transistors
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`that may be formed in such a layer suffers. While the quality of such transistors may suffice
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`for purposes of an LCD display, for example, the quality does not generally suffice for
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`realizing a memory or memory controller.
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`Again, none of the prior art references teaches or suggests the combination of features
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`of claim 62. New claims 92-106 have been previously added, drawn to various other
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`significant features of the invention.
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`Accordingly, Claims 1 and 62 are believed to patentably define over the cited
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`references, as is newly—added independent claim 106. Claims 2-30 and 63-103 are also
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`believed to add novel and patentable subject matter to their respective independent claims.
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`Withdrawal of the rejection and allowance of Claims 1-30 and 62-106 is therefore respectfully
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`y
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`requested.
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`Respectfully submitted,
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`BURNS. DOANE. SWECKER dz MATHIS, LLP
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`Post Office Box 1404
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`Alexandria, Virginia 22313-1404
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`(650) 854-7400
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`Date: September 8, 1998
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`By;
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`[L-r__
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`Michael J .
`
`e
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`Registration No. 33,089
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`MICRON ET AL. EXHIBIT 1025
`Page 9 of 9