CERTIFICATE OF FACSIMILEZ TRANSMISSION
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`I HEREBY CERTIFY THAT THIS CORRESPONDENCE TS RETNG F‘A{‘.RTMT‘I.E TRANSMITTED To THE
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`Name of person s_:'.9'ning certification:
`Sharon E. Ryan
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`Signature:_____§%-4--'_--f---r
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`Attorney's Docket No. Qflflfifi-@551
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`Group Art Unit: 1104
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`Examiner: Collins. D.
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`) )) ) ) ) ) ) ) )
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`In re Pattul. Application of
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`Glenn J’. Leqdy
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`Application No.: O8l835,190
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`Filed: Apri14. 1997
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`For: THREE DIIVIENSIONAL
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`STRUCTURE MEMORY
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`BEfl
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`ones-mo
`as/all/1995 asmnmr ooooooos oasaoo
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`143_o9lgfisista.nt Commissioner for Patents
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`41.00\fiIu-shingtun, D.C. 20231
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`Sir:
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`Responsive to the Offioe Action of January 28, 1998, please amend this application as
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`.___.___:_._j»'-
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`005/00/199! JPRMTBR 00000011 024800
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`55. 00 DH
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`1. (Amended) A method of forming a. random—acccsa mommy, comprising the steps of:
`fabricating a memory circuit on a first substmtc;
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`fabricating a memory uuntrullcr circuit on a second substrate; [and]
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`bonding the fist and second substrates to form interconnects between the
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`39:11 am. 86-90-AU!-I IN-ledl-U00
`uaqumu xed
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`7|,
`86/9/9
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`:saBed
`rama
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`(pepaaoons we/xg) 1uaAa pangaoaa
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`MICRON ET AL. EXHIBIT 1024
`Page 1 of 13
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`memory circuit and the memory controller circuit, neither the first substrate alone nor
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`the second substrate alone being sufficient to provide random access data storage,
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`LU/.(Amended) The method of Claim 1, [wherein said bonding is thermal diffusion
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`bonding of the first substrate to the second substrate to form a stacked IC structure, the
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`method] comprising the further steps of:
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`fabricating at least one additional memory circuit on at least one additional
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`bonding the at least one additional substrate to the stacked IC substrate and
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`forming interconnects between the at least one additionai memory circuit and the
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`memory controller circuit. wherein at {east some of the interconnects pass through a
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`substrate on which a memory circuit is formed.
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`)5/(Amended) The method of [Claim 14, further comprising the step of:
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`171/80 ‘cl
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`:adA_L
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`£9111 3fl.L 86-90-NH Muedwog
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`7|,
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`(papaaoons mama) ;uaA_:_| pangaoaa
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`MICRON ET AL. EXHIBIT 1024
`Page 2 of 13
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`Application Serial'No_ D8/835,190
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`Attorney's Docket No. 008442-057
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`thinning substrates on which memory circuits are formed to form thinned
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`substrates. facilitating formation of said intcrcomtcctsl
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`(Amended) A method of bonzfing together multiple substrates each having
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`integrated circuits formed thereon to form interconnections between the integrated circuits, the
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`method comprising the steps of:
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`processing a mating surface on each of firs: and second substrates to achieve
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`substantial pianarity of the mating surfaces;
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`fanning
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`fine-grain interconnect patterns on the mating surfaces; rand]
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`performing finnugrain, planar thermal diffusion bonding of the mating
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`Z-fii (Amended) The method of Claimfi [further comprising the step of:
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`th.1'nn.ing substrates on which memory circuits are formed to form thinned
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`substrates, facilitating formation of said imerconnects]
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`tad-<1
`:1oa_rqns
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`uapuas
`39!-U!J.
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`Wd 61152
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`29:11 HILL as-so-mu utuedwoo
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`Vt
`86/99
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`:sa6ed
`33130
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`(papaaoons mana) 1U9A3 pa/uaoau
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`MICRON ET AL. EXHIBIT 1024
`Page 3 of 13
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`Application Serial No. 08/835,190
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`ArDorney's Docket No. 008442-057
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`Please add the following new Claims:
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`include interconnect metallimtion and non-interconnect metallization;
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`whereby thermal diffusion bonding simultaneously achieves electrical
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`interconnection through said interconnect xnetallization and mechanical bonding through
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`said non-interconnect metaiiization.
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`/9K The method of claim/92’ wherein. prior to said thermal diffusion bonding, at least
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`one of the surfaces to be bonded is planarized using chemical/mechanical polishing.
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`(pi
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`347 The method of claim/93‘, wherein both of the surfaces to be bonded are planarizcd
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`using chemical/mechanical polishing.
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`£57 The method of claim 1, wherein said substrates are semiconductor wafers‘
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`comprising the further step ofdicing a resulting stacked
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`wafer into individual stacked ICs.
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`The method-of claim 1, wherein said memory controller circuit and said memory
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`circuit are fonned using low-stress dielectric.
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`=3dKJ.
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`ii.
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`5 E
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`MICRON ET AL. EXHIBIT 1024
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`Attorney's Docket No. 008442-057
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`/Q8'. The method of claimJr4/,/comprising the further step of, during backside processing
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`of a final substrate to form part of said random-access memory. forming bond pads on the
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`backside of the final substmte.
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`2.?
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`/99‘. The method of Claimfix wherein surfaces bonded by thermal diffusion bonding
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`include interconnect metallization and non—ini:erconnect tnetallizalion;
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`whereby thermal diffusion bonding simultaneously achieves electrical
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`interconnection through said interconnect metallization and mechanical bonding through
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`3.90. The method of claim ,62,/wherein, prior to said tlztermal diffusion bonding, at least
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`one of the surfaces to be bonded is planarized using chemical/mechanical polishing.
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`94;?
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`[L01 The method of claim , wherein both of the surfaces to be bonded are pianarized
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`}02'. The method of claim 52', wherein said substrates are semiconductor wafers.
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`M. The method of claim
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`comprising the further step of dicing a resulting
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`(papaaaons Juan-=1) iuang paniaaea
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`MICRON ET AL. EXHIBIT 1024
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`Attaorncy's Docket No. 008442-057
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`1J)[.ef. The method of claim,52, wherein said itttegrated circuits are formed using low-
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`J25. The method of claim/69,/comprising the further step of, during backside
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`processing of a final substrate to form part of said random~acccss memory, forming bond pads
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`mory structure comprising:
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`a first substrate; at
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`substrate to form conductive paths
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`REMARKS
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`The Office Action of January 28, 1998 has been carefully considered.
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`In response
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`thereto, the claims have been amended as set forth above. Withdrawal of the rejection and
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`allowance of the present application in view of the foregoing amendments and the following
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`remarks is respectfully requested.
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`=9d5.L
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`:;oa.fqns
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`99: H 3fl.I. 88*9U-ABM IKUEUIIJOO
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`17L
`86/9/9
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`:JaqumN xag
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`(papaaoons iua/ta) iuang pemgaoay
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`MICRON ET AL. EXHIBIT 1024
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`Attorney's Docket No. 008442-057
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`Claims 1 and 62 were rejected as being anticipated by Yasumoto er al. Claims 2-30 and
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`63-91 were rejected as being unpatentable over Yasumoto et al. in view of various secondary
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`references. including Grcenwald et al.. Val. Goossen. Nakamishi ct a1.. Sanders and Thomas
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`et al. Claims 1 and 62 have been amended to more clearly define over the cited references.
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`Reconsideration is respectfully requested.
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`More particularly, Claim 1 has been amended to recite forming a stacked IC structure
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`by thermal diffusion bonding of a memory circuit on a first substrate and a memory controller
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`circuit on a second substrate. including thinning and processing the backside of one of the
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`substrates to form interconnections that pass through the substrate and to form. contacts on the
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`backside of the substrate. No such features are taught or suggested by the cited references.
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`The bonding and interconnect methods, especially, of the invention of Claim 1 are far
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`different from those of the prior art. In accordance with the invention. bonding occurs by
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`thermal diffusion bonding. As described in the specification, various metals commonly used in
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`semiconductor processing are particularly amenable to thermal diffusion bonding in which
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`complementary surfaces are bonded together through the application of heat and pressure. A
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`requirement for thermal diffusion bonding is that the complementary surfaces be highly planar.
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`This degree of planarity is achieved using a semiconductor processing technique of only recent
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`origin Known as Chemical Mechanical Polishing, or CMP. The materials and methods used to
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`perform thermal diffusion bonding as described and claimed are fiilly compatible with existing
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`semiconductor processing techniques. Hence, a bonding step may be followed by further
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`13551
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`:1oe_rqn3
`uapuas
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`'
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`99111 311.1. 88-SD-ASH 35”!’-W100
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`1;],
`95/9/9
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`:.l3ql.LInN xeg
`:safied
`39190
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`(papaeoons tuang) iuang pa/qaaaa
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`MICRON ET AL. EXHIBIT 1024
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`Application Serial No. 08/835,190
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`semicontluctor processing, which may in turned be followed by a further bonding step, etc. A
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`three-dimensional device stack having, a large number of device layers may thereby be
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`produced. Furthermore, three-dimensional processing is performed at the wafer level as
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`opposed to at the chip level. The number of work pieces to be inuurlled is therefore greatly
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`reduced, typically several hundred-fold, as compared to three-dimensional processing
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`techniques performed at the chip level.
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`Yasurnoto performs bonding together offinished chips to form uuee-dimensional
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`structures. (Yasumoto. col. 10, lines 6-17; cot. 13, lines 38-40.) Furtner conventional
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`semiconductor processing steps (which are invariably performed in wafer form) are not
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`contemplated, but rather are precluded. In Yasumoto. bonding depends upon an adhesive resin
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`layer. This layer is intended to address the planarity problem, which could. not have been
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`addressed by CMP, since 1he.refeten<:.e predates by nearly a decade the advent of CMP. (The
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`use of such adhesive resin layers would, by itself, be likely to preclude further conventional
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`semiconductor processing of a three—dimensional structure in that such layers cannot, in
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`general, tolerate the high levels of heat associated with typical semiconductor processes.)
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`Also in accordance with the invention, interconnects are formed that pass entirely
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`through whole substrates. This interconnect structure is referred to in the specification as fine-
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`grnin vertical interconnect. As further described in the specification. such fine grain vertical
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`interconnects are formed by thinning and backside processing of a preceding substrate and
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`complementary fi-anrside processing of a succeeding substrate.
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`(Specification, page 15, step
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`=adIu
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`:;oa_lqng
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`86/9/9
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`(papaaoons iuangl ;uaA3 pangaoau
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`MICRON ET AL. EXHIBIT 1024
`Page 8 of 13
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`Application Serial No. 08/835.190
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`Attorney's Docket No. 008442-057
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`Page 9
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`3), followed by bonding of the backside and complementary frontside. This sequence may be
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`repeated an arbitrary number of times to produce a. stacked {C of 10 layers, 20 layers or more.
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`None of the references teach or suggests an interconnect that passes through a substrate.
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`Accordingly, all of the references are limited to two circuit layers where those circuit layers
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`are formed within a substrate. Yasumoto (col. 12, lines 60-64) alludes to the possibility of a
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`three-dimensional semiconductor structure having four or more multilayer structure portions
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`obtained when two or more of the multilayer structural portions 118 are provided between two
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`outer multilayer structural portions 24 and 24'. The intermediate circuit layers of such a
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`structure, however, are not formed within a substrate but rather are th.ii1-film transistor layers
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`formed an a substrate with the substrate being subsequently removed. (Yasumoto, Figure ‘I and
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`8. Interconnects 112 and 134 pass through a TF1‘ device layer but do not pass through a
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`substrate. the substrate having been removed.) Only in the case of the two outer multilayer
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`stntctural portions 24 and 24' is the cittzuit layer formed within the substrate.
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`The following table identifies for each figure in Yasumoto the substrates shown in that
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`figure.
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`In no instance does an interconnect pass through the substrate.
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`tat/U1 ‘cl
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`99:11 am 86-90-min Muvdwoo
`::equ.InN X25
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`7|,
`86/9/9
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`:sal5ed
`19:90
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`(papaaoons iuang) iuang patuaoaa
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`MICRON ET AL. EXHIBIT 1024
`Page 9 of 13
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`Application Serial ND. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 10
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`12. 12'
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`YASUMO new i
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`Fi l'e1(f)
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`F1 re2
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`igure: 6(g)
`Fi
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`- 3
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`T F
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`84 (multi1a{er1'.~£tx1lJ_c:uir::61t;:)t shown:
`. mes
`co.
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`The same analysis applies equally to each of the secondary references.
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`A fine-grain interconnect structure passing through a substrate can only be formed it‘
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`the substrate is very thin. A small hole (less then 1 um) might be formed in a conventional
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`thick substrate, but the aspect ratio of the hole would be so large (c.g., 75:1 to 350:1) as to
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`make filling the hole with metal impossible using known techniques. Of the cited references,
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`Sanders was cited as disclosing a multiple chip package with thinned semiconductor chips
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`using a grinding disk to remove material. Sanders. however, teaches backside circuit thinning
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`(in die form, not wafer form) for the purpose of cooling. None of the references teaches or
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`suggests the formation of a finc—gra.in vertical interconnect through a substrate in the manner of
`claim 1.
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`The technique of Yusumoto, besides being limited to only two device—bearing
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`substrates, is limited in various other important respects. Referring to Figure 4 and 5 of
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`Yasumoto, for example. the only way to provide for connection to a three-dimensional
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`structure of the type disclosed in Yasumoto is for one layer to have a larger extent than another
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`=9dKJ.
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`19:11 Elfll B6-S0-AUNWIBGWOO
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`(papaaoons JUBAQ) JUQAQ pBA!909fi
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`MICRON ET AL. EXHIBIT 1024
`Page 10 of 13
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 11
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`layer. A portion of the surface of the larger layer therefore remains exposed, allowing bond
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`pads to be formed thereon. The bond pads may he wire bonded to leads of an MCM (multi-
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`ehip module) package, for example. In the case of the present invention. as recited in claim
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`96. bond pads are formed on the backside of a final thinned substrate. The resulting multilayer
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`stmcnn-e is therefore comparable, in size and bond pad layout, to a single conventional
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`integrated circuit, compatible with existing single-chip packages.
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`Another problem not discussed in Yasuruoto is that of film stress. Semiconductor films
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`are not stress-free but exhibit certain stress levels depending on many factors including
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`material, deposition technique, etc. A thick film exhibits proportionally greater stress than a
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`thin film. Stress is relieved either by bending or cracking — i_e_, either the substrate gives or
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`the film gives. Using conventional higher-stress dielectric films of silicon dioxide and silicon
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`nitride (commonly used in conventional memory circuit fabrication), the technique of
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`Yasumoto would likely be limited to no more than three layers as shown in Figure 8.
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`Additional layers would be likely to cause peeling apart of the layers at the adhesive interface.
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`In the case of the present invention, an the other hand, low—stress dielectrics (less than
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`5 x 10‘ dynes (cm’) are used- as described on page 14 of the present specification and further
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`described in US. Patent 5,354,695 of the present inventor. Stress buildup and consequent
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`bending or cracking is therefore avoided. The number of layers is not stress-limited.
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`A sutmnary of some of the most salient differences between Yasurnoto and the present
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`invention. together with an indication of where that difference is reflected in the claims, is
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`presented in the following table:
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`bl/El ‘d
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`(papaaoans we/lg) iuang pangaaag
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`MICRON ET AL. EXHIBIT 1024
`Page 11 of 13
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 12
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`PRESENT INVENTION
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`Begin with wafer fabricated
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`using low-stress dielectrics
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`Bond additional. wafer
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`dielectrics) to previous wafer
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`by thermal diffusion bonding,
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`bonding.
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`Thin backside of additional
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`wafer, process backside to
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`form contacts
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`Repeat bonding and thinning
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`steps for as many wafers as
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`desired.
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`Form bond pad: on backside of
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`final wafer.
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`RELEVANT CLAIM
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`LANGUAGE
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`...wherein said substrates are
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`semiconductor wafers. ..
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`(claims 95, 102): ...formed
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`using low-stress dielectric...
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`(claims 97, 104)
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`_..said bonding is thermal
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`diffusion bonding of the first
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`substrate... (clairns 1, 62)
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`.. .the backside of one of said
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`substrates is thinned and then
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`processed to form
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`interconnections '|'.i'13.I 133.58
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`through said substrate and to
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`of said substrate... (claims 1,
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`G2)
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`...bon<iing at least one
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`stacked IC substrate... (claims
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`...forming bond pads on the
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`substrate... (claims 98, 105)
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`Begin with chip (die) having
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`topmost adhesive layer, with
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`contacts through adhesive
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`layer.
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`Prepare additional chip (die)
`having adhesive layer, device
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`layer, then substrate, with
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`contacts through adhesive layer
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`and device layer: bond together
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`with previous chip, adhesive
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`Remove substrate
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`Repeat preparing, bonding and
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`removing steps for as many
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`from heat) allow.
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`Bond additional chip (die),
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`leave substrate; either first chip
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`or last chip must have larger
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`Dice wafer stack into 3D chips.
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`...dicing a resulting stacked
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`ICS... (claims 96, I03)
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`171/El 'd
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`:adK_1_
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`89:11 am. 86-90-AW Hiuvdwoo
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`Vl-
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`:an2a
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`(papaaoons tuang) iuang pa/naoaa
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`MICRON ET AL. EXHIBIT 1024
`Page 12 of 13
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`Page 13
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`Claim 52 has been amended to recite thinning substrates on which integrated circuits
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`are formed to form thinned substrates, facilitating formation of interconnects, and performing
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`backside processing of the substrates. Thinning of a substrate is technically very different
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`from removing a substrate. As recited in claim 75, in the preferred embodiment of the present
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`invention, a substrate is thinned such that a thin device layer remains. Devices within this
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`device layer are formed within a portion of the substrate, which may be monocrystailine
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`silicon, for example. High-quality transistors result. Where devices are formed on (not within)
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`a substrate which is later removed, as in Yasurnoto, the device layer, because it is not part of
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`the substrate, remains when the substrate is removed. However, the quality of the transistors
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`that may be formed in such a layer suffers. While the quality of such transistors may suffice
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`for purposes of an LCD display, for example, the quality does not generally suffice for
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`realizing a. memory or memory controller.
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`Again. none of the prior art references teaches or suggests the combination of features
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`of claim 62. New claims 92-104 have been added drawn to various other significant features of
`the invention.
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`Accordingly, Clairnsl and 62 are believed to patentably define over the cited
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`references, as is newly-added independent claim 106. Claims 2-30 and 63-103 are also
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`believed to add novel and patentable subject matter to their respective independent claims.
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`Withdrawal of the rejection and allowance of Claims 1-30 and 62-106 is therefore respectfully
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`requested.
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`Post Office Box 1404
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`Alexandria, Virginia 22313-1404
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`(650) 8544400
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`Date: April 28, 1998
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`Respectfully submitted,
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`BURNS, DOANE, SWECKER & MATHIS, LLP
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`By:
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`:2
`Michael I.
`Registration N0. 33,089
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`69:11 301 88-90.-,(,§{ll,w°o '
`'.JeqtunN xeg
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`H
`96/919
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`:sa5ed
`39190
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`(PBPBBQOFIS Juana) IUBAQ PSMGOBH
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`MICRON ET AL. EXHIBIT 1024
`Page 13 of 13