UNITED STATES PATENT AND TRADEMARK OFFICE
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`IINITED $l‘A'l‘ES DI-.‘PAR'l‘l\ll£N”l‘ OF (‘0M.\l|'.‘R(‘l‘Z
`United States Patent and Trademark Office
`Addirss: (_‘()MMISSIONl;R FOR PA‘I'liN1'S
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`APPLICATION NO.
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`FILING DATE
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`FIRST NAMED I.\'VE.\ITOR
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`ATTORNEY DOCKET NO.
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`COI\'FIR.\'IATION .\'O.
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`13/73-8.874
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`01/04/2013
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`Glenn .1. Lead)’
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`l30lO~IMMD2.US
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`(>033
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`05/29/20] 3
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`10232
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`USEFUL ARTS II’
`Ml(.‘HAl-LL J. U RE
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`10518 PHIL PLACE
`(.'U1>ER'1‘1N0. CA 95014
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`UM. DAVID
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`2827
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`MAII . DATE
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`05/19/1013
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`DFJ .IVF.RY MODE
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`PA]-‘l:R
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply. if any. is set in the attached communication.
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`PTOI.-90A (Rev. 04/07)
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`MICRON ET AL. EXHIBIT 1018
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`Page 1 of 10
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`Application No.
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`13/734,874
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`App|icant(s)
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`LEEDY, GLENN J.
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`Office Action Summary
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`AIA (First Inventor to File)
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`SW‘No
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`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
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`Period for Reply
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`Examiner
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`DAVID LAM
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`Art Unit
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`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE § MONTH(S) OR THIRTY (30) DAYS,
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`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
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`Extensions of time may be available under the provisions of 37 CFR1.136(a).
`In no event. however, may a reply be timely filed
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`after SIX (6) MONTHS from the mailing date of this communication.
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`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (5) MONTHS from the mailing date of this communication.
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`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
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`Any reply received by the Office later than three months after the mailing date of this communication even if timely filed, may reduce any
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`earned patent term adjustment. See 37 CFR 1.704(b).
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`—
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`Status
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`1)I:I Responsive to communication(s) filed on
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`I] A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2b) This action is non—final.
`2a)I:I This action is FINAL.
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`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`j; the restriction requirement and election have been incorporated into this action.
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`4)I:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11,453 QC. 213.
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`Disposition of Claims
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`5)EI Claim(s) 1-5 7—17and 19-32 is/are pending in the application.
`5a) Of the above claim(s) j is/are withdrawn from consideration.
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`j is/are allowed.
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`1 -5 7-17 and 19-32 is/are rejected.
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`is/are objected to.
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`j are subject to restriction and/or election requirement.
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`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
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`participating intellectual property office for the corresponding application. For more information, please see
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`:/r’xwvw,-usoto. ovi -atents/init events/'
`i1,"index.‘s or send an inquiry to I-7Pl-Iieedback{<3>usrgtoxzov.
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`Application Papers
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`10)EI The specification is objected to by the Examiner.
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`11)I:I The drawing(s) filed on j is/are: a)I:| accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85( ).
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`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
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`Priority under 35 U.S.C. § 119
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`12)|:I Acknowledgment is made of a claim for foreign priority under 35 U.S.C.§119( )—(d) or (f).
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`Certified copies:
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`a)|:I All
`b)I:| Some * c)I:| None of the:
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`1.I:| Certified copies of the priority documents have been received.
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`2.|:l Certified copies of the priority documents have been received in Application No. j
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`3.I:| Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
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`* See the attached detailed Office action for a list of the certified copies not received.
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`Interim copies:
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`a)I:I All
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`c)I:I None of the:
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`Interim copies of the priority documents have been received.
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`Attach men1(s)
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`1) E Notice of References Cited (PTO-892)
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`2) IX Information Disclosure Sfatemenf(s) (PTO/SB/08)
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`Paper No(s)/Mail Date 1/7/13 1/3/13 4/10/13.
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`U 8. Patent and Trademark Office
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`3TOL—326 (Rev. 03-13)
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`3) D jntervjew summary (PTQ.4‘| 3)
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`Paper No(s)/Mail Date.
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`4 D Om _
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`I
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`Office Action Summary
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`Part of Paper No./Mail Date 20130521
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`MICRON ET AL. EXHIBIT 1018
`Page 2 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`DETAILED ACTION
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`Respond to Preliminary Amendment
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`This office action is in response to the preliminary amendment file on 2/6/13.
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`- Claims 6, 18 have been cancelled.
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`- Claims 31 -32 are newly added.
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`— Claims 1-5, 7-17, 19-32 are pending in the application.
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`Information Disclosure Statement
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`2.
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`The information disclosure statement (IDS) filed 1/7/10, 1/8/13, 4/10/13 fails to
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`comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because no issue
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`date and name of Patentee or Applicant found on the IDS.
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`It has been placed in the
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`application file, but the information referred to therein has not been considered as to the
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`merits. Applicant is advised to resubmits the IDS with proper issue date and name of
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`Patentee or Applicant for all patents list on the IDS.
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`Specification
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`The lengthy specification has not been checked to the extent necessary to
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`determine the presence of all possible minor errors. Applicant's cooperation is
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`requested in correcting any errors of which applicant may become aware in the
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`specification.
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`MICRON ET AL. EXHIBIT 1018
`Page 3 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Claim Objections
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`4.
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`Claims 7, 12, 19, and 24 are objected to because of the following informalities:
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`claims 7, 12, 19, and 24 are depend on cancelled claims 6, 18. Appropriate correction
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`is required.
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`5.
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`Claims 28-29 are objected to because of the following informalities: The claimed
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`subject matter on claims 28-29 are not supported by the disclosure. Appropriate
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`correction is required.
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`6.
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`Claims 7, 12, 19, and 24 are objected to because of the following informalities:
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`Independent claims 1, 14, 26, 30, and consequently their dependent claims, contain the
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`limitation “substantially flexible". The terms “substantially” render the claims un-
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`clarity, since the resulting claims do not clearly set for the metes and bounds of the
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`patent protection desired.
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`Double Patenting
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`The nonstatutory double patenting rejection is based on a judicially created
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`doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the
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`unjustified or improper timewise extension of the “right to exclude” granted by a patent
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`and to prevent possible harassment by multiple assignees. A nonstatutory
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`obviousness—type double patenting rejection is appropriate where the conflicting claims
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`are not identical, but at least one examined application claim is not patentably distinct
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`from the reference claim(s) because the examined application claim is either anticipated
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`by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140
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`F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29
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`USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir.
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`1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422
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`MICRON ET AL. EXHIBIT 1018
`Page 4 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Page 4
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`F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163
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`USPQ 644 (CCPA 1969).
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`A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d)
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`may be used to overcome an actual or provisional rejection based on a nonstatutory
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`double patenting ground provided the conflicting application or patent either is shown to
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`be commonly owned with this application, or claims an invention made as a result of
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`activities undertaken within the scope of a joint research agreement.
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`Effective January 1, 1994, a registered attorney or agent of record may sign a
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`terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with
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`37 CFR 3.73(b).
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`7.
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`Claims 1-5, 7-17, 19-32 are rejected on the ground of nonstatutory obviousness-
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`type double patenting as being unpatentable over claims 1-62 of U.S. Patent No.
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`8,410,617. Although the conflicting claims are not identical, they are not patentably
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`distinct from each other because the claims of the present application are either
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`anticipated by, or would have been obvious over, the reference claims as follows:
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`With regard to claims 1-5, 7-17, 19-32, the present application recited a thin and
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`substantially flexible circuit comprising a thin semiconductor layer; a dielectric layer
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`formed on the semiconductor layer and having a stress of about 5 x 1OSdynes/cm2 or
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`less; a circuitry formed within the thin semiconductor layer and the dielectric layer
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`defining an integrated circuit die having an area, wherein the thin semiconductor laver
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`extends throughout a substantial portion of the area of the integrated circuit die, a
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`vertical interconnect conductor extending vertically through the semiconductor layer; a
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`vertical dielectric insulator extending vertically through the semiconductor layer and
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`around the interconnect conductor and having a stress of about 5 x I08 dynes/cm‘? or
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`less; wherein the thin semiconductor layer includes vertical holes etched therethrough;
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`MICRON ET AL. EXHIBIT 1018
`Page 5 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`formed in the vertical holes of the thin semiconductor layer; wherein the thin
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`semiconductor layer comprises monocystalline silicon; wherein the thin semiconductor
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`layer is formed from a semiconductor wafer; wherein the thin and substantially flexible
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`substrate has a thickness of 50 microns or less; wherein the semiconductor wafer
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`comprises monocrystalline silicon, and the thin semiconductor layer comprises
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`monocrystalline silicon from the semiconductor wafer; wherein the thin semiconductor
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`layer is unitary; wherein the thin semiconductor layer extends from edge to edge of the
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`thin and substantially flexible substrate; wherein the dielectric layer extends from edge
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`to edge of the thin and substantially flexible substrate; wherein the thin semiconductor
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`layer comprises a polished surface; a bottomside surface and a topside surface; a
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`contact formed on the bottomside surface and electrically connected to the vertical
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`interconnect conductor; an interconnect, contact or circuit formed on or near the topside
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`surface and electrically connected to the vertical interconnect conductor; wherein the
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`interconnect, contact or circuit is electrically connected to the contact on the bottomside
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`surface via the vertical interconnect, which is a mere broader version with similar
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`intended cope of claims 1-32 of U.S. Patent No. 8,410,617.
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`With regard to claims 12, 24 of the present application, the further inclusion of the
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`polished surface formed by removing material during thinning of the thin semiconductor
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`to expose a surface thereof and then polishing the exposed surface would have been
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`inherently included by the claimed invention of the U.S. Patent No. 8,410,617.
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`MICRON ET AL. EXHIBIT 1018
`Page 6 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Page 6
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`With regard to claims 28-29 the present application, the further inclusion of
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`wherein at least a portion of the thin and substantially flexible substrate contain a high
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`density of the vertical interconnect conductor and an array of at least dimension 8 x 8
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`vertical interconnect conductors would have been inherently included by the claimed
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`invention of the U.S. Patent No. 8,410,617.
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`However, if not, the use of high density vertical interconnect conductor and an
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`array of at least dimension of 8 x 8 would have been known and available in the art.
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`It
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`would have been obvious to one of the ordinary skill in the art at the time if the invention
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`to modify Leedy (8,410,617) accordingly in order to reduce cost and provide size
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`efficiencies in a semiconductor integrated device structure. NOTE: Cols. 10-11, lines
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`54-67, 1-14 of Cole, Jr. et al. (5,338,975) cited to support the known position.
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`Claim Rejections - 35 USC § 102
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`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
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`form the basis for the rejections under this section made in this Office action:
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`A person shall be entitled to a patent unless —
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`(b) the invention was patented or described in a printed publication in this or a foreign country or
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`in public use or on sale in this country, more than one year prior to the date of application for
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`patent in the United States.
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`8.
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`Claims 1, 26, 30 are rejected under 35 U.S.C. 102(b) as being anticipated by
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`Park et al. (4,104,418).
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`MICRON ET AL. EXHIBIT 1018
`Page 7 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Page 7
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`Regarding to claims 1, 26, Park et al. disclose a thin flexible substrate (see at
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`least 4) comprising: a thin flexible layer (see at least 8); a dielectric layer (see at least
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`8’) formed on the semiconductor layer and having a stress of 5 x I03 dynes/cmz or less.
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`Regarding to claim 30, Park et al. disclose a thin flexible integrated circuit (see at
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`least Fig. 2) comprising: a thin flexible layer (see at least 8) comprising integrated circuit
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`device (see at least Fig. 2); a dielectric layer (see at least 8’) formed on the
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`semiconductor layer and having a stress of 5 x I08 dynes/cm‘? or less.
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`Claim Rejections - 35 USC § 103
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`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`(a) A patent may not be obtained though the invention is not identically disclosed or described as
`set forth in section 102 of this title, if the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have been obvious
`at the time the invention was made to a person having ordinary skill in the art to which said
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`subject matter pertains. Patentability shall not be negatived by the manner in which the invention
`was made.
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`9.
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`Claim 14 rejected under 35 U.S.C. 103(a) as being unpatentable over Park et al.
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`(4,104,418).
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`Regarding to claim 14, Park et al. disclose a thin flexible substrate (see at least
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`4) comprising: a thin flexible layer (see at least 8); a dielectric layer (see at least 8’)
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`formed on the semiconductor layer and having a stress of 5 x I08 dynes/cmz or less; a
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`circuitry for monitor the thicknesses of the deposited of glass layers.
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`MICRON ET AL. EXHIBIT 1018
`Page 8 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Park et al. disclose the claimed invention as noted above but not explicitly
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`disclose the circuitry formed within the thin semiconductor layer and the dielectric layer
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`defining an integrated circuit die having an area, wherein the thin semiconductor layer
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`extends throughout a portion of the area of the integrated circuit die. Providing a
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`circuitry formed within the thin semiconductor layer and the dielectric layer defining an
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`integrated circuit die having an area, wherein the thin semiconductor layer extends
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`throughout a portion of the area of the integrated circuit die would have been known and
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`available in the art.
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`It would have been obvious to one of the ordinary skill in the art at
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`the time if the invention of modify Park accordingly in order to reduce cost and size of
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`the semiconductor device. NOTE: Fig. 1-2, claims 4, 6, 10 of Corrie etai. (4,892,842)
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`cited to support the known position.
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`Conclusion
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`10.
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`The prior art made of record cited on Form PTO-892 is considered pertinent to
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`applicant’s disclosure.
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`Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to David Lam whose telephone number is (571)272-1782.
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`The examiner can normally be reached on 6:00 — 4:30.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
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`supervisor, Amir Zarabian can be reached on 571-272-1852. The fax phone numbers
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`for the organization where this application or proceeding is assigned is (571) 273-8300.
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`MICRON ET AL. EXHIBIT 1018
`Page 9 of 10
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`Application/Control Number: 13/734,874
`Art Unit: 2827
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`Page 9
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`Information regarding the status of an application may be obtained from the
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`Patent Application Information Retrieval (PAIR) system. Status information for published
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`applications may be obtained from either Private PAIR or Public PAIR. Status
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`information for unpublished applications is available through Private PAIR only. For
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`more information about the PAIR system, see http://pair-direct.uspto.gov. Should you
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`have questions on access to the Private PAIR system, contact the Electronic Business
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`Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO
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`Customer Service Representative or access to the automated information system, call
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`800-786-9199 (IN USA OR CANADA) or 571-272-1000.
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`/David Lam/
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`Primary Examiner, Art Unit 2827
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`May 24, 2013
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`MICRON ET AL. EXHIBIT 1018
`Page 10 of 10