Doc Code: TRACK1.REQ
`Document Description: TrackOne Request
`
`PTO/SB/424 (12-11)
`
`CERTIFICATION AND REQUEST FOR PRIORITIZED EXAMINATION
`UNDER 37 CFR 1.102(e) (Page 1 of 1)
`
`First Named
`Inventor:
`Title of
`Invention:
`
`LEEDY
`
`known):
`Three dimensional memory structure
`
`I Nonprovisional Application Number (if I
`
`APPLICANT HEREBY CERTIFIES THE FOLLOWING AND REQUESTS PRIORITIZED EXAMINATION FOR
`THE ABOVE-IDENTIFIED APPLICATION.
`
`1. The processing fee set forth in 37 CFR 1.17(i), the prioritized examination fee set forth in 37
`CFR 1.17(c), and if not already paid, the publication fee set forth in 37 CFR 1.18(d) have been
`filed with the request. The basic filing fee, search fee, examination fee, and any required
`excess claims and application size fees are filed with the request or have been already been
`paid.
`
`2. The application contains or is amended to contain no more than four independent claims and
`no more than thirty total claims, and no multiple dependent claims.
`
`3. The applicable box is checked below:
`
`I.
`
`r::-~1 Original Application (Track One) -Prioritized Examination under§ 1.1 02(e)(1)
`
`i.
`
`(a) The application is an original nonprovisional utility application filed under 35 U.S.C. 111 (a).
`This certification and request is being filed with the utility application via EFS-Web.
`---OR---
`( b) The application is an original nonprovisional plant application filed under 35 U.S.C. 111 (a).
`This certification and request is being filed with the plant application in paper.
`
`ii. An executed oath or declaration under 37 CFR 1.63 is filed with the application.
`
`II.
`
`[] Request for Continued Examination - Prioritized Examination under§ 1.1 02(e)(2)
`
`i. A request for continued examination has been filed with, or prior to, this form.
`ii.
`If the application is a utility application, this certification and request is being filed via EFS-Web.
`iii. The application is an original nonprovisional utility application filed under 35 U.S.C. 111 (a), or is
`a national stage entry under 35 U.S.C. 371.
`iv. This certification and request is being filed prior to the mailing of a first Office action responsive
`to the request for continued examination.
`v. No prior request for continued examination has been granted prioritized examination status
`under 37 CFR 1.1 02( e )(2).
`
`Siqnature /MichaeiJ Ure/
`~p~~~Typed) Michael J. Ure
`
`Date 2013-08-08
`33089
`
`Practitioner
`Registration Number
`
`Note: Signatures of all the inventors or assignees of record of the entire interest or their representative(s) are required in accordance with
`37CFR 1.33 and 11.18. Please see 37 CFR 1.4(d) for the form of the signature. If necessary, submit multiple forms for more than one
`siqnature, see below*.
`
`D *Total of
`
`forms are submitted.
`
`MICRON ET AL. EXHIBIT 1017
`Page 1 of 613
`
`

`

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`
`Page 2
`
`MICRON ET AL. EXHIBIT 1017
`Page 2 of 613
`
`

`

`l.
`
`A stacked circuit structure comprising:
`
`a plurality ofstacked, thin, substantially· flexible circuit !ayers or
`
`wiring layers each comprising a top sud~H.:e and a bottom surhKt~ and at
`
`least one ohvhich comprises a thinned, substantially flexible semiconduc-
`
`tor substratt~ of one pieu~; and
`
`an inter!ayer n.~gion disposed bt~twt~en a pair of vertically adjacent
`
`circuit layers or v-.riring layers and extending from a top surfa1.:e of one of
`
`the pair of vertically adjacent circuit layers or \viring !ay·ers to a bottom
`
`surt~Ke of anoth.~r one oftht.~ pair ot\ierlic~tl!y adjacent circuit Iayt~rs or
`
`\viring Iayt~rs, the interlayer region comprising an interlayer lbr pn.nriding
`
`mechanical attachment and ek~ctricalinterconnect1on bet\veen the pair of
`
`vertically <H.ij<K:ent circuit layers or \Viring layers;
`
`wherdn within the intedayer region the stacked 1..:ircuit structun~
`
`consists essentia Hy of metal or meta! and silicon-based dielectric.
`
`2.
`
`The apparatus of Claim I, wherein the interlayer cmnprises hotl1
`
`signa!-canying metal contacts and lH.m-signal-can)ling meta! bonding areas.
`
`3.
`
`The apparatus of Claim I, \Vherein the thinned, substantially f1exi-
`
`b!e semiconductor substrate comprises a plurality of etched through-holes each
`
`surrounding a vertical interconnect, each vertical interconnect comprising a con-
`
`dutctm and an insulator surrounding tl1e conductor and isolating the conductor
`
`tl-om the thinned, substantially flexible semiconductor substrate.
`
`4.
`
`The apparatus ofClai1n 3, wht.~rein the insulator comprises low-
`
`stress dielertric material having a stress of 5 x lOx dynes/cn12 tensile or less.
`
`5.
`
`The apparatus of Claim 1 , comprising a lO\\' -stress dielectric. I a y·er
`
`formed above the thinned, substantially tlexible semiconductor substrate,. \vherein
`
`the low-stress dielectric layer exhibits net tensile stress.
`
`MICRON ET AL. EXHIBIT 1017
`Page 3 of 613
`
`

`

`6.
`
`The apparatus of Claim 5, >vherein the !m-v-stress dide<.:tric layer
`
`has a StH.$S of 5 X I 08 dynes/cm2 tensile or less.
`
`7.
`
`~T'he appa.ratus t)f(~Iairn l, \\<here.h.l a l.lacks.tde i..1f d1e th.itlnt~d~ sttb-
`
`stantiaUy Hex1hle semkonductor substrate is polished. to reduce vulnerability to
`
`fracture as a result of Hexing and is devoid of integrated circuitry.
`
`Fl. <.:.
`
`The apparatl.ls of Claim 1, comprising a plurality of stacked, thin,
`
`substantiaHv f1exihle circuit la,,..ers. one of the stacked, thin, substantially tlexible
`.
`.
`
`.
`
`~
`
`'~ircuit layers comprising a memory array and another ofthe stacked, thin, substan-
`
`tially flexibk~ circuit la~lers comprising a mt~nKH)' controller for controlling the
`
`memory arra)r.
`
`9..
`
`Tht.~ apparatus of Claim 8, \·vherdn the one of the stacked, thin, sub-
`
`stantiaHy flexible circu.it layers <..:omprises a. phlmllt)l of independently-operable
`
`tnemory arrays, tht.~ n1emory controller being <.:onfigured to control the plurahty of
`
`in,kpendently-operable memory arrays independently· and in paralkl;
`
`further con1prising a plurality of indeptmtly-operable verti<.:al inter-
`
`conm .. ~(.:t buses, \)/herein data exchanged bt.~twt~en the memory controller
`
`~md the plurality of independently-operable nx~mory arrays is bussed inde-
`
`pt.~ndently and in parallel over tht~ plurality of independently-operable ver-
`
`tic a 1 inten .. :unnet:t buses.
`
`l 0.
`
`The apparatus of Claim 8, \vherein at least one of:
`
`the memory anay and memory controller together term a memory,
`
`the memory being reconfigurable by operation of the memory controller;
`
`the other of the stacked,, thin, substantially t1exib!e circuit layers
`
`comprises circuitry for perfbnning functional testing of the memory array.
`
`11.
`
`.A. stacked circuit structure comprising:
`
`MICRON ET AL. EXHIBIT 1017
`Page 4 of 613
`
`

`

`a plurality of stacked, thin, substantially fkxible circuit lay(~rs or
`
`\vidng layt~rs each comprising a top surface and a bottom surface and at
`
`least one of which {.:omprises a thinned, substantially Hexiblc semkonduc-
`
`tor substrate of one piece;
`
`'NlK~rein a pa:ir of vertkaHy adja{.:ent {.:ircuit layers or \Viring layers
`
`is joined togetht~r using metal-to-tnetal bonding as a sole or primary mech-
`
`anism of both attad1ment and ek~ctrkal interconnection.
`
`12.
`
`The apparatus of Claim 11, cornprising an interlayer joining the
`
`pair ofvertkal!y adjacent circuit layers or wiring layers, the interlay·er comprising
`
`both signa1-can)'ing metal contacts and non-signal-carrying metal bonding areas.
`
`13.
`
`The apparatus of Claim 11, wherein the thinned, substantially tlexi-
`
`b!e semiconductor substrate comprises a plurality of etched through-holes each
`
`surrounding a vertical interconnect, each vertical interconnect comprising a con-
`
`ductor and an insulator surrounding the conductor and isolating the conductor
`
`tl-om the thinned, substantially flexible semiconductor substrate.
`
`14.
`
`The apparatus of Claim 13, w·hcrein the insulator comprises lo\v-
`
`stJess dielectric material having u stress of 5 x l 08 dynesic.m2 tensile or k$S.
`
`15.
`
`The apparatus of Claim ll, comprising a !ow-stress dielectric layer
`
`fonned above the thinned, substantially flexible semiconductor substrate,. \vherein
`
`the low-stress dielectric layer exhibits net tensile stress.
`
`16.
`
`The apparatus of Claim t5, •vherein the lmv-stress dielectric layer
`8
`..,
`has a stress of 5 x I 0' dynes/em':. tensile or less.
`
`MICRON ET AL. EXHIBIT 1017
`Page 5 of 613
`
`

`

`17.
`
`The apparatus of Claim 11, ,.., .. ·herein a backside of the thinned, sub-
`
`stantially tlexible Stmliconductor substrate is polished to reduce vulnerabllity to
`
`fi:-a,~ture as a result of flexing and is '-kvoid of integrated circuitry
`
`18.
`
`The apparatus of ClaiJn ll, con1prising a p!uxality of stacked, thin,
`
`substantially flexible circuit layers, one of the stacked, thin, substantially tlex.ible
`
`circuit layers comprising a rnemory array and another of the stacked,. thin, snhstml(cid:173)
`
`tially tle.xible circuit la)ters comprising a memory controller for controlling the
`
`menwry array.
`
`19.
`
`The apparatus of Claim 18, wherein the one ofthe stacked, thin,
`
`substantially :t1exible circuit layers comprises a plurality of independently-operable
`
`memory arrays, the memOI)' controller being configured to control the plurality of
`
`independently-operable memory array·s independently and in parallel:,
`
`funher comprising a plurality of indepently-operable vertical inter(cid:173)
`
`connect buses, \Vherein data exchanged bet\\'een the memory controHer
`
`and tl1e plurality of independently-operable memory arrays is bussed inde(cid:173)
`
`pendently and in parallel over the plurality of independently-operable ver(cid:173)
`
`tical interconnet:t buses.
`
`20.
`
`The apparatus of Claim 8, >vherein at !east one of:
`
`the mcmor.Y an-ay and memory <::ontro!ler together f(xm a men:lQry,
`
`the mt~mory being recont1gurab!e by opt~ration of the memory controller;
`
`the other of the stacked, thin, substantially Hexib!e 1.:ircuit layers
`
`1.:ompdses circuitry for performing functional testing oftht~ memory array.
`
`21.
`
`A stacked circuit structure comprising:
`
`a plurality of stacked,. thin, sul.1stantially flexible circuit layers or
`
`\viring layers each comprising a top surface and a bottom suti"'ace and at
`
`least one of \vhich cmnprises a thinned, substantiaHy flexible semiconduc-
`
`MICRON ET AL. EXHIBIT 1017
`Page 6 of 613
`
`

`

`tor substnrte of one piect.~;
`
`\Vherein a pair of adjacent ones of th.~ stacked, thin, substantially
`
`Hexible dn.:uit layers or \Viring layers is bon(kd togetlwr at least predomi-
`
`nantly with metal, or at l!i.~ast pr~~dominantly ·with sihcon-based dielectric
`
`and metal;
`
`22.
`
`The apparatus of ClaiJn 21, comprising an interlayer joining the
`
`pair of adjacent ones of the stacked, thin, substantially Hexihle circuit layers or
`
`\·viring layers, the interlayer co1npris:ing signal-carrying tnetal contacts and non-
`
`signal-carrying xnetal bonding areas.
`
`23.
`
`The apparatus of Claim 21, "vherein the thinned, substantially f1exi-
`
`ble semiconductor substrate comprises a plurality of etched through-holes each
`
`surrounding a 1/eltical interconnect, each vertical interconnect comprising a con-
`
`ductor and an insulator surrounding the conductor and isolating the conductor
`
`from the thinned,. substantially flexible semiconductor substrate.
`
`24.
`
`Tht.~ apparatus of Claim 23, \!,therein the insulator comprises knv-
`
`stress dielectric tnaterial having a stress of 5 x I 08 dynes.i'cm2 tensile or less.
`
`25.
`
`The apparatus of Claim 21, comprising a lO\'i~'-stress dielectric layer
`
`formed above the thinned,. substantially flexible semiconductor substrate, \Vhere1n
`
`the lmv~stress dielectric layer exhibits net tensile stress.
`
`26.
`
`The apparatus of Claim 25, wherein the low-stress dielectric layer
`:;;;
`has a stress of 5 x lO' dynes,...'cm"' tensile or less.
`
`.
`
`')
`
`27.
`
`The apparatus of Claim 21, \Vherein a backside of the thinned, sub-
`
`s:tantially t1exible sexniconductor substrate is polished to reduce vulnerability to
`
`fractllH! as a result <.Jf Hexing and is devoid of integrated circuitry.
`
`MICRON ET AL. EXHIBIT 1017
`Page 7 of 613
`
`

`

`28.
`
`The apparatus of Claim 21, comprising a plurality of stacked, thin,
`
`substantially t1exible circuit layers, one of the stacked, thin, substantially flexible
`
`(:ircnit layt~rs compr1sing ~t memory array and another of the stacked, thin, substan~
`
`tially Hexible circuit layers comprising a tnemory' controller for controlling the
`
`memory anay.
`
`29.
`
`The apparatus ofCiaiJn 28, \.vberein the one of the stacked, thin,
`
`substantially tlexible circuit layers comprises a plura!.ity of independently-operable
`
`menwry arrays, the xnenw1y controller being configured to control the pluralit_y of
`
`independently-operable mernory arrays independently and in parallel;
`
`further comprising a plurality of indepently-operable vertical inter(cid:173)
`
`connect buses, \vherein data exchanged bet\veen the metJlOl)' controller
`
`and the plurality of independently-operable rnemory arraj,·s is bussed inde~
`
`pendently and in parallel over the pluralhy· of independently·-opemble ver(cid:173)
`
`tical interconnect buses.
`
`30,
`
`The apparatus of Claim 28, wherein at least one of:
`
`the memory array and memory controller together tonn a m.emory,
`
`the memory' being reconfigurable b).t operation of the memory controller;
`
`the other of the stacked, thin, substantially t1exible circuit layers
`
`comprises circuitry for perfom1ing functional testing of the memory array,
`
`MICRON ET AL. EXHIBIT 1017
`Page 8 of 613
`
`

`

`Electronic Patent Application Fee Transmittal
`
`Application Number:
`
`Filing Date:
`
`Title of Invention:
`
`Three dimensional memory structure
`
`First Named Inventor/Applicant Name:
`
`Glenn J Leedy
`
`Filer:
`
`Attorney Docket Number:
`
`Filed as Small Entity
`
`Michael James Ure
`
`130809NEW.US
`
`Track I Prioritized Examination -Non provisional Application under 35 USC 111 (a) Filing Fees
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`
`Quantity
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`Amount
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`Sub-Total in
`USD($)
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`Utility filing Fee (Electronic filing)
`
`Utility Search Fee
`
`Utility Examination Fee
`
`Request for Prioritized Examination
`
`4011
`
`2111
`
`2311
`
`2817
`
`1
`
`1
`
`1
`
`1
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`70
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`300
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`360
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`70
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`300
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`360
`
`2000
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`2000
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`Basic Filing:
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`Pages:
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`Claims:
`
`Claims in excess of 20
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`2202
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`10
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`40
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`400
`
`Miscellaneous-Filing:
`
`MICRON ET AL. EXHIBIT 1017
`Page 9 of 613
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`

`

`Description
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`Fee Code
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`Quantity
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`Amount
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`Sub-Total in
`USD($)
`
`Publ. Fee- Early, Voluntary, or Normal
`
`OTHER PUBLICATION PROCESSING FEE
`
`1504
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`1808
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`1
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`1
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`300
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`130
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`300
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`130
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`Petition:
`
`Patent-Appeals-and-Interference:
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`Post-Allowance-and-Post-Issuance:
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`Miscellaneous:
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`Total in USD ($)
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`3560
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`MICRON ET AL. EXHIBIT 1017
`Page 10 of 613
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`

`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`16547690
`
`13963164
`
`International Application Number:
`
`Confirmation Number:
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`8709
`
`Title of Invention:
`
`Three dimensional memory structure
`
`First Named Inventor/Applicant Name:
`
`Glenn J Leedy
`
`Customer Number:
`
`30232
`
`Filer:
`
`Michael James Ure
`
`Filer Authorized By:
`
`Attorney Docket Number:
`
`130809NEW.US
`
`Receipt Date:
`
`09-AUG-2013
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`MICRON ET AL. EXHIBIT 1017
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`MICRON ET AL. EXHIBIT 1017
`Page 12 of 613
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`If a new international application is being filed and the international application includes the necessary components for
`an international filing date (see PCT Article 11 and MPEP 181 0), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/R0/1 OS) will be issued in due course, subject to prescriptions concerning
`national security, and the date shown on this Acknowledgement Receipt will establish the international filing date of
`the application.
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`THREE DIMENSION STRUCTURE MEMORY
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to stacked integrated circuit memory.
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`2. State of the Art
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`Manufacturing methods for increasing the performance and decreasing the cost of electronic
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`circuits, nearly without exception, are methods that increase the integration of the circuit and
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`decrease its physical size per equivalent number of circuit devices such as transistors or
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`capacitors. These methods have produced as of 1996 microprocessors capable of over 100
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`million operations per second that cost less than $1,000 and 64 Mbit DRAM circuits that access
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`data in less than 50 ns and cost less than $50. The physical size of such circuits is less than 2
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`cm2. Such manufacturing methods support to a large degree the economic standard of living in
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`the major industrialized countries and will most certainly continue to have significant
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`consequences in the daily lives of people all over the world.
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`Circuit manufacturing methods take two primary forms: process integration and assembly
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`integration. Historically the line between these two manufacturing disciplines has been clear, but
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`recently with the rise in the use ofMCMs (Multi-Chip Modules) and flip-chip die attach, this
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`clear separation may soon disappear. (The predominate use of the term Integrated Circuit (IC)
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`herein is in reference to an Integrated Circuit in singulated die form as sawed from a circuit
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`substrate such as s semiconductor wafer versus, for example, an Integrated Circuit in packaged
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`form.) The majority ofiCs when in initial die form are presently individually packaged,
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`however, there is an increasing use ofMCMs. Die in an MCM are normally attached to a circuit
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`substrate in a planar fashion with conventional IC die I/0 interconnect bonding methods such as
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`wire bonding, DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).
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`Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM, Ferroelectric,
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`GMR (Giant MagnetoResistance), etc. have the common architectural or structural characteristic
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`of being monolithic with the control circuitry integrated on the same die with the memory array
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`circuitry. This established (standard or conventional) architecture or circuit layout structure
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`creates a design trade-off constraint between control circuitry and memory array circuitry for
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`large memory circuits. Reductions in the fabrication geometries of memory cell circuitry has
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`resulted in denser and denser memory ICs, however, these higher memory densities have
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`resulted in more sophisticated control circuitry at the expense of increased area of the IC.
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`Increased IC area means at least higher fabrication costs per IC (fewer ICs per wafer) and lower
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`IC yields (fewer working ICs per wafer), and in the worst case, an IC design that cannot be
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`manufactured due to its non-competitive cost or unreliable operation.
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`As memory density increases and the individual memory cell size decreases more control
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`circuitry is required. The control circuitry of a memory IC as a percentage ofiC area in some
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`cases such as DRAMs approaches or exceeds 40%. One portion of the control circuitry is the
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`sense amp which senses the state, potential or charge of a memory cell in the memory array
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`circuitry during a read operation. The sense amp circuitry is a significant portion of the control
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`circuitry and it is a constant challenge to the IC memory designer to improve sense amp
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`sensitivity in order to sense ever smaller memory cells while preventing the area used by the
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`sense amp from becoming too large.
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`2
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`If this design constraint or trade-offbetween control and memory circuits did not exist, the
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`control circuitry could be made to perform numerous additional functions, such as sensing
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`multiple storage states per memory cell, faster memory access through larger more sensitive
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`sense amps, caching, refresh, address translation, etc. But this trade-off is the physical and
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`economic reality for memory ICs as they are presently made by all manufacturers.
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`The capacity of DRAM circuits increases by a factor of four from one generation to the next; e.g.
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`1 bit, 4 bit, 16 Mbit and 64 Mbit DRAMs. This four times increase in circuit memory capacity
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`per generation has resulted in larger and larger DRAM circuit areas. Upon introduction of a new
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`DRAM generation the circuit yields are too low and, therefore, not cost effective for high
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`volume manufacture. It is normally several years between the date prototype samples of a new
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`DRAM generation are shown and the date such circuits are in volume production.
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`Assembling die in a stacked or three dimensional (3D) manner is disclosed in U.S. Pat. No.
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`5,354,695 of the present inventor, incorporated herein by reference. Furthermore, assembling die
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`in a 3D manner has been attempted with regard to memory. Texas Instruments of Dallas Tex.,
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`Irvine Sensors of Costa Mesa Calif. and Cubic Memory Corporation of Scotts Valley Calif. have
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`all attempted to produce stacked or 3D DRAM products. In all three cases, conventional DRAM
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`circuits in die form were stacked and the interconnect between each DRAM in the stack was
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`formed along the outside surface of the circuit stack. These products have been available for the
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`past several years and have proved to be too expensive for commercial applications, but have
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`found some use in space and military applications due to their small physical size or footprint.
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`3
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`The DRAM circuit type is referred to and often used as an example in this specification,
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`however, this invention is clearly not limited to the DRAM type of circuit. Undoubtedly memory
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`cell types such as EEPROMs (Electrically Erasable Programmable Read Only Memories), flash
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`EPROM, Ferroelectric, GMR Giant Magneto Resistance or combinations (intra or inter) of such
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`memory cells can also be used with the present Three Dimensional Structure (3DS) methods to
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`form 3DS memory devices.
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`The present invention furthers, among others, the following objectives:
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`1. Several-fold lower fabrication cost per megabyte of memory than circuits conventionally
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`made solely with monolithic circuit integration methods.
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`2. Several-fold higher performance than conventionally made memory circuits.
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`3. Many-fold higher memory density per IC than conventionally made memory circuits.
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`4. Greater designer control of circuit area size, and therefore, cost.
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`5. Circuit dynamic and static self-test of memory cells by an internal controller.
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`6. Dynamic error recovery and reconfiguration.
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`7. Multi-level storage per memory cell.
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`8. Virtual address translation, address windowing, various address functions such as indirect
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`addressing or content addressing, analog circuit functions and various graphics acceleration and
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`microprocessor functions.
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`SUMMARY OF THE INVENTION
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`The present 3DS memory technology is a stacked or 3D circuit assembly technology. Features
`
`include:
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`4
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`1. Physical separation of the memory circuits and the control logic circuit onto different layers;
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`2. The use of one control logic circuit for several memory circuits;
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`3. Thinning of the memory circuit to less than about 50 microns in thickness forming a
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`substantially flexible substrate with planar processed bond surfaces and bonding the circuit to the
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`circuit stack while still in wafer substrate form; and
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`4. The use of fine-grain high density inter layer vertical bus connections.
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`The 3DS memory manufacturing method enables several performance and physical size
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`efficiencies, and is implemented with established semiconductor processing techniques. Using
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`the DRAM circuit as an example, a 64 Mbit DRAM made with a 0.25 microns process could
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`have a die size of 84 mm2
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`, a memory area to die size ratio of 40% and a access time of about 50
`
`ns for 8 Mbytes of storage; a 3DS DRAM IC made with the same 0.25 microns process would
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`have a die size of 18.6 mm2
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`, use 17 DRAM array circuit layers, a memory area to die size ratio
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`of 94.4% and an expected access time ofless than 10 ns for 64 Mbytes of storage.
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`The 3DS DRAM IC manufacturing method represents a scalable, many-fold reduction in the cost
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`per megabyte versus that of conventional DRAM IC manufacturing methods. In other words,
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`the 3DS memory manufacturing method represents, at the infrastructure level, a fundamental
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`cost savings that is independent of the process fabrication technology used.
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`BRIEF DESCRIPTION OF THE DRAWING
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`The present invention may be further understood from the following description in conjunction
`
`with the appended drawing. In the drawing:
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`5
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`FIG. la is a pictorial view of a 3DS DRAM IC manufactured with Method A or Method Band
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`demonstrating the same physical appearance ofl/0 bond pads as a conventional IC die;
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`FIG. 1 b is a cross-sectional view of a 3DS memory IC showing the metal bonding interconnect
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`between several thinned circuit layers;
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`FIG. lc is a pictorial view of a 3DS DRAM IC stack bonded and interconnected face-down onto
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`a larger conventional IC or another 3DS IC;
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`FIG. 2a is a diagram showing the physical layout of a 3DS DRAM array circuit block with one
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`data-line set of bus lines, i.e. one port;
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`FIG. 2b is a diagram showing the physical layout of a 3DS DRAM array circuit block with two
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`sets of data-line bus lines, i.e. two ports;
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`FIG. 2c is a diagram showing the physical layout of a portion of an exemplary memory
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`controller circuit;
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`FIG. 3 is a diagram showing the physical layout of a 3DS DRAM array circuit showing
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`partitions for sixty-four (64) 3DS DRAM array blocks;
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`FIG. 4 is a cross-sectional view of a generic 3DS vertical interconnection or feed-through in a
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`thinned substrate;
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`6
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`FIG. 5 is a diagram showing the layout of a 3DS memory multiplexer for down-selecting gate(cid:173)
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`line read or write selection.
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`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
`
`Referr