|||||||||||||||l||||||||l|||l|||Illlllllllllllllllll||||Illllllllllllllllll
`US005502333A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,502,333
`
`Bertin et al.
`
`[45] Date of Patent:
`
`Mar. 26, 1996
`
`[54] SEMICONDUCTOR STACK STRUCTURES
`AND FABRICATION/SPARING METHODS
`UTILIZING PROGRAMMABLE SPARE
`CIRCUIT
`
`4,918,335
`5,179,540
`5,266,833
`5,315,552
`5,386,386
`
`.............................. 307/303.1
`4/1990 Cha.ll,Jr.
`1/1993 Stockton .
`365/225.7
`11/1993 Capps ... ...
`.. .. ... 257/690
`5/1994 Yoneda
`365/200
`1/1995 Ogihara ................................... 365/200
`
`Inventors: Claude L. Bertin, South Burlington;
`Erik L. Hedberg, Essex Junction;
`Y
`W
`_ H
`H’ 5
`th B 1-
`of-ilytne J
`ur mgton an
`owe
`on
`'
`
`OT}-JER PUBLICATIONS
`_
`_
`_
`“
`_
`_
`_
`Fitzpatrick et al., Redundancy Using Plat1num—S1l1con
`Fuses,” IBM Technical Disclosure Bulletin, vol. 29, No, 10,
`pp. 4612-4615, Mar. 1987.
`
`Assignee:
`
`Internatienal Business Machines
`C01‘P01'atI0Il, Armonk, NY.
`
`Appl. No.: 220,086
`Filed:
`Mar’ 30’ 1994
`Int. Cl.“ ..................................................... H01L 23/02
`U.S. c1. .......................... 257/685; 257/686; 257/690;
`257/723; 257/773
`Field of Search ..................................... 257/690, 691,
`257/694, 773, 777, 723, 685, 686; 365/200
`
`References cited
`
`4 312 046
`4:534:55”
`4,597,095
`4,731,760
`4,770,640
`
`U-S- PATENT DOCUMENTS
`1,1982
`4/1936
`9/1937
`3/1988
`9/1988
`
`-
`
`O
`
`'
`
`'
`
`primary Emmine,-_wi11iam Mimel
`Assistant Examiner——Roy Potter
`Attomey, Agent, or Firm—Heslin & Rothenberg
`[57]
`ABSTRACT
`Electronic semiconductor structures utilize an electrically
`programmable spare circuit incorporated with a multichip
`package. The programmable sparing capability in the mul-
`tichip package is accomplished either with or without the
`§n°1_“§i°“ °f_a SW6 °hiP(S)- With *1 SPKFC m°m°TY Cifcllitv
`Individual failed memory cells in the semiconductor chips of
`a stack can be functionally replaced by memory cells of the
`spare memory circuit subsequent to encapsulation and burn-
`in testing. With use of a spare chip, non-volatile sparing can
`occur subsequent to encapsulation and burn-in testing with-
`out physical rewiring of a wire bond connection. Specific
`details of alternate electronic semiconductor structures, and
`fabrication and sparing methods therefore, are set forth.
`
`25 Claims, 7 Drawing Sheets
`
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`33
`
`MICRON ET AL. EXHIBIT 1010
`Page 1 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 1 of 7
`
`5,502,333
`
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`MICRON ET AL. EXHIBIT 1010
`Page 2 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1995
`
`Sheet 2 of 7
`
`5,502,333
`
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`MICRON ET AL. EXHIBIT 1010
`Page 3 of 17
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`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 3 of 7
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`5,502,333
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`MICRON ET AL. EXHIBIT 1010
`Page 4 of 17
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`

`
`U.S. Patent
`
`Mar. 26, 1995
`
`Sheet 4 of7
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`5,502,333
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`MICRON ET AL. EXHIBIT 1010
`Page 5 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 5 of 7
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`5,502,333
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`MICRON ET AL. EXHIBIT 1010
`Page 6 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 6 of 7
`
`5,502,333
`
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`MICRON ET AL. EXHIBIT 1010
`Page 7 of 17
`
`

`
`U.S. Patent
`
`Mar. 26, 1996
`
`Sheet 7 of 7
`
`5,502,333
`
`304
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`MICRON ET AL. EXHIBIT 1010
`Page 8 of 17
`
`

`
`5,502,333
`
`1
`SENIICONDUCTOR STACK STRUCTURES
`AND FABRICATION/SPARING METHODS
`UTILIZING PROGRAMMABLE SPARE
`CIRCUIT
`
`TECHNICAL FIELD
`
`The present invention relates in general to high density
`electronic circuit packaging, and more particularly, to tech-
`niques for providing programmable sparing capability to a
`multichip package, either with or without the inclusion of a
`spare chip(s) in the multichip package.
`
`BACKGROUND ART
`
`The market for high density electronic circuit packages of
`multiple semiconductor chips continues to increase. Two
`common types of semiconductor chip stacks are the verti-
`cally-extending (or “pancake”) stack and the horizontally-
`extending (or “breadloai”) stack.
`U.S. Pat. Nos. 4,525,921 and 4,646,128 by Carson et al.
`disclose structure and fabrication techniques for producing
`one type of high density, multichip electronic package.
`These documents describe a semiconductor chip stack con-
`sisting of multiple integrated circuit chips adhesively
`secured together. Ametallized pattern is provided on at least
`one side surface of the stack for electrical connection of the
`stack to external circuitry. This metal pattern typically
`includes both individual contacts and bussed contacts. The
`stack is positioned on an upper surface of a substrate so that
`electrical contact can be made between the stack metalliza-
`tion pattern and a substrate surface metallization pattern.
`Various alternate stack structures and electrical intercon-
`nection possibilities have also been described. For example,
`reference U.S. patent application Ser. No. 08/000,826
`entitled, “Multichip Integrated Circuit Packages and Sys-
`tems," U.S. patent application Ser. No. 08/120,876, entitled
`“Integrated Multichip Memory Module, Structure and Fab-
`rication,” and U.S. patent application Ser. No. 08/120,993,
`entitled, “Integrated Memory Cube, Structure and Fabrica-
`tion,” which are all commonly assigned to the same assignee
`as the present invention, and which are all hereby incorpo-
`rated herein by reference.
`At least one redundant chip(s) is often provided in a
`semiconductor chip stack so that if one or more of the
`primary chips in the stack should fail following stack
`fabrication and/or stressing (i.e., burn-in), the redundant
`chip(s) may be “invoked” to provide the electronic circuit
`package with the desired performance level. This activity is
`referred to in the art as “sparing.” Invoking of a redundant
`or spare semiconductor chip is typically physically accom-
`plished at the package level of assembly, which normally
`entails wirebonding the chip to a lead frame and then
`encapsulating the entire assembly in a polymer material.
`Thus, burn—in and invoking of the redundant semiconductor
`chip (“sparing”) in a multichip package must be performed
`prior to encapsulation and final testing of the semiconductor
`chip stack. Unfortunately, chip failure can occur during final
`stack packaging,
`in which case the resultant electronic
`circuit package must be discarded.
`Conventional stack “breadloat” sparing technology is
`based on provision of a programmable via in combination
`with a thin film metallization layer on a side-surface of an
`unpackaged semiconductor chip stack. Such technology
`enables access to the spare chip(s) in the stack while still
`maintaining a fixed pattern and fixed function solder bump
`array. Alternatively, additional stack side-face wiring chan-
`
`2
`nels may be employed to independently access a spare
`chip(s) in the semiconductor chip stack.
`An important application of today’s chip stacking tech-
`nology is in the fabrication of computer memory systems.
`Traditionally, computer memory systems are assembled
`from many types of memory chips, such as DRAMs,
`SRAMS, EPROMS and EEPROMS. The number of storage
`devices per memory chip technology generation varies but
`increases over time with more devices per chip being
`delivered with each succeeding generation, thereby provid-
`ing greater memory capacity. When a next generation
`memory chip becomes available,
`the number of chips
`needed to make a given memory system is correspondingly
`reduced. With fewer memory chips needed, the resultant
`memory system becomes physically smaller.
`The next generation DRAM memory chips have tradi-
`tionally increased by 4x the number of bits compared with
`current generation technology. For example, assume that the
`current generation of memory chips comprises 16 megabit
`(Mb) chips, then by industry standards the next generation
`comprises 64 Mb memory chips. This 4>< advancement from
`one generation of memory chips to the next generation is
`typically accomplished with corresponding advancement in
`semiconductor tool and process technologies, for example,
`sufficient to attain a 2X reduction in surface geometries. Due
`to this interrelationship, a significant interval of time can
`pass between generations of memory chips. Therefore, a
`genuine improvement in memory system design and fabri-
`cation would be attained if current generation memory chips
`could be assembled to have the same functions and physical
`dimensions of an anticipated, next generation memory chip.
`The multichip memory packages and fabrication techniques
`presented in the above-incorporated patent applications pro-
`vide such an improvement.
`Experience has shown that burn—in stressing of semicon-
`ductor chips in a multichip package predominately results in
`only a few single bit (i.e., “memory cell”) fails per failing
`semiconductor chip. For example,
`in a typical
`failed
`memory chip, there might be 10-15 memory cells in the chip
`which fail
`testing following burn-in stressing. Currently,
`there is no cost-effective technology to spare only these
`failed bits, particularly after the chip has been encapsulated;
`that is, at least not without providing a redundant semicon-
`ductor chip. Therefore, an entire semiconductor chip stack
`might have to be discarded because of only a few failed
`memory cells. Since single memory cell failures are the
`predominant mode of failure of a semiconductor chip's
`memory, an alternative stack sparing approach based on
`replacement of only the failed memory cell(s), rather than
`replacement of the entire semiconductor chip, would clearly
`have commercial advantages.
`As another problem, most semiconductor random access
`memories (RAMs) utilize power-on latches which assume a
`state based on non-volatile data. Fuses, for instance, can be
`opened to influence latch state during power—up. Such circuit
`technologies are commonly used for memory array redun-
`dancy allocation. Unfortunately, in a high radiation flux
`environment, an ion impact episode may cause these redun-
`dancy latches to flip;
`thereby activating or deactivating
`random redundancy. Obviously, this could have catosph-
`ropic consequences to a memory dependent machine.
`In general, various novel techniques for providing pro-
`grammable sparing capability to a multichip package, either
`with or without the inclusion of a spare chip(s) in the
`multichip package, are presented herein. These techniques
`address each of the above-noted drawbacks of the existing
`multichip stack fabrication art.
`
`MICRON ET AL. EXHIBIT 1010
`Page 9 of 17
`
`

`
`5,502,333
`
`3
`DISCLOSURE or lNVENTION
`
`Briefly described, the present invention comprises in one
`aspect an electronic semiconductor structure wherein a
`plurality of semiconductor chips are electrically coupled
`together to form a system. At least one semiconductor chip
`in the system has a memory with m memory cells, wherein
`m is an integer. A spare memory circuit having 11 memory
`cells is also provided, wherein n is an integer and ném. The
`spare memory circuit is electrically connected to the plural-
`ity of semiconductor chips and is programmable such that
`single memory cells of the 11 memory cells of the spare
`memory circuit can functionally replace a single failed
`memory cell of the m memory cells of the at least one
`semiconductor chip in the system. If desired, the spare
`memory circuit could be provided physically separate from
`the plurality of semiconductor chips, or on a semiconductor
`chip comprising one of the plurality of semiconductor chips,
`or on each semiconductor chip of the plurality of semicon-
`ductor chips.
`In another aspect, an electronic semiconductor structure is
`provided wherein a plurality of semiconductor chips are
`electrically coupled together to form a system. A controller
`circuit is electrically coupled to the system and contains
`non-volatile means for sparing the system by permanently
`selecting after encapsulation at least one semiconductor chip
`of the plurality of semiconductor chips to be active within
`the system.
`In yet another aspect, a packaged electronic semiconduc-
`tor structure is described wherein, again, a plurality of
`semiconductor chips are electrically coupled together in a
`packaged system. A spare circuit is mechanically and elec-
`trically coupled to the plurality of semiconductor chips so as
`to comprise part of the packaged system and electrical
`means are provided for activating the spare circuit to func-
`tion in combination with the plurality of semiconductor
`chips in the packaged system.
`In a further aspect, the invention comprises a method for
`sparing a packaged semiconductor device having multiple
`semiconductor chips each with a memory of In memory
`cells, wherein m is an integer. The device also includes a
`spare memory circuit having 11 memory cells, wherein n is
`an integer and né m. The multiple semiconductor chips and
`the spare memory circuit are electrically coupled together.
`The sparing method includes the steps of: for each semi-
`conductor chip of the multiple semiconductor chips, testing
`operability of and monitoring for failure at a memory cell of
`the In memory cells of the memory; and after detecting a
`failed memory cell, programming a memory cell of the n
`memory cells of the spare memory circuit to functionally
`replace the failed memory cell.
`In still another aspect, the invention comprises a method
`for fabricating a multichip semiconductor package includ-
`ing: providing a plurality of semiconductor chips, each
`having two substantially parallel planar main surfaces;
`mechanically and electrically coupling together the plurality
`of semiconductor chips such that at least one planar main
`surface of each semiconductor chip is coupled to a planar
`main surface of an adjacent semiconductor chip; and pro-
`viding and electrically coupling a controller circuit to the
`multichip semiconductor stack, the controller circuit includ-
`ing programmable, non-volatile means for sparing the mul-
`tichip semiconductor stack.
`To summarize, various techniques are discussed for spar-
`ing a stack subsequent to scaling a stack within a micro-
`electronic package. Personalization of the package is thus
`attainable at final testing, along with permanent sparing
`
`4
`thereof, for example, by using an electrical fuse array,
`non-volatile memory or an electrical programmable logic
`array. The programmable methodologies presented can also
`be used to invoke various logic functions such as I/O
`reconfiguration, error correction code (ECC), self-timed
`refresh, address reconfiguration, or any desired application
`specific function. When the logic function and selecting
`function are combined, the resultant circuitry can be incor-
`porated almost anywhere within the stack.
`In addition, techniques are presented for sparing a mul-
`tichip package by replacing only failed memory bits, i.e.,
`without the use of a redundant semiconductor chip in the
`stack. Thus, greater density is achieved, and fixed segmen-
`tation points in a large stack fabrication process are possible
`i and cost—efiective, while still maintaining high stack yield.
`Significant
`stack fabrication/test
`cost
`reductions
`are
`achieved by eliminating the need for functional, but not
`accessed, spare chips. Sparing of memory chip fails caused
`by ion bombardment after packaging is also possible.
`Further, the invention enables the “upgrading” of non-
`conforming chips when incorporated into a multichip stack.
`Specifically, the invention can result in the replacement of
`failed memory cells from a DRAM stack with functional
`memory cells contained in a SRAM cache. Thus, the inven-
`tion is not necessarily limited to simply replacing failed
`memory cells that occur during stressing. Rather, cell
`replacement can also occur for memory cells that fail due to
`other reasons, even to the extent of taking semiconductor
`chips that as single chips would be considered non-conform-
`ing, incorporating them into the stack, and replacing the
`failed memory cells in those chips with the SRAM macro
`cells. Further, the cell replacement technique presented is
`not restricted to DRAM chips. The invention can be applied
`to any number of technologies, including SRAM, flash, etc.,
`for which sparing is needed for cost effective fabrication of
`a multichip package.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`These and other objects, advantages and features of the
`present invention will be more readily understood from the
`following detailed description of certain preferred embodi-
`ments of the invention, when considered in conjunction with
`the accompanying drawings in which:
`FIG. 1 is a partially exposed top view of a multichip
`package in accordance with one embodiment of the inven-
`tion wherein a logic circuit and a non-volatile sparing
`controller are electrically coupled;
`FIG. 1a is an exposed side elevational view of the
`multichip package of FIG. 1;
`FIG. 2 is an exposed end elevational view of the multichip
`package of FIG. 1;
`FIG. 3 is a schematic of one embodiment of a non-volatile
`spare circuit controller for the multichip package of FIG. 1;
`FIG. 4 is a partially exposed top view of another embodi-
`ment of a multichip package in accordance with the present
`invention wherein alogic/SRAM chip is aflixed to an endcap
`chip of a semiconductor chip stack;
`FIG. 4a is an exposed side elevational view of the
`multichip package of FIG. 4;
`FIG. 5 is an exposed end elevational view of the multichip
`package of FIG. 4;
`FIG. 6 is a block diagram representation of one embodi-
`ment of a logic/SRAM circuit
`in accordance with the
`invention for the multichip package of FIG. 4;
`
`MICRON ET AL. EXHIBIT 1010
`Page 10 of 17
`
`

`
`5,502,333
`
`5
`FIG. 7 is a block diagram representation of one embodi-
`ment of a sparing circuit in accordance with the invention for
`the logic/SRAM circuit of FIG. 6;
`FIG. 8 is a block diagram representation of one embodi-
`ment of a SRAM decoder and SRAM circuit for the sparing
`circuit of FIG. 7;
`FIG. 9 is an elevational view of one stacking/packaging
`arrangement
`in accordance with the invention showing
`connection of a logic/SRAM chip to a multichip stack;
`FIG. 10 is an elevational view of another stacking]
`packaging arrangement in accordance with the invention
`showing connection of a logic/SRAM circuit embedded
`within an endcap chip of a multichip stack; and
`FIG. 11 is an elevational view of still another stackingl
`packaging arrangement in accordance with the invention
`showing connection of a logic/SRAM chip to a side-surface
`of a multichip stack.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`Broadly stated, the present invention comprises various
`electronic semiconductor structures and fabrication/sparing
`methods for improving multichip package yield, principally
`subsequent to encapsulation and bum-in of the package.
`More particularly, various multichip stack structures and
`packaging techniques are described for enhancing package
`yield by providing the capability to spare memory ranging in
`size from one or more memory cells to an entire chip or
`chips.
`Reference is now made to the drawings, which are not
`drawn to scale for ease of understanding, wherein the same
`reference numbers used throughout ditferent figires desig-
`nate the same or similar components.
`FIGS. 1, la & 2 depict one embodiment of a multichip
`package, generally denoted 10,
`in accordance with the
`invention. Package 10 includes by way of example five
`identical-type integrated circuit chips 12, only four of which
`need to be active with the fifth chip comprising a redundant
`semiconductor chip. In one embodiment, each chip 12 may.
`comprise a memory chip such as a 4 Mb dynamic random
`access memory (DRAM) chip. Semiconductor chips 12 are
`coupled together in a vertically-extending stack referred to
`in the art as a “pancake” configuration. An endcap 14, for
`example, fabricated of a ceramic or organic material, is
`disposed above an uppermost semiconductor chip 12 in the
`vertically-oriented stack. The multichip package depicted in
`FIGS. 1, la & 2 comprises an SOJ package wherein encap-
`sulant 36 surrounds the multichip stack and pins/lead frame
`38 provide electrical connection to the semiconductor chips
`of the stack. FIGS. 9-11 depict various alternate mechanical
`arrangements for interconnecting semiconductor chips to
`form a stack.
`
`Disposed above endcap 14 is a logic circuit chip 16 and
`a non-volatile programming means, labelled “sparing con-
`trol” 24, along with a multitude of pads 20 which electrically
`connect through endcap 14 by metallized via holes, such as
`metallized via 32, and appropriate transfer metallization 26
`to side surface bussings 34. Bussings 34 electrically connect
`to the multiple chips 12 in the package. Pads 18 and 30 are
`also disposed above circuit chip 16 and sparing control chip
`24, respectively. Traditional wire bond 22 can be used to
`interconnect chips 16 and 24 and to connect the chips to
`selected metallized via holes (32) through endcap 14, for
`coupling to side surface metallization 34 via an appropriate
`
`6
`transfer metallization 26 above the uppermost semiconduc-
`tor chip 12 in the stack.
`Wiring 26 extends outwardly to the stack’s side surface '
`bussings 34 and electrically connects thereto via, e.g., con-
`ventional T-connections (FIG. 2). Note that transfer metal-
`lization 26 may be employed to electrically contact to an
`active surface of an adjacent semiconductor chip or to
`electrically connect a metallized via 32 to side surface
`metallization 34 of the multichip package. One preferred
`approach to electrically connecting a semiconductor chip
`disposed on an end surface of a multichip stack is described
`in the above-incorporated application entitled “Multichip
`Integrated Circuit Packages and Systems,” Ser. No. 08/000,
`826.
`
`Various implementations of the non-volatile program-
`mable means, i.e., sparing control 24, are possible. Again, in
`this embodiment the goal of programmable means 24 is to
`provide a mechanism for selecting those semiconductor
`chips 12 to be active in the stack. More particularly, package
`10 may be configured such that by default the four lower-
`most semiconductor chips in the stack are active, i.e., unless
`testing subsequent to encapsulation and burn-in establishes
`that one of these semiconductor chips is defective. In such
`a case, programming means 24 is activated to deselect the
`failed semiconductor chip and substitute therefore the upper-
`most semiconductor chip 12 in the stack. Obviously, this
`assumes that there is only one failed semiconductor chip in
`the multichip package. If desired, multiple redundant semi-
`conductor chips could be incorporated into the stack prior to
`encapsulation. The decision whether to incorporate one or
`more redundant semiconductor chips into the stack can be
`based upon empirical yield data for the particular type
`semiconductor chips at issue. Alternatively, a “spare chip”
`not redundant of the particular type semiconductor chips at
`issue could be incorporated into the stack as described
`below. Programming of non-volatile program means 24 is
`electrically controlled after encapsulation through a pro-
`grammable control bus 28.
`Sparing of a multichip package after encapsulation and
`final testing can be accomplished using a number of different
`non-volatile programming means. For example, a first
`option might be to employ an electrical fuse array, either on
`a second silicon chip (e.g., chip 24) or by invoking a fuse
`array integrated with the logic circuit chip 16. Such fuses
`can be open circuited via programmable control lines con-
`nected to a spare package pin or multiplexed with functional
`package pins. For instance, package address pins can be
`used to “point” to specific fuses. Then by driving current
`through the p'1n(s), the fuse in question can be open circuited.
`With such a capability, the spare control 24 can be “perma-
`nently” (non-volatilely) directed to access only semiconduc-
`tor chips of the stack which have tested functional subse-
`quent
`to encapsulation and bum—in. Alternatively, non-
`volatile memory may be accessed via a spare package pin(s)
`to electrically program a data output configuration similar to
`that of a fuse network.
`
`The control circuit of FIG. 3, which presents still another
`non-volatile programming option, employs electrically pro-
`grammable logic arrays (EPLAs) to program a sparing
`algorithm at final testing of the multichip package. This
`circuit includes complementary metal oxide semiconductor
`(CMOS) circuits with P-charmel
`field-eifect
`transistors
`(PFETs) indicated in the drawing by a rectangle with a
`diagonal line formed therein and a control element or gate
`electrode arranged adjacent thereto and with N-charmel
`field-efiect
`transistors (NFETs) indicated by a rectangle
`without a diagonal line and with a control element or gate
`electrode arranged adjacent thereto.
`
`MICRON ET AL. EXHIBIT 1010
`Page 11 of 17
`
`

`
`5,502,333
`
`7
`Data is scanned into a data register 50 at a. rate dictated by
`a common clock 51. Coupled to data register 50 are a
`plurality of non-volatile logic circuits 54, only one of which
`is shown. Each bit location in data register 50, e.g., location
`53, has a corresponding logic circuit 54 associated there-
`with. A zero ‘0’ at the corresponding bit 53 of data register
`50 forward biases a PFET 58, which permits a floating gate
`NFET 56 to receive an elevated voltage at its gate ‘G’ and
`drain ‘D’. As a result, floating gate structure 56 absorbs hot
`electrons which increases the threshold voltage of the
`device, driving it to a permanently “off” state. A PFET 62
`configured as a bleeder is connected to the drain ‘D’ of
`NFET 56 to ensure that the drain 5D’ never floats. A buffer
`64 is employed to amplify the floating gate network to
`CMOS levels for input to an appropriate bit of a compare
`register 52, which has ‘n’ bits that correspond to ‘11’ bits of
`data register 50. Programming of a ‘0’ in the data register
`thus produces a ‘1’ in the compare register. After program-
`ming, compare register 52 holds the logic vector for the
`sparing algorithm. Scan out can be used to verify program-
`ming accuracy.
`The same non-volatile programming methodologies for
`substituting chips can be used to invoke various logic
`functions, collectively referred to herein as “feature cir-
`cuits.” Such logic functions, which can reside on logic chip
`16 (FIG. 1), might include logic for I/O reconfiguration,
`ECC, self-timed refresh, address reconfiguration, or almost
`any application specific function desired. Thus, multichip
`package personalization may be completed on a customer-
`specific basis. The physical wiring of FIGS. 1, 1a & 2
`supports test, burn-in and application, while FIG. 3 depicts
`an embodiment for programming final logic functions and
`selecting good chips without rewiring any electrical con-
`nection. When the logic function and the non-volatile select-
`ing function are combined, the total system can be placed
`anywhere within the multichip stack, for example, reference
`FIGS. 10 and 11 (discussed below).
`As noted initially, for certain applications it may be
`desirable to avoid the inclusion of one or more redundant
`semiconductor cl1ip(s) in a multichip package, yet to still
`provide a sparing capability, particularly after encapsulation
`and bum-in of the package. This is because inclusion of a
`redundant semiconductor chip in a multichip stack neces-
`sarily results in a greater stack height (or length), more
`complex package side-surface wiring, additional test time
`and, ultimately, additional product cost.
`The majority of today’s multichip packages comprise
`memory modules wherein multiple memory chips are elec-
`trically and mechanically integrated within the package.
`Failure analysis has shown that testing subsequent to burn-in
`(i.e., after encapsulation) may result in failure of a memory
`chip at, for example, 5-l5 memory cells of the memory
`array. Thus, another aspect of the present invention com-
`prises the sparing of a multichip package after encapsula-
`tion, without the use of a redundant semiconductor chip
`within the stack, by substitution of individual functional
`memory cells for identified failed memory cells in one or
`more semiconductor chips of the multichip package.
`FIGS. 4, 4a & 5 depict one embodiment of a multichip
`stack, generally denoted 110, in accordance with this aspect
`of the invention. In this stack, four semiconductor chips 112
`are mechanically connected such that at least one planar
`main surface of each memory chip is coupled to a planar
`main surface of an adjacent memory chip, resulting in the
`chips residing one above the other as shown in FIGS. 4a &
`5. By way of example, package 110 could comprise four
`DRAM chips. However, the concepts described herein are
`
`8
`equally applicable to other semiconductor chips, such as
`logic chips, wherein memory is included on at least one of
`the chips and a failed memory cell location is identified
`during post-bum-in testing.
`In the embodiment shown, an endcap 114, positioned
`above the four semiconductor chips 112, has a logic/SRAM
`chip 116 aflixed thereto. Analogous to endcap 14 of FIG. 1,
`endcap 114 facilitates electrical connection of chip 116 to
`semiconductor chips 112 via metallized vias 132 and trans-
`fer metallization 126. Chip 116 contains contact pads 118 on
`an upper surface thereof which can be wire bonded 122 to
`surrounding pads 120 disposed above endcap 114, such as
`shown. Pads 120 might be electrically connected to side
`surface metallizations 134 through connection to appropri-
`ate metallized vias 132 and transfer metallization 126. In this
`embodiment, the multichip package is encapsulated 136 to
`form an SOJ package having connection pins 138 extending
`therefrom.
`
`Central to this aspect of the invention is the provision of
`programmable, spare memory cells (e.g., in the form of a
`SRAM macro) that are electrically connected to the multi-
`chip stack to provide substitute memory cells for failed
`memory cells in the stack. In the embodiment shown, the
`SRAM macro is integrated with a logic macro, which
`coordinates communication with the package via appropri-
`ate addressing and I/O buffering logic. One embodiment of
`such a logic chip is described in the above-incorporated U.S.
`patent application entitled “Integrated Multichip Memory
`Module, Structure and Fabrication,” Ser. No. 08/120,876
`However, it is important to note that the spare memory cells
`could be disposed anywhere within the multichip stack,
`including on each semiconductor chip of the stack or on a
`dedicated semiconductor chip integrated with the multichip
`stack.
`<
`»
`
`By way of overview, the SRAM macro provides access to
`spare memory cells at retrieval rates equal to or greater than
`access rates to the semiconductor chips of the stack, e.g.,
`dynamic random access memory (DRAM) chips. This is
`accomplished by storing the address of a failed memory cell
`location in the logic/SRAM chip by some means of non-
`volatile data recordation, such as, but not limited to, an
`electrically programmable fuse bank. The fuse bank