Umted States Patent
`
`[19]
`
`US005354695A
`[11] Patent Number:
`
`5,354,695
`
` _
`
`Leedy
`
`[45] Date of Patent:
`
`Oct. 11, 1994
`
`[54] MEMBRANE DIELECTRIC ISOLATION IC
`FABRICATION
`Inventor: Glenn J. Ieedy, 1061 13. Mountain
`Dr., Montecito, Calif. 93108
`
`[76]
`
`Assistant Examiner-—Trung Dang
`Attorney. Agent, or Firm—Blakely, Sokoloff, Taylor &
`mm”
`[57]
`
`ABSTRACI‘
`
`General purpose methods for the fabrication of inte-
`at
`'
`'
`xible
`v
`é‘1§n'”1§CZ‘§Z“é§ §’1‘2‘fZ§§§c ma?f1'£‘s’,'§3§§ §‘;';'?1?§o?.fd1§§’.
`ide or silicon nitride, and semiconductor layers. Semi-
`conductor devices are formed in a semiconductor layer
`of the membrane. The semiconductor membrane layer
`is initially formed from a substrate of standard thick-
`ness, and all but a thin surface layer of the substrate is
`then etched or polished away. In another version, the
`flexible membrane is used as support and electrical in-
`terconnect
`for conventional
`integrated circuit die
`bonded thereto, with the interconnect formed in multi-
`P13 ‘fillers in ‘he m¢mb’“°- M“1‘iP1° die Ca“ be 00”‘
`nected to one such membrane, which is then packaged
`as a multi-chip module. Other applications are based on
`(circuit) membrane processing for bipolar and MOS-
`PET transistor fabrication, low impedance conductor
`interconnecting fabrication, flat panel displays, maskless
`-
`-
`-
`I
`-
`-
`(duect wm°)hth°g'aphy" and 3D C fab"°at'°"'
`
`[21] App1_ No_; 865,412
`.
`I221 FM Aw 8-1992
`[51]
`Int. CL5 ............................................. H01L 21/00
`[52] US. Cl. ........................................ 437/7; 437/974;
`437/62; 437/238; 437/241; 437/907; 148/DIG.
`135
`[58] Field of Search ................... 437/974, 7, 8, 62, 66,
`437/238, 241; 156/662; 148/DIG. 135
`
`References Cited
`U.S- PATENT DOCUMENTS
`4,o7o,23o
`1/1978 Stein ...................................... 437/66
`4,131,985
`1/1979 Greenwoodetal.
`437/5;
`437/s
`4,618,397 10/1986 Shimizu etal.
`4,702,936 10/1987 Maeda et al.
`437/241
`4,721,938
`l/1988 Stevenson ......
`155/652
`42951445 3/1990 L09 3‘ 31-
`437/974
`5,o71,s1o12/1991 Findleretal. ..
`156/662
`5,110,373
`5/1992 Mauger ............................... 437/974
`
`
`
`[56]
`
`Primary Examiner—Brian I-learn
`
`16 Claims, 64 Drawing Sheets
`
`MICRON ET AL. EXHIBIT 1006
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`MEMBRANE DIELECTRIC ISOLATION IC
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`
`FABRICATION
`
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`
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`
`
`BACKGROUND OF THE INVENTION
`
`
`
`1. Field of the Invention
`
`
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`This invention relates to methods for fabricating inte-
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`grated circuits on and in flexible membranes, and to
`structures fabricated using such methods.
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`2. Description of Related Art
`Mechanically and thermally durable free standing
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`dielectric and semiconductor membranes have been
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`disclosed with thicknesses of less than 2 pm. (See com-
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`monly invented U.S. Pat. No. 4,924,589, and U.S. patent
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`application Ser. No. 07/482,135, filed Feb. 16, 1990,
`now U.S. Pat. No. 5,103,557, both incorporated herein
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`by reference). This disclosure combines the novel use of
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`these technologies and other integrated circuit (IC)
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`processing techniques to form ICs as membranes typi- 20
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`cally less than 8 pm thick. This approach to IC fabrica-
`tion falls under the generic industry-established title
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`known as Dielectric Isolation (DI), and is inclusive of
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`subject areas such as Silicon-on-Insulator (SOI) and
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`Silicon-on-Sapphire (SOS). ICs formed from dielectric 25
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`and semiconductor membranes can reduce significantly
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`the number and complexity of processing steps pres-
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`ently used to provide complete IC device isolation;
`dielectric isolation techniques that provide dielectric
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`isolation on all surfaces of the individual circuit devices
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`comprising the complete IC are not as yet widely used
`in volume IC fabrication. Integrated Circuits are de-
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`fined as commonly understood today when referring to
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`SSI, MSI, LSI, VLSI, ULSI, etc. levels of circuit com-
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`plexity.
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`SUMMARY OF THE INVENTION
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`This invention is directed to a general method for the
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`fabrication of integrated circuits and interconnect met-
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`allization structures from membranes of dielectric and
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`semiconductor materials. The fabrication technology in
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`accordance with this invention is referred to herein as
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`Membrane Dielectric Isolation (MDI), and the circuits
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`made from it as circuit membranes. The novel use of
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`materials and processing techniques provides for the 45
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`fabrication of high temperature, mechanically durable,
`large area free standing membranes (greater than 1
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`square cm in area) from low stress dielectric and/or
`semiconductor films. These membranes permit the ap-
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`plication (continued use) of most of the established 50
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`integrated processing methods for the fabrication of
`circuit devices and interconnect metallization.
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`In accordance with the invention, an integrated cir-
`cuit is formed on a tensile low stress dielectric mem-
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`brane comprised of one layer or a partial layer of semi-
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`conductor material in which are formed circuit devices
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`and several layers of dielectric and interconnect metalli-
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`zation. Also, a structure in accordance with the inven-
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`tion is a tensile membrane of semiconductor material in
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`which are formed circuit devices with multiple layers of 60
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`tensile low stress dielectric and metallization intercon-
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`nect on either side of the semiconductor membrane.
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`The membrane structure is a processing or manufac-
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`turing structure for enabling the manufacture of novel
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`and more cost effective integrated circuits. This is in
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`addition to an objective to manufacture an integrated
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`circuit, or portion thereof, in a membrane or thin film
`form.
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`2
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`The general categories of circuit membranes that can
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`be made by this invention are:
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`1. Large scale dielectric isolated integrated circuits
`formed on or from semiconductor or non-semiconduc-
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`tor substrates.
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`interconnect metallization circuits
`2. Multi-layer
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`formed on or from semiconductor or non-semiconduc-
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`tor substrates.
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`The primary objectives of the MDI fabrication tech-
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`nology disclosed herein are the cost effective manufac-
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`ture of high performance, high density integrated cir-
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`cuits and integrated circuit interconnect with the elimi-
`nation or reduction of detrimental electrical effects on
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`the operation of individual circuit devices (e.g. diodes,
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`transistors, etc.) by completely isolating with a dielec-
`tric material each such circuit device from the common
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`substrate upon which they are initially fabricated, and
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`therefore, from each other, and to provide a more ver-
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`satile and efficient physical form factor for the applica-
`tion of integrate circuits. Some of the benefits of the
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`MDI IC fabrication process are the elimination or re-
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`duction of substrate current leakage, capacitive cou-
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`pling and parasitic transistor effects between adjoining
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`circuit devices. The MDI IC fabrication process bene-
`fits extend to several other categories of IC fabrication
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`such as lower IC processing costs due to fewer IC isola-
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`tion processing steps, greater IC transistor densities
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`through the capability to use established IC processing
`techniques to fabricate interconnect metallization on
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`both sides of a MDI IC circuit membrane, and greater
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`IC performance through novel transistor structures.
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`The strength of the MDI processes is primarily
`drawn from two areas:
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`(1) The ability to make a large area flexible thin film
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`free standing dielectric membrane, typically framed or
`suspended or constrained at its edges by a substrate
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`frame or ring, or bonded frame or ring. This membrane
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`is able to withstand a wide range of IC processing tech-
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`niques and processing temperatures (of at least 400° C.)
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`without noticeable deficiency in performance. The
`present dielectric materials that meet these require-
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`ments are silicon dioxide and silicon nitride films when
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`prepared with specific low stress film deposition recipes
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`for instance on equipment supplied by Novellus Sys-
`tems, Inc. Dielectric free standing films created by
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`CVD process methods such as silicon carbide, boron
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`nitride, boron carbon nitride aluminum oxide, alumi-
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`num nitride, tantalum pentoxide, germanium nitride,
`calcium fluoride, and diamond have been produced, and
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`can potentially be used as one of the dielectric materials
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`in a MDI circuit membrane when deposited at an appro-
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`priate level of surface stress. Advances in the technol-
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`ogy for making low stress dielectric films will likely
`produce additional free standing films that can be used
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`as described herein.
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`(2) The ability to form a uniform thin film single
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`crystal semiconductor substrate either as the primary
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`substrate of semiconductor devices or as a carrier sub-
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`strate upon which semiconductor devices could be
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`grown epitaxially. Several methods toward this end are
`disclosed herein, and other techniques which are modi-
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`fications thereof exist. Further, in certain applications
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`polycrystalline semiconductor membranes
`such as
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`polysilicon can be used in substitution for monocrystal-
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`line material.
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`It is the combination of the use of low stress free
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`standing dielectric films with the appropriate process-
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`ing qualities and membrane or thin film single crystal-
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`MICRON ET AL. EXHIBIT 1006
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`Page 66 of 89
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`MICRON ET AL. EXHIBIT 1006
`Page 66 of 89
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`

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`5,354,695
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`3
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`line (monocrystalline), polycrystalline or amorphous
`semiconductor substrate formation that provides much
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`of the advantage of the MDI IC fabrication process.
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`The following methods are encompassed within the
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`present disclosure:
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`1. Methods for the fabrication of low stress free stand-
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`ing (thin film) dielectric membranes that encapsulate
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`each semiconductor device that comprises an IC.
`2. Methods for the formation of uniform thickness
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`semiconductor membrane (thin film) substrates for use
`in combination with low stress dielectric materials.
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`3. Methods for the fabrication of semiconductor de-
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`vices within and on a dielectric membrane that com-
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`prises a circuit membrane.
`4. Methods for the formation of interconnect metalli-
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`zation structures within and on a dielectric membrane
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`that comprises a circuit membrane.
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`The MDI circuit fabrication process in one embodi-
`ment starts with a semiconductor wafer substrate, and
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`results in an IC in the form of a circuit membrane where
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`each transistor or semiconductor device (SD) in the IC
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`has complete dielectric isolation from every other such
`semiconductor device in the IC. Only interconnect at
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`the specific electrode contact sites of the semiconductor
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`devices provides electrical continuity between the semi-
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`conductor devices. The primary feature of the MDI
`process is complete electrical isolation of all semicon-
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`ductor devices of an IC from all of the intervening
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`semiconductor substrate on which or in which they
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`were initially formed and to do so at lower cost and
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`process complexity than existing bulk IC processing
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`methods. Other features of the MDI process are vertical
`electrode contact (backside interconnect metallization),
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`confined lateral selective epitaxial growth, non-sym-
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`metric dopant profiles, and the use of a MDI circuit
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`membrane to serve as a conformal or projection mask
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`for lithography processing. Even if the initial substrate
`with which MDI processing begins with is the most
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`commonly used semiconductor silicon, the resulting IC
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`need not be composed of silicon-based devices, but
`could be of any semiconductor device material such as
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`GaAs, InP, HgCdTe, InSb or a combination of technol-
`ogies such as silicon and GaAs grown on a silicon sub-
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`strate through epitaxial means. Silicon is an inexpensive
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`and well understood semiconductor substrate material
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`with superior mechanical handling properties relative
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`to most other presently established semiconductor ma-
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`terials. The MDI process is not limited to starting with
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`a silicon substrate and the process definition of MDI is
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`not dependent on use of silicon; however, there are
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`presently clear advantages to using silicon as a starting
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`semiconductor substrate, and the chief embodiment
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`disclosed herein of MDI uses a starting semiconductor
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`substrate material of silicon.
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`The benefits to fabricating an IC with the MDI pro-
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`cess are significant over prior art methods, some of
`these benefits being:
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`1. Complete electrical isolation of semiconductor de-
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`vices.
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`2. Vertical semiconductor device structures.
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`3. Lower processing costs through lower processing
`complexity or
`fewer device isolation processing
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`steps.
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`4. Conformal mask lithography through the membrane
`substrate.
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`5. Control of depth of focus during lithography expo-
`sure due to control of substrate thickness.
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`6. Application of interconnect metallization to both
`sides of the IC.
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`7. Through-membrane (substrate) interconnect metalli-
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`zation routing.
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`8. Three dimensional IC structures through the bonding
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`of circuit membrane IC layers.
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`9. Efficient conductive or radiant cooling of IC compo-
`nents of circuit membrane.
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`10. Direct optical (laser) based communication between
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`parallel positioned membrane ICs.
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`11. Higher performance ICs.
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`12. Vertical semiconductor device structure formation.
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`13. Novel selective epitaxial device formation.
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`In some semiconductor technologies it is not neces-
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`sary to have complete isolation between each transistor
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`or semiconductor device, such as certain applications
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`using polycrystalline or amorphous TFTs (thin film
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`transistors). This is not a limitation on the MDI process,
`because semiconductor device side wall isolation is an
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`option in the MDI process. What is novel is that the
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`MDI process provides general methods by which thin
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`films or membranes of dielectric and semiconductor
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`materials can be formed into a free standing IC or cir-
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`cuit membrane.
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`BRIEF DESCRIPTION OF THE FIGURES
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`FIGS. 1a to lj show a dielectric and semiconductor
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`membrane substrate in cross-section.
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`FIG. 2 shows an etched silicon substrate membrane in
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`cross-section.
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`FIGS. 3a, 3b show dielectric membranes with semi-
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`conductor devices.
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`FIG. 4 shows an alignment mark of a circuit mem-
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`brane in cross-section.
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`FIG. 5 shows support structures for a membrane
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`structure isolation structure.
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`FIG. 6a to 61' show a circuit membrane Air Tunnel
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`structure.
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`FIG. 7 shows stacked circuit membranes with optical
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`input/output.
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`FIG. 8 shows a three dimensional circuit membrane.
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`FIGS. 9a to 9j show fabrication of a MOSFET in a
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`membrane.
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`FIGS. 10a to 10d show fabrication of a transistor by
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`lateral epitaxial growth on a membrane.
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`FIGS. 11a to 11fshow vertical MOSFET and bipolar
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`transistors formed on a membrane.
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`FIG. 12a to 12g show transistor fabrication on a
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`membrane using confined laterally doped epitaxy.
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`FIGS. 12h to 12j show cross-sections of selective
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`epitaxial growth on a membrane.
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`FIGS. 13:: to 13:1 show cross-sections of multi-chip
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`modules.
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`FIG. 14 shows a cross-section of a membrane formed
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`on a reusable substrate.
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`FIG. 15 shows a cross-section of the membrane of
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`FIG. 14 with a support frame attached.
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`FIGS. 16a, 16b show multi-chip modules in packages.
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`FIGS. 17a to 17¢ show soldering of bond pads of a
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`circuit membrane to a die.
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`FIG. 18 shows bond pads on a die.
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`FIGS. 19a, 19b show bonding and de-bonding of a die
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`to a circuit membrane.
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`FIGS. 20, 21 show two sides of a circuit membrane.
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`FIGS. 22a to 226 show formation of a metal trace in
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`a circuit membrane by a lift-off process.
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`MICRON ET AL. EXHIBIT 1006
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`Page 67 of 89
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`MICRON ET AL. EXHIBIT 1006
`Page 67 of 89
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`

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`5
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`FIGS. 23a, 23b show use of a buried etch stop layer
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`to form a circuit membrane having a thinner inner por-
`tion.
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`FIGS. 24, 25 show a source-integrated light valve for
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`direct write lithography.
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`FIGS. 26, 27 are cross-sections of X-ray sources for
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`the device of FIGS. 24, 25.
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`FIGS. 28a to 28b show a coil for the device of FIG.
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`24.
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`FIGS. 29a to 29k show portions of a source-external
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`radiation valve for direct write lithography device.
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`FIGS. 291 to 29p show use of fixed freestanding mem-
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`brane lithography masks.
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`FIG. 30 shows a cross-section of a lithographic tool.
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`FIGS. 31:: to 31c show cross-sections of a display
`formed on a membrane.
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`FIGS. 32a, 32b show bonding of two circuit mem-
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`branes.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`The MDI process is the formation of an IC or inter-
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`connect metallization circuit as a free standing dielec-
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`tric and/or semiconductor circuit membrane. Each
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`semiconductor device comprising an IC circuit mem-
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`brane is a semiconductor device optionally isolated
`from adjoining semiconductor devices, and where each
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`semiconductor device is formed on or in a membrane of
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`semiconductor material typically less than 8 pm in
`thickness. The overall thickness of a circuit membrane
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`is typically less than 50 pun and preferably less than 8
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`pm. The dielectric membrane is compatible with most
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`higher temperature IC processing techniques.
`MDI Fabrication Process
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`Several process variations can be used to form the
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`thin film or membrane of semiconductor material for
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`use in the MDI process. Additional related methods for
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`forming semiconductor membranes may exist or come
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`into existence and are included in the MDI technology.
`Examples of some of the methods that can be used for
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`forming silicon single crystal thin films are:
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`1. Heavily boron doped (typically greater than 1013
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`atoms/cmz) etch stop layer (formed by diffusion, im-
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`plant or epitaxy) with optional epitaxial SiGe (less than
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`20% Ge) anti—autodoping overlayer layer and optional
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`epitaxial layer.
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`2. 02 (oxide) and N2 (Nitride) implant etch stop bar-
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`rier layer. Implant concentrations are typically between
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`10 to 100 times less for formation of an etch stop barrier
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`layer than that required to form a buried oxide or nitride
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`dielectric isolation layer as presently done with a stan-
`dard thickness silicon substrate.
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`3. Buried oxide etch stop barrier layer formed from a
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`porous silicon layer.
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`4. High precision double sided polished substrate and
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`masked timed chemical etch back of back-side.
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`5. Electro-chemical etch stop.
`6. Buried etch stop layer formation through anodic or
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`thermal wafer bonding in combination with precision
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`substrate polishing and chemical etching.
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`There are many established methods for forming thin
`semiconductor substrates or membranes. The MDI
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`process requires that
`the semiconductor membrane
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`forming process (thinning process) produce a highly
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`uniform membrane typically less than 2 pm thick and
`that the surface tension of the semiconductor membrane
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`be in low tensile stress. If the membrane is not in tensile
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`6
`stress, but in compressive stress, surface flatness and
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`membrane structural integrity will in many cases be
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`inadequate for subsequent device fabrication steps or
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`the ability to form a sufficiently durable free standing
`membrane.
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`The use of highly doped layers on the surface or near
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`the surface of the substrate formed by diffusion, implant
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`or epitaxial means is an established method for forming
`a barrier etch stop layer. A heavily doped boron layer
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`will etch 10 to 100 times slower than the rest of the
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`substrate. However, if it is to form an effective uniform
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`membrane surface, autodoping to the lower substrate
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`and to the upper device layer must be prevented or
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`minimized. This is accomplished in one method by epi-
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`taxially growing a SiGe layer of less than 4,000./ii
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`(1A=10-1°m) and less than 25% Ge on either side of
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`the barrier etch stop. The SiGe layers and the barrier
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`etch stop layers are subsequently removed after forma-
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`tion of the membrane in order to complete device di-
`electric isolation.
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`The MDI process for forming a dielectric membrane
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`requires that the dielectric material be deposited in net
`surface tensile stress and that the tensile surface stress
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`level be 2 to 100 times less than the fracture strength of
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`the dielectric. Consideration is also given to matching
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`the coefficient of thermal expansion of the semiconduc-
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`tor material and the various dielectric materials being
`used in order to minimize the extrinsic net surface stress
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`of the membrane. Thermally formed silicon dioxide
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`forms as a strongly compressive film and most depos-
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`ited dielectrics currently in use form typically with
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`compressive surface stress. High temperature silicon
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`dioxide and silicon nitride dielectric deposited films
`with tensile surface stress levels 100 times less than their
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`fracture strength have been demonstrated as large area
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`free standing membranes consistent with the require-
`ments of the MDI process.
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