UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.
`Petitioner
`
`v.
`
`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Patent No. 8,791,581
`____________________
`
`DECLARATION OF DR. PAUL D. FRANZON
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,791,581
`
`
`
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`III.
`
`IV.
`
`V.
`
`VI.
`
`INTRODUCTION .............................................................................................................. 1
`
`QUALIFICATIONS ........................................................................................................... 1
`
`SUMMARY OF OPINIONS .............................................................................................. 4
`
`TECHNOLOGICAL BACKGROUND.............................................................................. 5
`
`LEVEL OF ORDINARY SKILL IN THE ART .............................................................. 35
`
`THE ’581 PATENT .......................................................................................................... 36
`
`A.
`
`B.
`
`Summary of the ’581 Patent ................................................................................. 36
`
`Claim Construction ............................................................................................... 43
`
`1.
`
`“Substantially flexible… semiconductor substrate” (Claims 36, 54,
`78, 116, and 136) ...................................................................................... 43
`
`VII. THE PRIOR ART TEACHES OR SUGGESTS EVERY FEATURE OF THE
`CHALLENGED CLAIMS OF THE ’581 PATENT ........................................................ 45
`
`A.
`
`Overview of the Prior Art References .................................................................. 45
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`U.S. Patent No. 5,627,106 (“Hsu”) (Ex. 1008) ......................................... 45
`
`U.S. Patent No. 5,354,695 (“Leedy ’695”) (Ex. 1006) ............................. 53
`
`U.S. Patent No. 5,208,782 (“Sakuta”) (Ex. 1067) .................................... 59
`
`U.S. Patent 5,502,333 (“Bertin ‘333”) (Ex. 1010) .................................... 71
`
`Japanese Patent Publication H3-151637 (“Kowa”) (Ex. 1007) ................ 77
`
`B.
`
`Hsu, Leedy ’695, and Sakuta Teach or Suggest Every Feature of Claims 1,
`5, 12, 36, 54, 78, 113, 116, 133, and 136, as Construed by Petitioner ................. 80
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Claim 1 ...................................................................................................... 80
`
`Claim 5 ...................................................................................................... 91
`
`Claim 12 .................................................................................................. 101
`
`Claim 36 .................................................................................................. 109
`
`Claim 54 .................................................................................................. 116
`
`
`
`i
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`Claim 78 .................................................................................................. 118
`
`Claim 113 ................................................................................................ 121
`
`Claim 116 ................................................................................................ 126
`
`Claim 133 ................................................................................................ 129
`
`6.
`
`7.
`
`8.
`
`9.
`
`10.
`
`Claim 136 ................................................................................................ 133
`
`C.
`
`D.
`
`Stress Balancing .................................................................................................. 135
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`Opinions Under Alternative Constructions of Certain Claim Features .............. 136
`
`VIII. CONCLUSION ............................................................................................................... 137
`
`
`
`
`
`ii
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`I, Paul D. Franzon, declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Micron Technology, Inc. and SK hynix Inc.
`
`(collectively, “Petitioner”) as an independent expert consultant in this proceeding
`
`before the United States Patent and Trademark Office (“PTO”).
`
`2.
`
`I have been asked to consider whether certain references teach or
`
`suggest the features recited in claims 1, 5, 12, 36, 54, 78, 113, 116, 133, and 136 of
`
`U.S. Patent No. 8,791,581 (“the ’581 patent”) (Ex. 1001), which I understand is
`
`allegedly owned by Elm 3DS Innovations, LLC (“Patent Owner”). My opinions
`
`and the bases for my opinions are set forth below.
`
`3.
`
`I am being compensated at my ordinary and customary consulting rate
`
`for my work.
`
`4. My compensation is in no way contingent on the nature of my
`
`findings, the presentation of my findings in testimony, or the outcome of this or
`
`any other proceeding. I have no other interest in this proceeding.
`
`II. QUALIFICATIONS
`
`5.
`
`I am a currently a Distinguished Professor in the Department of
`
`Electrical and Computer Engineering at North Carolina State University (“NCSU”)
`
`in Raleigh, North Carolina. I have been affiliated with NCSU in various roles
`
`since 1989.
`
`1
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`I obtained my Ph.D. in Electrical and Electronic Engineering in 1989
`
`6.
`
`from the University of Adelaide in Australia. I obtained two additional degrees
`
`from the University of Adelaide, a Bachelor of Engineering in Electrical and
`
`Electronic Engineering (1984) and a Bachelor of Science in Physics and
`
`Mathematics (1983).
`
`7.
`
`I have well over twenty years of experience with 3D circuits,
`
`applications, analysis, and fabrication. “3D” refers to stacking of chips or circuits,
`
`interconnecting and bonding multiple circuit layers (e.g., with through-silicon vias
`
`(“TSVs”)), and the packaging of these chips. My experience in 3D circuits began
`
`in the 1980s when I began publishing on Wafer Scale Integration and other related
`
`topics.
`
`8.
`
`I have been involved in 3D memory stacks in various projects,
`
`including early projects with MCNC, my work for Rambus where I am a named
`
`inventor on certain Rambus memory patents, and current work with the Air Force
`
`Research Labs, Tezzaron, and Intel.
`
`9.
`
`I have worked on several other projects in and regarding 3D
`
`integration, including design and submission projects for fabrication of 3D logic
`
`structures, as funded by DARPA, Google, and Intel, as well as 3D thermal
`
`analysis, as funded by Qualcomm.
`
`2
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`10. While a professor at NCSU, I have built and developed processes for
`
`integrating 3D chip stacks using contactless signaling. I am currently the principal
`
`investigator of a project conducting detailed stress and thermal analysis of a 3D
`
`heterogeneous chip stack. Other projects of mine in this area include exploring
`
`advantages specific to 3D in computing, signal processing and other areas, as well
`
`as putting together Computer Aided Design flows to support 3D design.
`
`11. While Vice President of Engineering for Lightspin, I led a group that
`
`put together fabrication recipes for, and fabricated and tested a series of Gallium
`
`Arsenide based Light Emitting Diodes and Heterojunction Bipolar Transistors.
`
`These were built largely in the Nanofabrication Facility at NCSU. While a
`
`professor at NCSU, my group has put together fabrication recipes for, and
`
`fabricated and tested a number of micromachined structures for various
`
`applications as well as a new memory device. These were built largely in the
`
`Nanofabrication Facility at NCSU.
`
`12.
`
`I have also authored nearly 300 peer-reviewed articles, chapters,
`
`textbooks, and other publications relating primarily to electrical engineering and
`
`VLSI design, including numerous publications directed to 3D chip stack
`
`technologies and applications. I have authored and/or edited three books,
`
`including two concerning multichip modules and packages in 1993 and 1996. I
`
`co-authored an article entitled “A Review of 3-D Packaging Technology,” where I
`
`3
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`reviewed the state-of-the-art in three dimensional (“3-D”) packaging technology
`
`for VLSI applications that existed by 1997. I also reviewed various vertical
`
`interconnect techniques that existed at the time that were used for 3D stacking of
`
`integrated circuits. This article was ultimately published in the IEEE Transactions
`
`on Components, Packaging and Manufacturing Technology in February 1998.
`
`13.
`
`I have been awarded sixty research grants and contracts, one
`
`equipment grant, one educational grant, and seven cash gifts which total over
`
`$41 million.
`
`14. Additional qualifications are detailed in my curriculum vitae, which I
`
`understand has been submitted as Exhibit 1003 in this proceeding.
`
`III. SUMMARY OF OPINIONS
`
`15.
`
`In preparing this declaration, I have reviewed the documents
`
`identified in Appendix A and other materials referred to herein. In addition to
`
`these materials, I have relied on my education, experience, and my knowledge of
`
`practices and principles in the relevant field, e.g., semiconductor processing. My
`
`opinions have also been guided by my appreciation of how one of ordinary skill in
`
`the art would have understood the claims and specification of the ’581 patent
`
`around the time of the alleged invention, which I have been asked to assume is the
`
`earliest claimed priority date of April 4, 1997.
`
`4
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`16. Based on my experience and expertise, it is my opinion that certain
`
`references teach or suggest all the features recited in claims 1, 5, 12, 36, 54, 78,
`
`113, 116, 133, and 136 of the ’581 patent, as explained in detail below.
`
`IV. TECHNOLOGICAL BACKGROUND
`
`1.
`
`Traditional “2d” Circuits
`
`17. An integrated circuit (“IC”) is electronic circuitry typically fabricated
`
`on a thin slice of silicon called a wafer and then is “singulated” or cut into
`
`individual devices known as a die or dice. A basic two-dimensional (“2D”) IC is a
`
`standard IC with a single, active circuit layer where a die or dice are mounted in a
`
`package in a single plane. 2D ICs are the most common form of IC and have
`
`existed since the creation of the IC in 1958. Within each die, a 2D IC has a wafer
`
`as a base level, typically made of silicon, with various other materials implanted
`
`within and/or deposited on top of the wafer. For example, 2D IC’s have metal
`
`wiring that forms the connections for the transistors of the IC. This is commonly
`
`referred to as a conductive and/or metal layer or level. 2D ICs also have one or
`
`more “thin films” of non-metal materials ranging from a few nanometers to several
`
`micrometers (commonly referred to as micron(s) and/or the symbol µm) thick that
`
`are grown or deposited on an IC. Ex. 1040 at 109-10. One common “thin film”
`
`used in IC design is a dielectric film. The basic function of a dielectric is as an
`
`electrical insulator. Dielectrics provide crucial functions in integrated circuits most
`
`5
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`commonly to isolate various components in an IC chip from the substrate and from
`
`each other, such as isolating the metal layer from other elements on the IC.
`
`18. Silicon wafers are cut from a grown crystalline ingot. By far the
`
`majority of silicon wafers used to make integrated circuits, such as DRAMs,
`
`SRAMs, EPROMS, analog, and logic are made from single crystal wafers, that is,
`
`wafers grown to have a uniform single crystal lattice. The alternative is a
`
`polycrystalline wafer, which does not have a single uniform crystal lattice.
`
`Ex. 1040, Ch. 1. Though Wolf does not use the term “monocrystalline,” a
`
`practitioner of the art would have used that term interchangeably with “single
`
`crystal,” “mono” meaning “single” in this context. Wolf states, “[i]f the [crystal]
`
`periodic arrangement exists throughout the entire solid, the substance is defined as
`
`being formed of a single crystal. If the solid is composed of a myriad of small
`
`single crystal regions the solid is referred to as polycrystalline material.” Id. at 1-2.
`
`Wolf goes on, “The fabrication of VLSI takes place on silicon substrates
`
`possessing very high crystalline perfection. G.K. Teal originally recognized the
`
`critical importance of utilizing single crystal material for the transistor regions of
`
`microelectronic circuits. He reasoned that polycrystalline material would exhibit
`
`inadequately short minority carrier lifetimes.” Id. at 5.
`
`19. Terms like “top,” “bottom,” “front,” “back,” and “face,” often with
`
`the addendum “side,” are typically used to refer to a particular side of a wafer or
`
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`Inter Partes Review of U.S. Patent No. 8,791,581
`substrate. In the field, “top,” “front,” and “face” generally refer to the side of the
`
`silicon wafer on which the transistors and metal layers are built, while “back” and
`
`“bottom” are the opposing side.
`
`20. Since the creation of the IC in 1958, the microelectronics industry has
`
`worked to improve computing power and efficiency of electronic structures. This
`
`constant drive to improve IC’s was so predictable that, in 1965, Gordon Moore
`
`coined “Moore’s law,” which states that the number of transistors on an IC would
`
`double approximately every year (later revised in 1975 to every two years). This
`
`“law” has been the most powerful driver for the development of the
`
`microelectronics industry in the past 50 years. Higher computing power has been
`
`achieved primarily through scaling down device dimensions (such as individual
`
`transistors) to include more transistors in a semiconductor device. Semiconductor
`
`devices are made in wafer form, and then singulated to create individual die. Due
`
`to the desire for high yield (the percentage of the die that functions correctly), these
`
`die, or chips, are relatively small. These size limits in turn limit the amount of
`
`connectivity between chips, especially as off-chip connection bandwidth does not
`
`scale with Moore’s Law. Among the issues that 2D IC designers faced that are
`
`relevant to the patent at issue in this matter are thinning and polishing of the
`
`substrate, increasing off-chip connection bandwidth and material stress
`
`management to address, for example, IC warping and cracking.
`
`7
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`Thinning and Polishing
`
`a)
`
`21. Since the early days of IC mass fabrication in the 1960s, IC designers
`
`have thinned and polished substrates to create thin electronic circuits that could fit
`
`in ever-smaller commercial devices. See, e.g., Ex. 1041. In IC fabrication,
`
`typically, a large, single crystal of silicon is shaped into a solid cylinder (known as
`
`ingots), and then sliced into thin discs called wafers. The resulting wafer is
`
`processed so that thin chips could be implemented in microelectronics. Thinning
`
`has traditionally been performed by backside grinding and polishing of the silicon
`
`wafer. Rather than leave a rough, unfinished surface after grinding, it was a
`
`common practice to polish the ground substrate to reduce surface roughness. See,
`
`e.g., Ex. 1040 at xxiii, 6, 24. A polished surface was desired due to a known
`
`correlation between wafer back surface roughness and the resistance to stress
`
`induced failures. Ex. 1016. In some cases, grinding removed much more substrate
`
`whereas polishing was used as a final step to reach a desired thickness. For
`
`example, Motorola’s U.S. Patent No. 3,508,980 discusses a common practice of
`
`backside thinning of a silicon substrate and polishing to reach desired and uniform
`
`thickness. Ex. 1041 at 1:19-31, 2:8-10, 3:33-35.
`
`b)
`
`Through Silicon Vias
`
`22. The microelectronics industry has, since nearly the inception of the
`
`IC, also implemented vertical interconnections to connect different surfaces of an
`
`8
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`Inter Partes Review of U.S. Patent No. 8,791,581
`IC. In 1958, Nobel Laureate William Shockley, the co-inventor of the transistor,
`
`invented the first of what is now known as a through silicon via (“TSV”). In U.S.
`
`Patent No. 3,044,909, Mr. Shockley described and depicted holes that could be
`
`used as a TSV:
`
`Ex. 1042 at Fig 4 (annotation added). According to Mr. Shockley, these “holes”
`
`would allow electrical connection through the wafer to various layers within the
`
`
`
`IC. Id. at 2:27-49.
`
`c)
`
`Stress Management
`
`23. As the microelectronics industry created more powerful and efficient
`
`2D ICs, the industry was also concerned with improving the reliability of the ICs.
`
`For semiconductor fabricators, one important measurement of success is
`
`commonly referred to as the “yield,” which is the proportion of semiconductor
`
`devices on a wafer that function properly. The greater the yield, the more
`
`semiconductor devices a manufacturer can sell. Many of the processes used in the
`
`fabrication of silicon ICs, however, impose stress on the silicon substrate which
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`Inter Partes Review of U.S. Patent No. 8,791,581
`may ultimately affect the yield. Consequently, stress has always been a concern of
`
`any IC design.
`
`24.
`
`In the context of semiconductors, stress (σ) is the force per unit area
`
`that is acting on a surface of a solid. It is usually expressed in terms of Mega
`
`Pascals (“MPa”) or dynes/cm2. 50 MPa is the equivalent of 5x108 dynes / cm2.1
`
`Stress can be classified in two groups: extrinsic and intrinsic. Extrinsic stress is
`
`caused by the different coefficients of thermal expansion of the different materials
`
`that are added as films go into making an integrated circuit. Generally these
`
`materials are not deposited at room temperature. As the wafer cools after adding a
`
`new material, the different materials contract at different rates, causing stress.
`
`Intrinsic stress depends on a number of factors such as deposition rate, deposition
`
`temperature, pressure in the deposition chamber, incorporation of impurities during
`
`growth, grain structure, and fabrication process defects.
`
`25. Stress also can be uniform or non-uniform throughout a thin film. If
`
`the stress is uniform, its measurement will give an average stress. If the stress is
`
`non-uniform, a difference of stress or stress gradient exists between the top and
`
`the bottom of the thin film, as well as different stress at different locations from the
`
`center of the film outward to the edges. There is a vertical and lateral variation of
`
`stress. Consequently, just indicating that a film is “low stress” or “low tensile
`
`
`1 This is the relevant stress level mentioned in the patent at issue.
`
`10
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`Inter Partes Review of U.S. Patent No. 8,791,581
`stress” does not provide enough context to one of skill in the art because the phrase
`
`alone does not indicate whether extrinsic or intrinsic stress, average stress
`
`measurement, or the measurement point along the film is indicated. For net stress,
`
`each individual film contributes stress, either positive (tensile) or negative
`
`(compressive). Therefore, the net stress is the sum of the individual IC films
`
`contributions since each are additive.
`
`26. A film under stress can expand or contract by bending in a vertical
`
`direction. According to the Wolf Textbook:
`
`Nearly all films are found to be in a state of internal stress, regardless
`of the means by which they have been produced. The stress may be
`compressive or tensile. Compressively stressed films would like to
`expand parallel to the substrate surface, and in the extreme, films in
`compressive stress will buckle up on the substrate, as shown in Fig. 4.
`Films in tensile stress, on the other hand, would like to contract
`parallel to the substrate, and may crack if their elastic limits are
`exceeded.
`
`Ex. 1040 at 114 (emphasis in original). In other words, “tensile” suggests a film
`
`that is in tension, meaning that it pulls outward. “Compressive” suggests a film
`
`that is in compression, meaning that it pushes inward. The Wolf Textbook further
`
`provides a graphical depiction of the effects tensile and compressive stresses may
`
`have on a substrate after thin film deposition:
`
`11
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`Inter Partes Review of U.S. Patent No. 8,791,581
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`
`
`
`
`Id. at 117.
`
`27. As depicted in the image above from the Wolf Textbook, given
`
`enough stress, a silicon substrate will bend and possibly generate dislocations.
`
`Other potential mechanical stress related issues include wafer cracking, metal
`
`voiding, fracture and delamination of films, and other mechanically induced
`
`problems. There are many sources of stress that arise during the fabrication
`
`processes. Some examples are the use of materials with a coefficient of thermal
`
`expansion (“CTE”) “different from that of silicon, deposition of films with
`
`intrinsic stress, and oxidation of nonplanar surfaces.” Ex. 1043 at 158 (discussing
`
`the mechanical stress related issues that may occur in semiconductor fabrication).
`
`28. One of the first comprehensive reviews of the mechanical properties
`
`of thin films was published by R. W. Hoffman in 1966. See Ex. 1044. This
`
`publication contains a section on the intrinsic stresses in evaporated films. Id. at
`
`219-53. Mr. Hoffman’s data showed that metal films produced by evaporation (the
`
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`Inter Partes Review of U.S. Patent No. 8,791,581
`dominant technology at the time) were generally in tension, whereas dielectric
`
`compounds exhibited both tensile and compressive stress.
`
`29. Moreover, since the beginning of semiconductor wafer fabrication,
`
`semiconductor manufacturers have examined stress management to reduce the
`
`potential of mechanical stress induced problems. Specifically, by 1979, the
`
`industry had already examined mechanical stresses that occurred as a result of the
`
`deposition in thin films on semiconductor substrates. In one article, it was
`
`disclosed that “The mechanical properties of materials used in Si [silicon] device
`
`processing, such as Si, thermal SiO2 [silicon dioxide], and deposited SiO2 and
`
`Si3N4 [silicon nitride], are rapidly becoming limiting factors in advanced
`
`integrated-circuit technology.” Ex. 1045 at 8. In particular, Mr. EerNisse
`
`observed that “high-temperature dislocation” occurred between silicon and
`
`deposited films such as silicon dioxide and silicon nitride and “lead to yield
`
`problems as device packing density increases. Mechanical stress-induced cracking
`
`in Si3N4/SiO2 masking layers at discontinuities degrades yield.” Id. Mr. EerNisse
`
`also recognized that stress free and/or “small tensile stresses” could be created in
`
`SiO2 films by growing such films at high temperature. Id. Mr. EerNisse disclosed
`
`that “[n]o stress is observed at 975 and 1000o C with possible small tensile stresses
`
`seen above 1000o C.” Id. at 10 (emphasis added). He then concluded that his
`
`“results, which treat the stresses during growth at the growth temperature, should
`
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`Inter Partes Review of U.S. Patent No. 8,791,581
`be of value in avoiding mechanical damage effects in VLSI or VHSI technologies
`
`by careful choice of SiO2 growth temperatures.” Id.
`
`30. By 1987, several industry members recognized the mechanical stress
`
`related problems associated with the deposition of thin films on silicon substrates
`
`and recommended controlling stress to limit stress related failures in
`
`semiconductor manufacturing. One approach was the use of films with
`
`intrinsically low stress. For example, in the Wolf Textbook, it was suggested that
`
`the use of high stressed films would be disadvantageous for various reasons:
`
`In general, the stresses in thin films are in the range of 108-5 x 1010
`dynes/cm2. Highly stressed films are generally undesirable for
`VLSI applications for several reasons, including: a) they are more
`likely to exhibit poor adhesion; b) they are more susceptible to
`corrosion; c) brittle films, such as inorganic dielectrics, may undergo
`cracking in tensile stress; and d) the resistivity of stressed metallic
`films is higher than that of their annealed counterparts.
`
`Ex. 1040 at 115 (emphasis added). By providing a range of stresses and
`
`recommending avoiding “highly stressed films,” the Wolf Textbook taught the use
`
`of low stress films closer to the base of the given range which he identified as
`
`1x108 dynes/cm2.
`
`31.
`
`Industry participants also recognized the disadvantages of using
`
`intrinsically high stressed films. In September 1987, IBM published an article that
`
`recognized that “[t]he fracture and delamination of thin films is a relatively
`
`common occurrence, and prevention of these mechanical failures is essential for
`
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`the successful manufacture of thin-film devices.” Ex. 1046 at 585. IBM noted the
`
`source of mechanical stress related issues was the use of thin films with an intrinsic
`
`stress above 109 dynes/cm2:
`
`[S]tress present in thin films is an inherent part of the deposition
`process, and can be either tensile or compressive. The sign and
`magnitude of film stress are for the most part determined by the
`deposition parameters, i.e., substrate temperature, kind of substrate,
`deposition rate, and method of deposition. Stresses of about 109 - 1010
`dynes/cm2 are often observed, and it has been commonly found that
`these stresses cause film fracture, delamination, and occasionally
`substrate fracture.
`
`Id. (emphasis added). IBM concluded that “[t]o avoid catastrophic film failure
`
`[stress and film thickness] must be reduced in some manner.” Id. at 590. To deal
`
`with these issues in memory devices in particular, another IBM article recognized
`
`that “[t]wo general approaches can be followed to eliminate dislocation generation
`
`in DRAM cells: Reduce the amount of stress in the substrate or eliminate the
`
`source of nucleation for dislocations.” Ex. 1043 at 178.
`
`32. By 1990, the prior art taught that the way to avoid mechanical stress
`
`related issues due to high stress films placed directly on the substrate was to use
`
`low-tensile stress dielectrics. For example, U.S. Patent No. 4,948,482 proposed a
`
`method for forming a silicon nitride film for use in “semiconductor chips or
`
`memory disks and an X-ray transmission film.” Ex. 1047 at 1:7-10. In particular,
`
`Kobayashi found that depositing a 2μm thick silicon nitride film on a silicon
`
`15
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`Page 18 of 140
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`

`
`Declaration of Dr. Paul D. Franzon
`
`Inter Partes Review of U.S. Patent No. 8,791,581
`
`substrate where “sputtering gas pressure = 0.5 Pa, the internal stress can be
`
`controlled at 5x108 dyne/cmz or less in terms of a tensile stress over a wide
`
`substrate temperature range of 200—290° C. . .
`
`Id. at 4:18-21 (emphasis added).
`
`33.
`
`Likewise, NEC published a paper in 1990 where the authors posited
`
`that “the dielectrics deposition temperature induced stress, caused by the difference
`
`of the expansion coefficients to Al [aluminum], is the main factor for [stress-
`
`migration].” Ex. 1048 at 363. Thus, NEC concluded the “best way of dielectrics
`
`formation against [stress-migration] is, ‘depositing low Al diffusivity dielectrics at
`
`low temperature after stress [sic] reluxation.” Id. As part of its experiments, NEC
`
`showed that using a spin—on polyimide layer of 0.5 pm thickness would result in a
`
`low tensile stress of 50 MPa (5x108 dyne/cmz) with zero failures in the film as
`
`depicted below:
`
`Dielectric Flln Influence on Stress-llisretlon
`A. lsobe. K.Okauura. S.Osura and 0.Iizuno
`
`Tables
`
`Typical data of dielectrics deposition conditions and
`open failures after 7000H held in l75'C (N2).
`
`Experinental® Pure Al (l=0.8um)
`
`Material Thickness
`Pre Heat
`Depo Telp. Str ss
`Failure
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`
`16
`
`MICRON ET AL. EXHIBIT 1002
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`Page 19 of 140
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`Declaration of Dr- Paul D. Franzon
`
`Inter Partes Review of U.S. Patent No. 8,791,581
`
`Id. at 364 (annotation added).
`
`34.
`
`The prior art also disclosed how IC designers could achieve the
`
`deposition of low stress films by changing the characteristic of the intrinsic stress
`
`of a film from either “tensile” to “compressive” or vice versa. Novellus, a
`
`prominent semiconductor manufacturing equipment maker, touted the use of Dual
`
`frequency Plasma Enhanced Chemical Vapor Deposition (“PECVD”) to “control
`
`the film stress” in order to reduce “stress cracking, stress induced metal
`
`voiding. .
`
`Ex. 1049 at 194, 196. Novellus stated that Dual Frequency PECVD
`
`could cause “a change in the intrinsic film from tensile to compressive and
`
`increase[] the film density.” Id. at 196. As shown in Figure 3, the change is
`
`gradual and easy to control.”
`
`CONTROL OF FILM STRESS
`STRESS (X 1OE9 D/CM2l
`
` .uu..cnauro_a—Mta)hU|
`
`0
`
`20
`
`60
`40
`PERCEN I LF POWER
`
`80
`
`100
`
`Figure 3.
`
`Film stress as a function
`' percent LF power. The
`total (HF and LF) power
`uleusity in this and following
`fi ures was kept constant at
`— /me.
`
`17
`
`MICRON ET AL. EXHIBIT I002
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`Page 20 of 140
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`

`
`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`
`Id. at 196 (annotation added).
`
`35. As multiple films, metal layers, and other materials were placed on
`
`top of the substrate in a 2D IC, the prior art disclosed that balancing the stress of
`
`these materials was necessary to solve mechanical stress issues such as stress
`
`migration, cracking, delamination, and other stress induced failures. At the time,
`
`the prior art was recommending low stress materials, it also disclosed stress
`
`balancing. For example, Fujitsu’s U.S. Patent No. 5,160,998 disclosed stress
`
`balancing by using differing layers of dielectric material with tensile and
`
`compressive intrinsic stresses:
`
`[A]ccording to one aspect of the present invention, there is provided a
`semiconductor device comprising a semiconductor substrate; a metal
`wiring layer formed on the semiconductor substrate; a first insulation
`layer formed on the metal wiring layer, the first insulation layer being
`formed by a tensile stress insulation layer having a contracting
`characteristic relative to the substrate; and a second insulation layer
`formed on the first insulation layer, the second insulation layer being
`formed by a compressive stress insulation layer having an expanding
`characteristic relative to the substrate.
`
`Ex. 1050 at 1:35-46. By stress balancing, Fujitsu found that:
`
`[A]s show in the experimental data described in detail below, a
`semiconductor device according to the present invention (i.e., a
`semiconductor device comprising a tensile stress insulation layer
`formed on the metal layer and a compressive stress insulation layer
`formed on the tensile stress insulation layer) effectively prevents both
`a disconnection of the metal layers due to stre