throbber
Pin Spacing: 0.1"
`
`0.178"
`
`SIP Style
`
`1.260"
`
`0.628"
`
`HP SERIES RF TRANSMITTER
`TXM-900-HP3-SP*
`LOT 10000
`
`0.150"
`
`SMD Style
`Figure 1: Package Dimensions
`
`HIGH-PERFORMANCE
`RF MODULE
`TXM-900-HP3-xxx
`
`1.290"
`
`0.680"
`
`HP SERIES RF TRANSMITTER
`TXM-900-HP3-PP*
`LOT 10000
`
`WIRELESS MADE SIMPLE ®
`HP3 SERIES TRANSMITTER MODULE DATA GUIDE
`DESCRIPTION
`The HP3 RF transmitter module is the third
`generation of the popular HP Series. Like its
`predecessors, the HP3 is designed for the cost-
`effective, high-performance wireless transfer of
`analog or digital information in the popular 902-
`928MHz band. HP3 Series parts feature eight
`parallel selectable channels, and some versions
`also add direct serial selection of 100 channels.
`To ensure reliable performance, the transmitter
`employs FM / FSK modulation and a micro-
`processor controlled synthesized architecture.
`Both SMD and pinned packages are available.
`When paired with an HP3 receiver, a reliable
`link is created for the transfer of analog and
`digital information up to 1,000 feet. As with all Linx modules, the HP3 requires no
`tuning or additional RF components (except an antenna), making integration
`straightforward, even for engineers without prior RF experience.
`APPLICATIONS INCLUDE
`FEATURES
`n 8 parallel, 100 serial (PS Versions) user-
`n Wireless Networks / Data Transfer
`selectable channels
`n Wireless Analog / Audio
`n FM / FSK modulation for outstanding
`n Home / Industrial Automation
`performance and noise immunity
`n Remote Access / Control
`n Precision frequency synthesized
`n Remote Monitoring / Telemetry
`architecture
`n Long-Range RFID
`n Transparent analog / digital interface
`n MIDI Links
`n Wide-range analog capability including
`n Voice / Music / Intercom Links
`audio (50Hz to 28kHz)
`n Wide temperature range
`(-30°C to +85°C)
`n No external RF
`components required
`n Compatible with previous
`HP Series modules
`n Power-down and CTS
`functions
`n Wide supply range
`(2.8 to 13.0VDC)
`n High data rate
`(up to 56kbps)
`n Pinned and SMD packages
`n No production tuning
`
`ORDERING INFORMATION
`DESCRIPTION
`PART #
`HP3 Transmitter (SIP 8 CH only)
`TXM-900-HP3-PPO
`HP3 Transmitter (SIP 8p / 100s CH)
`TXM-900-HP3-PPS
`HP3 Transmitter (SMD 8 CH only)
`TXM-900-HP3-SPO
`HP3 Transmitter (SMD 8p / 100s CH)
`TXM-900-HP3-SPS
`HP3 Development Kit (SIP Pkg.)
`MDEV-900-HP3-PPS-USB
`HP3 Development Kit (SIP Pkg.)
`MDEV-900-HP3-PPS-RS232
`HP3 Development Kit (SMD Pkg.)
`MDEV-900-HP3-SPS-USB
`HP3 Development Kit (SMD Pkg.)
`MDEV-900-HP3-SPS-RS232
`Transmitters are supplied in tubes of 15 pcs.
`
`Revised 7/27/11
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 1
`
`

`
`ELECTRICAL SPECIFICATIONS
`
`ABSOLUTE MAXIMUM RATINGS
`
`Parameter
`POWER SUPPLY
`Operating Voltage
`Supply Current
`Power-Down Current
`TRANSMIT SECTION
`Transmit Frequency Range
`Center Frequency Accuracy
`Available Channels
`Channel Spacing
`Occupied Bandwidth
`Output Power
`Spurious Emissions
`Harmonic Emissions
`Data Rate
`Analog / Audio Bandwidth
`Data Input:
`Logic Low
`Logic High
`Data Input Impedance
`Frequency Deviation @ 3VDC
`Frequency Deviation @ 5VDC
`ANTENNA PORT
`RF Output Impedance
`TIMING
`Transmitter Turn-On Time
`Channel Change Time
`ENVIRONMENTAL
`Operating Temperature Range
`
`Designation
`
`Min.
`
`Typical
`
`Max.
`
`Units
`
`Notes
`
`VCC
`ICC
`IPDN
`
`FC
`–
`–
`–
`–
`PO
`–
`PH
`–
`–
`
`–
`–
`–
`–
`–
`
`ROUT
`
`–
`–
`
`–
`
`2.8
`–
`–
`
`902.62
`-50
`8 (Par.)
`–
`–
`-3
`–
`–
`100
`50
`
`0.0
`2.8
`–
`60
`90
`
`–
`
`–
`–
`
`-30
`
`3.0
`14.0
`–
`
`–
`–
`–
`250
`115
`0
`-45
`-60
`–
`–
`
`–
`–
`200
`70
`115
`
`50
`
`7.0
`1.0
`
`–
`
`13.0
`17.0
`15.0
`
`927.62
`+50
`100 (Ser.)
`–
`140
`+3
`–
`-47
`56,000
`28,000
`
`0.5
`5.2
`–
`110
`140
`
`–
`
`10.0
`1.5
`
`+85
`
`VDC
`mA
`µA
`
`MHz
`kHz
`–
`kHz
`kHz
`dBm
`dBm
`dBm
`bps
`Hz
`
`VDC
`VDC
`kΩ
`kHz
`kHz
`

`
`mSec
`mSec
`
`°C
`
`–
`1
`2
`
`3
`–
`4
`–
`–
`5
`6
`6
`7
`7
`
`–
`–
`–
`8
`8
`
`–
`
`–
`–
`
`–
`
`Table 1: HP3 Series Transmitter Specifications
`Notes
`1. Over the entire operating voltage range.
`2. With the PDN pin low.
`3. Serial Mode.
`4. 100 serial channels on the PS versions only.
`5. Does not change over the 3-13VDC supply.
`6.
`Into 50 ohms.
`7. The receiver will not reliably hold a DC level. See the HP3 Series Receiver Module Data Guide for the
`minimum transition rate.
`8. The voltage specified is the modulation pin voltage.
`
`*CAUTION*
`This product incorporates numerous static-sensitive components.
`Always wear an ESD wrist strap and observe proper ESD handling
`procedures when working with this device. Failure to observe this
`precaution may result in module damage or failure.
`
`Supply Voltage VCC
`Any Input or Output Pin
`Operating Temperature
`Storage Temperature
`Soldering Temperature
`
`+18.0
`to
`-0.3
`VCC
`to
`-0.3
`+85
`to
`-30
`+85
`to
`-45
`+260°C for 10 seconds
`
`VDC
`VDC
`°C
`°C
`
`*NOTE* Exceeding any of the limits of this section may lead to permanent
`damage to the device. Furthermore, extended operation at these maximum
`ratings may reduce the life of this device.
`
`PERFORMANCE DATA
`These performance parameters
`are based on module operation at
`25°C from a 5.0VDC supply unless
`otherwise
`noted.
`Figure
`2
`illustrates
`the
`connections
`necessary
`for
`testing
`and
`operation. It is recommended all
`ground pins be connected to the
`ground plane. The pins marked NC
`have no electrical connection.
`
`GND
`ANT
`GND
`NC
`CS0
`CS1 / SS CLOCK
`CS2 / SS D
`CTS
`PDN
`VCC
`MODE
`DATA
`
`NC
`NC
`NC
`NC
`GND
`NC
`NC
`NC
`NC
`NC
`NC
`GND
`
`PC
`PC
`PC
`
`5VDC
`
`PC
`
`Figure 2: Test / Basic Application Circuit
`
`TYPICAL PERFORMANCE GRAPHS
`
`VCC / PDN
`
`VCC / PDN
`
`1
`
`1
`
`RX DATA
`
`CTS
`
`2
`
`CH2 2.00V
`CH1 1.00V
`2.5mS
`Figure 3: Power-up to CTS
`
`Delta 7.200mS
`
`2
`
`CH1 1.00V
`Delta 7.200mS
`2.5mS
`CH2 2.00V
`Figure 4: TX Power-up to Valid RX Data
`
`IN
`
`OUT
`
`IN
`
`OUT
`
`Page 2
`
`250μS
`CH1 2.00V
`CH2 500mV
`Figure 5: Sine Wave Modulation Linearity
`
`250μS
`CH1 2.00V
`CH2 500mV
`Figure 6: Square Wave Modulation Linearity
`
`Page 3
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 2
`
`

`
`PIN ASSIGNMENTS
`
`PIN DESCRIPTIONS
`
`Pinned Transmitter
`
`Surface-Mount Transmitter
`
`GND
`ANT
`GND
`NC
`CS0
`CS1 / SS CLOCK
`CS2 / SS DATA
`CTS
`PDN
`VCC
`MODE
`DATA
`
`NC
`NC
`NC
`NC
`GND
`NC
`NC
`NC
`NC
`NC
`NC
`GND
`
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`14
`13
`
`1 2 3 4 5 6 7 8
`
`9
`10
`11
`12
`
`DATA
`MODE
`VCC
`PDN
`CTS
`CS 2 / SS DATA
`CS1 / SS CLOCK
`CS0
`
`0
`3 4 5 6 7 8 9 1
`
`ANT
`GND
`
`1 2
`
`Figure 7: HP3 Series Receiver Pinout
`
`Pin #
`SMD SIP
`
`Name
`
`1
`
`2
`
`1
`
`2
`
`3
`
`4
`
`GND
`
`ANT
`
`GND
`
`NC
`
`Description
`
`Analog Ground
`
`50-ohm RF Output
`
`Analog Ground (SMD only)
`
`Pin #
`SMD Pinned
`1, 3
`13, 20
`
`1
`
`2
`
`5
`
`6
`
`7
`
`2
`
`3
`
`4
`
`5
`
`Name
`
`GND
`
`ANT
`
`CS0
`
`CS1 /
`SS CLOCK
`
`CS2 /
`SS DATA
`
`Equivalent Circuit
`
`Description
`
`50Ω
`
`RF
`Out
`
`25k

`
`25k

`
`25k

`
`CS0
`
`CS1
`
`CS2
`
`CTS
`Out
`
`Analog Ground
`
`50-ohm RF Output
`
`Channel Select 0
`
`Channel Select 1 /
`Serial Select Clock
`
`Channel Select 2 /
`Serial Select Data
`
`Clear-to-Send
`Output
`
`No Electrical Connection. Soldered for physical support
`only.
`
`8
`
`6
`
`CTS
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`CS0
`
`CS1 / SS
`CLOCK
`
`CS2 / SS
`DATA
`
`Channel Select 0
`Channel Select 1 / Serial Select Clock. Channel Select 1
`when in parallel channel selection mode, clock input for
`serial channel selection mode.
`Channel Select 2 / Serial Select Data. Channel Select 2
`when in parallel channel selection mode, data input for
`serial channel selection mode.
`
`CTS
`
`PDN
`
`VCC
`
`Clear-To-Send. This line will go high when the transmitter
`is ready to accept data.
`
`Power Down. Pulling this line low will place the transmitter
`into a low-current state. The module will not be able to
`transmit a signal in this state.
`Supply Voltage
`
`MODE
`
`Mode Select. GND for parallel channel selection, VCC for
`serial channel selection
`
`12
`
`10
`
`DATA
`
`Digital / Analog Data Input. This line will input the
`modulated digital data or analog signal.
`
`GND
`
`NC
`
`13, 20
`
`14-19,
`21-24
`
`Page 4
`
`Analog Ground (SMD only)
`
`No Electrical Connection. Soldered for physical support
`only. (SMD only)
`
`9
`
`10
`
`11
`
`7
`
`8
`
`9
`
`PDN
`
`VCC
`
`MODE
`
`12
`
`10
`
`DATA
`
`VCC
`430k
`
`PDN
`
`Power Down
`(Active Low)
`
`Voltage Input 2.8-13V
`
`MODE
`
`25k

`
`Mode Select
`
`160k
`
`100k
`
`510k
`
`20pF
`
`Digital / Analog Input
`
`4,
`14-19,
`21-24
`
`NC
`
`SMD (Only)
`
`No Electrical Connection
`
`Figure 8: Pin Functions and Equivalent Circuits
`
`Page 5
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 3
`
`

`
`THEORY OF OPERATION
`The HP3 Series transmitter is a high-performance, multi-channel RF transmitter
`capable of transmitting both analog (FM) and digital (FSK) information. FM / FSK
`modulation offers significant advantages over AM or OOK modulation methods,
`including increased noise immunity and the receiver’s ability to capture in the
`presence of multiple signals. This is especially helpful in crowded bands, such
`as the one in which the HP3 operates.
`
`DATA
`IN
`
`MODE
`CS0
`CS1
`CS2
`
`28kHz Low Pass
`Filter
`
`μP
`4MHz
`Int. Osc.
`
`PLL
`
`Modulator
`
`12MHz
`Crystal
`
`Amplifier
`
`Band Pass
`Filter
`
`VCO
`
`RF OUT
`
`Figure 9: HP-3 Series Transmitter Block Diagram
`
`A precision 12.00MHz Voltage Controlled Crystal Oscillator (VCXO) serves as
`the frequency reference for the transmitter. Incoming data is filtered to limit the
`bandwidth, and then used to directly modulate the reference. Direct reference
`modulation inside the loop bandwidth provides fast start-up, while allowing a
`wide modulation bandwidth and near DC modulation capability. This also
`eliminates the need for code balancing.
`The modulated 12.00MHz reference frequency is applied to the Phase-Locked
`Loop (PLL). The PLL, combined with a 902 to 928MHz VCXO, forms a frequency
`synthesizer that can be programmed to oscillate at the desired transmit
`frequency. An on-board microcontroller manages the PLL programming and
`greatly simplifies user interface. The microcontroller reads the channel selection
`lines and programs the on-board synthesizer. This frees the designer from
`complex programming requirements and allows for manual or software channel
`selection. The microcontroller also monitors the status of the PLL and indicates
`when the transmitter is ready to transmit data by pulling the CTS line high.
`The PLL-locked carrier is amplified to increase the output power of the
`transmitter and to isolate the VCO from the antenna. The output of the buffer
`amplifier is connected to a filter network, which suppresses harmonic emissions.
`Finally, the signal reaches the single-ended antenna port, which is matched to
`50 ohms to support commonly available antennas, such as those from Linx.
`CTS OUTPUT
`The Clear-To-Send (CTS) output goes high to indicate that the transmitter PLL
`is locked and the module is ready to accept data. In a typical application, a
`microcontroller will raise the PDN line high and begin to monitor the CTS line.
`When the line goes high, the microcontroller will start sending data. It is not
`necessary to use the CTS output, but if not used, the circuit should wait a
`minimum of 10mS after raising the PDN line high before transmitting data. If data
`is being sent redundantly, there is generally no need to monitor the CTS line or
`to wait a fixed time, though the initial bits may not get through.
`
`Page 6
`
`POWER ON
`
`Parallel Mode
`
`Determine Mode
`
`Serial Mode
`
`Read Channel-
`Selection Inputs
`
`Program Freq. Synth
`To Default CH. 50
`
`Program Frequency
`Synthesizer
`
`Crystal Oscillator
`Begins to Operate
`
`Determine State of
`CTS Output Line
`
`Cycle Here Until
`Channel
`or Mode Change
`
`Crystal Oscillator
`Begins to Operate
`
`Ready for
`Serial Data Input
`
`Program Frequency
`Synthesizer
`
`Determine State of
`CTS Output Line
`
`Cycle Here Until More
`Data Input, Mode Change,
` or PLL Loses Lock
`
`POWER-UP SEQUENCE
`The HP3 transmitter is controlled by an
`on-board microprocessor. When power is
`applied, a start-up sequence is initiated.
`At the end of the start-up sequence, the
`transmitter is ready to transmit data.
`The adjacent figure shows the start-up
`sequence. It is executed when power is
`applied to the VCC line or when the PDN
`line is taken high.
`On power-up, the micro processor reads
`the external channel-selection lines and
`sets the frequency synthesizer to the
`appropriate channel. When the frequency
`synthesizer has locked on to the proper
`channel frequency, the circuit is ready to
`accept data. This is acknowledged by the
`CTS line transitioning high. The module
`will then transmit data from the user’s
`circuit.
`POWER SUPPLY
`The HP3 incorporates a precision, low-dropout
`regulator on-board, which allows operation over an
`input voltage range of 2.8 to 13 volts DC. Despite this
`regulator, it is still important to provide a supply that is
`free of noise. Power supply noise can significantly
`affect the transmitter modulation; therefore, providing
`a clean power supply for the module should be a high
`priority during design.
`Figure 11: Supply Filter
`A 10Ω resistor in series with the supply followed by a
`10µF tantalum capacitor from VCC to ground will help in cases where the quality
`of supply power is poor. This filter should be placed close to the module’s supply
`lines. These values may need to be adjusted depending on the noise present on
`the supply line.
`USING THE PDN PIN
`The Power Down (PDN) line can be used to power down the transmitter without
`the need for an external switch. This line has an internal pull-up, so when it is
`held high or simply left floating, the module will be active.
`When the PDN line is pulled to ground, the transmitter will enter into a low-
`current (<15µA) power-down mode. During this time, the transmitter is off and
`cannot perform any function.
`The PDN line allows easy control of the transmitter state from external
`components, such as a microcontroller. By periodically activating the transmitter,
`sending data, then powering down, the transmitter’s average current
`consumption can be greatly reduced, saving power in battery-operated
`applications.
`
`Figure 10: Start-up Sequence
`
`10Ω
`
`Vcc IN
`
`Vcc TO
`MODULE
`
`+
`
`10μF
`
`Page 7
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 4
`
`

`
`ADJUSTING THE OUTPUT POWER
`Depending on the type of antenna being used, the output power of the
`transmitter may be higher than FCC regulations allow. It is intentionally set high
`to compensate for losses resulting from inefficient antennas. Since attenuation is
`often required, it is generally wise to provide for its implementation so that the
`FCC test lab can easily attenuate the transmitter to the maximum legal limit.
`ANTENNA
`A T-pad is a network of three
`R1
`R1
`resistors that allows for variable
`attenuation while main taining the
`correct match to the antenna. An
`example layout is shown in the
`adjacent figure. For more details
`on T-pad attenuators, please
`see Application Note AN-00150.
`
`RF
`MODULE
`
`R2
`
`GROUND PLANE
`ON LOWER LAYER
`GROUND
`Figure 12: T-Pad Attenuator Example Layout
`
`INPUTTING DIGITAL DATA
`
`The DATA line may be directly connected to virtually any digital peripheral,
`including microcontrollers, encoders, and UARTs. It has an impedance of 200kΩ
`and can be used with any data that transitions from 0V to a 3 to 5V peak
`amplitude within the specified data rate of the module. While it is possible to send
`data at higher rates, the internal filter will cause severe roll off and attenuation.
`Many RF products require a fixed data rate or place tight constraints on the mark
`/ space ratio of the data being sent. The HP3 transmitter architecture eliminates
`such considerations and allows virtually any signal, including PWM, Manchester,
`and NRZ data, to be sent at rates from 100bps to 56kbps.
`The HP3 does not encode or packetize the data in any manner. This
`transparency gives the designer great freedom in software and protocol
`development. A designer may also find creative ways to utilize the ability of the
`transmitter to accept both digital and analog signals. For example, an application
`might transmit voice, then send out a digital control command. Such mixed mode
`systems can greatly enhance the function and versatility of many products.
`INPUTTING ANALOG SIGNALS
`Analog signals from 50Hz to 28kHz may be connected directly to the
`transmitter’s DATA line. The HP3 is a single supply device and, as such, is not
`capable of operating in the negative voltage range. Analog sources should be
`within 0 to 5VP-P and should, in most cases, be AC-coupled into the DATA line
`to achieve the best performance. The size of the coupling capacitor should be
`large enough to ensure the passage of all desired frequencies and small enough
`to allow the start-up time desired. Since the modulation voltage applied to the
`DATA line determines the carrier deviation, distortion can occur if the DATA line
`is over-driven. The actual level of the input waveform should be adjusted to
`achieve optimum in-circuit results for your application.
`The HP3 is capable of providing audio quality comparable to a radio or intercom.
`In applications where higher quality audio is required, a compandor may be
`employed to increase dynamic range and reduce noise. If true high-fidelity audio
`is required, the HP3 is probably not the best choice, as it is optimized for data.
`
`Page 8
`
`TIMING CONSIDERATIONS
`Timing plays a key role in link reliability, especially when the modules are being
`rapidly turned on and off or hopping channels. Unlike a wire, allowance must be
`made for the programming and settling times of both the transmitter and
`receiver, or portions of the signal will be lost. There are two major timing
`considerations the engineer must consider when designing with the HP3 Series
`transmitter. These are shown in the table below. The stated timing parameters
`assume a stable supply of 2.8 volts or greater. They do not include the charging
`times of external capacitance on the module’s supply lines, the overhead of
`external software execution, or power supply rise times.
`Parameter
`Description
`T1
`Transmitter turn-on time
`T2
`Channel change time (time to valid data)
`
`Max.
`10.0mS
`1.5mS
`
`T1 is the maximum time required for the transmitter to power-up and lock on-
`channel. This time is measured from the application of VCC to the CTS line
`transitioning high.
`T2 is the worst-case time needed for a powered-up module to switch between
`channels after a valid channel selection. This time does not include external
`overhead for loading a desired channel in Serial Channel Select Mode.
`Normally, the transmitter will be turned off after each transmission. This is
`courteous use of the airwaves and reduces power consumption. The transmitter
`may be shut down by switching its supply or the PDN line. When the transmitter
`is again powered up, allowance must be made for the requirements above.
`In many cases, the transmitter will lock more quickly than the times indicated.
`When turn-around time or power consumption are critical, the CTS line can be
`monitored so data may be sent immediately upon transmitter readiness.
`TRANSMITTING DATA
`Once an RF link has been established, the challenge becomes how to effectively
`transfer data across it. While a properly designed RF link provides reliable data
`transfer under most conditions, there are still distinct differences from a wired link
`that must be addressed. Since the modules do not incorporate internal encoding
`or decoding, the user has tremendous flexibility in how data is handled.
`It is important to separate the types of transmissions that are technically possible
`from those that are legally allowed in the country of operation. Application Notes
`AN-00126, AN-00140 and Part 15, Section 249 of the FCC rules should be
`reviewed for details on acceptable transmission content in the U.S.
`If you want to transfer simple control or status signals (such as button presses)
`and your product does not have a microprocessor or you wish to avoid protocol
`development, consider using an encoder / decoder IC set. These chips are
`available from several manufacturers, including Linx. They take care of all
`encoding and decoding functions and provide a number of data lines to which
`switches can be directly connected. Address bits are usually provided for
`security and to allow the addressing of multiple receivers independently. These
`ICs are an excellent way to bring basic remote control products to market quickly
`and inexpensively. It is also a simple task to interface with inexpensive
`microprocessors or one of many IR, remote control, DTMF, or modem ICs.
`
`Page 9
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 5
`
`

`
`CHANNEL SELECTION
`Parallel Selection
`Frequency
`Channel
`CS0
`CS1
`CS2
`903.37
`0
`0
`0
`0
`All HP3 transmitter models feature
`906.37
`1
`1
`0
`0
`eight parallel selectable channels.
`907.87
`2
`0
`1
`0
`909.37
`3
`1
`1
`0
`Parallel Mode
`is selected by
`912.37
`4
`0
`0
`1
`grounding the MODE line. In this
`915.37
`5
`1
`0
`1
`mode, channel selection is deter -
`919.87
`6
`0
`1
`1
`1
`1
`1
`7
`921.37
`mined by the logic states of pins CS0,
`Table 2: Parallel Channel Selection Table
`CS1, and CS2, as shown in the table.
`A ‘0’ represents ground and a ‘1’ the supply. The on-board microprocessor
`performs all PLL loading functions, eliminating external programming and
`allowing channel selection via DIP switches or a product’s processor.
`Serial Selection
`In addition to the Parallel Mode, PS versions of the HP3 also feature 100 serially
`selectable channels. The Serial Mode is entered when the MODE line is left open
`or held high. In this condition, CS1 and CS2 become a synchronous serial port,
`with CS1 serving as the clock line and CS2 as the data line. The module is easily
`programmed by sending and latching the binary number (0 to 100) of the desired
`channel (see the adjacent Serial Channel Selection Table). With no additional
`effort, the module’s microprocessor handles the complex PLL loading functions.
`The Serial Mode
`is
`straight forward; however,
`minimum timings and bit
`order must be followed.
`Loading
`is
`initiated by
`taking the clock line high
`and the data line low as
`shown.
`The
`eight-bit
`channel number is then
`clocked-in one bit at a
`time, with the LSB first.
`(T0) Time between packets or prior to data startup ................................1mS min.
`(T1) Data-LO / Clock-HI to Data-LO / Clock-LO .......................................25µS min.
`(T2) Clock-LO to Clock-HI ...........................................................................5µS min.
`(T3) Clock-HI to Clock-LO ...........................................................................8µS min.
`(T4) Data-HI / Clock-HI .................................................................................5µS min.
`Total Packet Time ......................................................................................157µS min.
`
`Note 2
`
`Note 1
`
`Data
`
`Clock
`
`T0
`1ms
`
`Variable Data
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`T3
`8μs
`T2
`T1
` 5μs
`25μs
`1) Loading begins when clock line is high and data line is taken low
`2) Ensure that edge is fully risen prior to high-clock transition
`3) Both lines high triggers automatic latch
`
`Note 3
`
`T4
`5μs
`
`SERIAL CHANNEL SELECTION TABLE
`RX LO
`CHANNEL TX FREQUENCY
`RX LO
`CHANNEL
`TX FREQUENCY
`880.67
`0
`902.62
`867.92
`51
`915.37
`880.92
`1
`902.87
`868.17
`52
`915.62
`881.17
`2
`903.12
`868.42
`53
`915.87
`881.42
`3
`903.37
`868.67
`54
`916.12
`881.67
`4
`903.62
`868.92
`55
`916.37
`881.92
`5
`903.87
`869.17
`56
`916.62
`882.17
`6
`904.12
`869.42
`57
`916.87
`882.42
`7
`904.37
`869.67
`58
`917.12
`882.67
`8
`904.62
`869.92
`59
`917.37
`882.92
`9
`904.87
`870.17
`60
`917.62
`883.17
`10
`905.12
`870.42
`61
`917.87
`883.42
`11
`905.37
`870.67
`62
`918.12
`883.67
`12
`905.62
`870.92
`63
`918.37
`883.92
`13
`905.87
`871.17
`64
`918.62
`884.17
`14
`906.12
`871.42
`65
`918.87
`884.42
`15
`906.37
`871.67
`66
`919.12
`884.67
`16
`906.62
`871.92
`67
`919.37
`884.92
`17
`906.87
`872.17
`68
`919.62
`885.17
`18
`907.12
`872.42
`69
`919.87
`885.42
`19
`907.37
`872.67
`70
`920.12
`885.67
`20
`907.62
`872.92
`71
`920.37
`885.92
`21
`907.87
`873.17
`72
`920.62
`886.17
`22
`908.12
`873.42
`73
`920.87
`886.42
`23
`908.37
`873.67
`74
`921.12
`886.67
`24
`908.62
`873.92
`75
`921.37
`886.92
`25
`908.87
`874.17
`76
`921.62
`887.17
`26
`909.12
`874.42
`77
`921.87
`887.42
`27
`909.37
`874.67
`78
`922.12
`887.67
`28
`909.62
`874.92
`79
`922.37
`887.92
`29
`909.87
`875.17
`80
`922.62
`888.17
`30
`910.12
`875.42
`81
`922.87
`888.42
`31
`910.37
`875.67
`82
`923.12
`888.67
`32
`910.62
`875.92
`83
`923.37
`888.92
`33
`910.87
`876.17
`84
`923.62
`889.17
`34
`911.12
`876.42
`85
`923.87
`889.42
`35
`911.37
`876.67
`86
`924.12
`889.67
`36
`911.62
`876.92
`87
`924.37
`889.92
`37
`911.87
`877.17
`88
`924.62
`890.17
`38
`912.12
`877.42
`89
`924.87
`890.42
`39
`912.37
`877.67
`90
`925.12
`890.67
`40
`912.62
`877.92
`91
`925.37
`890.92
`41
`912.87
`878.17
`92
`925.62
`891.17
`42
`913.12
`878.42
`93
`925.87
`891.42
`43
`913.37
`878.67
`94
`926.12
`891.67
`44
`913.62
`878.92
`95
`926.37
`891.92
`45
`913.87
`879.17
`96
`926.62
`892.17
`46
`914.12
`879.42
`97
`926.87
`892.42
`47
`914.37
`879.67
`98
`927.12
`892.67
`48
`914.62
`879.92
`99
`927.37
`892.92
`49
`914.87
`880.17
`100
`927.62
`= Also available in Parallel Mode
`50*
`915.12
`880.42
`*See NOTE on previous page.
`
`Figure 13: PLL Serial Data Timing
`
`There is no maximum time for this process, only the minimum times that must be
`observed. After the eighth bit, both the clock and data lines should be taken high
`to trigger the automatic data latch. A typical software routine can complete the
`loading sequence in under 200μS. Sample code is available on the Linx website.
`NOTE: When the module is powered up in the Serial Mode, it will default to channel 50 until changed
`by user software. This allows testing apart from external programming and prevents out-of-band
`operation. When programmed properly, the dwell time on this default channel can be less than 200μS.
`Channel 50 is not counted as a usable channel since data errors may occur as transmitters also default
`to channel 50 on startup. If a loading error occurs, such as a channel number >100 or a timing problem,
`the receiver will default to serial channel 0. This is useful for debugging as it verifies serial port activity.
`
`Page 10
`
`Page 11
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 6
`
`

`
`TYPICAL APPLICATIONS
`The figure below shows a typical RS-232 circuit using the HP3 Series transmitter
`and a Maxim MAX232. The MAX232 converts RS-232 compliant signals to a
`serial data stream, which the transmitter then sends. The MODE line is
`grounded, so the channels are selected by the DIP switches.
`
`NC
`NC
`NC
`NC
`GND
`NC
`NC
`NC
`NC
`NC
`NC
`GND
`
`24
`23
`22
`21
`20
`19
`18
`17
`16
`
`14
`13
`
`GND
`ANT
`GND
`NC
`CS0
`CS1 / SS CLOCK
`CS2 / SS DATA
`CTS
`PDN
`VCC
`MODE
`DATA
`TXM-900-HP3
`
`1 2 3 4 5 6 7 8
`
`9
`10
`11
`12
`
`GND
`
`GND
`
`VCC
`
`DB-9
`
`162738495
`
`VCC
`
`+
`
`C2
`4.7uF
`
`GND
`
`GND
`
`GND
`
`16
`15
`14
`13
`12
`11
`0
`
`91
`
`VCC
`GND
`T1OUT
`R1IN
`R1OUT
`T1IN
`T2IN
`R2OUT
`
`C1+
`V+
`C1-
`C2+
`C2-
`V-
`T2OUT
`R2IN
`
`MAX232
`
`12345678
`
`VCC
`
`C1
`4.7uF
`
`+
`
`+
`
`C3
`4.7uF
`
`+
`
`C4
`4.7uF
`
`C5
`4.7uF
`
`+
`
`GND
`
`Figure 14: HP3 Transmitter and MAX232 IC
`
`The figure below shows a circuit using the QS Series USB module. The QS
`converts USB compliant signals from a PC to serial data to be sent to the
`transmitter. The MODE line is high, so the module is in Serial Channel Select
`Mode. The RTS and DTR lines are used to load the channels. Application Note
`AN-00155 shows sample source code that can be adapted to use on a PC. The
`QS Series Data Guide and Application Note AN-00200 discuss the hardware
`and software set-up required for QS Series modules.
`
`NC
`NC
`NC
`NC
`GND
`NC
`NC
`
`NC
`NC
`GND
`
`24
`23
`22
`21
`20
`19
`18
`
`14
`13
`
`GND
`ANT
`GND
`NC
`CS0
`CS1 / SS CLOCK
`CS2 / SS DATA
`CTS
`PDN
`VCC
`MODE
`DATA
`TXM-900-HP3
`
`1 2 3 4 5 6 7
`
`9
`
`11
`12
`
`GND
`
`VCC
`
`GND
`
`16
`15
`14
`13
`12
`11
`0
`
`91
`
`RI
`DCD
`DSR
`DATA_IN
`DATA_OUT
`RTS
`CTS
`DTR
`
`USBDP
`USBDM
`GND
`VCC
`SUSP_IND
`RX_IND
`TX_IND
`485_TX
`SDM-USB-QS
`
`1 2 3 4 5 6 7 8
`
`USB-B CONNECTOR
`
`GND
`
`GND
`
`134
`
`GND
`DAT+
`DAT -
`5V
`
`GSHD
`
`GSHD
`
`56
`
`GND
`
`GND
`
`Figure 15: HP3 Transmitter and Linx QS Series USB Module
`
`The transmitter can also be connected to a microcontroller, which will generate
`the data based on specific actions. A UART may be employed or an I / O line
`may be “bit banged” to send the data to the transmitter. The transmitter may be
`connected directly to the microcontroller without the need for buffering or
`amplification.
`
`PROTOCOL GUIDELINES
`While many RF solutions impose data formatting and balancing requirements,
`Linx RF modules do not encode or packetize the signal content in any manner.
`The received signal will be affected by such factors as noise, edge jitter, and
`interference, but it is not purposefully manipulated or altered by the modules.
`This gives the designer tremendous flexibility for protocol design and interface.
`Despite this transparency and ease of use, it must be recognized that there are
`distinct differences between a wired and a wireless environment. Issues such as
`interference and contention must be understood and allowed for in the design
`process. To learn more about protocol considerations, we suggest you read Linx
`Application Note AN-00160.
`Errors from interference or changing signal conditions can cause corruption of
`the data packet, so it is generally wise to structure the data being sent into small
`packets. This allows errors to be managed without affecting large amounts of
`data. A simple checksum or CRC could be used for basic error detection. Once
`an error is detected, the protocol designer may wish to simply discard the corrupt
`data or implement a more sophisticated scheme to correct it.
`INTERFERENCE CONSIDERATIONS
`The RF spectrum is crowded and the potential for conflict with other unwanted
`sources of RF is very real. While all RF products are at risk from interference, its
`effects can be minimized by better understanding its characteristics.
`Interference may come from internal or external sources. The first step is to
`eliminate interference from noise sources on the board. This means paying
`careful attention to layout, grounding, filtering, and bypassing in order to
`eliminate all radiated and conducted interference paths. For many products, this
`is straightforward; however, products containing components such as switching
`power supplies, motors, crystals, and other potential sources of noise must be
`approached with care. Comparing your own design with a Linx evaluation board
`can help to determine if and at what level design-specific interference is present.
`External interference can manifest itself in a variety of ways. Low-level
`interference will produce noise and hashing on the output and reduce the link’s
`overall range.
`High-level interference is caused by nearby products sharing the same
`frequency or from near-band high-power devices. It can even come from your
`own products if more than one transmitter is active in the same area. It is
`important to remember that only one transmitter at a time can occupy a
`frequency, regardless of the coding of the transmitted signal. This type of
`interference is less common than those mentioned previously, but in severe
`cases it can prevent all useful function of the affected device.
`Although technically it is not interference, multipath is also a factor to be
`understood. Multipath is a term used to refer to the signal cancellation effects
`that occur when RF waves arrive at the receiver in different phase relationships.
`This effect is a particularly significant factor in interior environments where
`objects provide many different signal reflection paths. Multipath cancellation
`results in lowered signal levels at the receiver and, thus, shorter useful distances
`for the link.
`
`Page 12
`
`Page 13
`
`Zepp Labs, Inc.
`ZEPP 1013
`Page 7
`
`

`
`
`
`GROUND PLANEGROUND PLANEGROUND PLANE
`
`
`ON LOWER LAYERON LOWER LAYERON LOWER LAYER
`
`Figure 16: Suggested PCB Layout
`
`BOARD LAYOUT GUIDELINES
`If you are at all familiar with RF devices, you may be concerned about
`specialized board layout requirements. Fortunately, because of the care taken by
`Linx in designing the modules, integrating them is very straightforward. Despite
`this ease of application, it is still necessary to maintain respect for the RF stage
`and exercise appropriate care in layout and application in order to maximize
`performance and ensure reliable operation. The antenna can also be influenced
`by layout choices. Please review this data guide in its entirety prior to beginning
`your design. By adhering to good layout principles and observing some basic
`design rules, you will be on the path to RF success.
`The adjacent figure shows the suggested
`PCB footprint for the module. The actual pad
`dimensions are shown in the Pad Layout
`section of this manual. A ground plane (as
`large as possible) should be placed on a
`lower layer of your PC board opposite the
`module. This ground plane can also be critical
`to the performance of your antenna, which will
`be discussed later. There should not be any
`ground or traces under the module on the
`same layer as the module, just bare PCB.
`During prototyping, the module should be soldered to a properly laid-out circuit
`board. The use of prototyping or “perf” boards will result in horrible performance
`and is strongly discouraged.
`No conductive items should be placed within 0.15in of the module’s top or sides.
`Do not route PCB traces directly under the module. The underside of the module
`has numerous signal-bearing traces and vias that could short or couple to traces
`on the product’s circuit board.
`The module’s ground lines should each have their own via to the ground plane
`and be as short as possible.
`AM / OOK receivers are particularly subject to noise. The module should, as
`much as reasonably possible, be isolated from other components on your PCB,
`especially high-frequency circuitry such as crystal oscilla

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