···· PCI System·
`Architecture
`Third Edition
`
`MINDSHARE, INC.
`
`TOM SHANLEY
`AND
`DoN ANDERSON
`
`RECE\VIO
`
`~JAN- 2 9 1996
`SEAVER SC~EWCi
`
`Addison-Wesley Publishing Company
`Reading, Massachusetts • Menlo Park, California • New York
`Don Mills, Ontario • Wokingham, England • Amsterdam
`Bonn • Syclney • Singapore • Tokyo • Madrid • San Juan
`Paris • Seoul • Milan • Mexico City • Taipei
`
`Page 1 of 235
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`ZTE EXHIBIT 1019
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`Many of the designati,ons used by manufacturers and sellers to distinguish their
`products are claimed as trademarks. Where those designations appear in this b'ook,
`and Addison-Wesley was aware of a trademark claim, the designations have been
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`The authors and publishers have taken care in preparation of this book, but make no
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`Library of Congress Cataloging-in-Publication Data
`
`ISBN: 0-201-40993-3
`
`Copyright© 1995 by MindShare, Inc.
`
`All rights reserved. No part of this publication may be reproduced, stored in a
`retrieval system, or transmitted, in any form or by any means, electronic, mechanical,
`photocopying, recording, or otherwise, without the prior written permission of the .
`publisher. Printed in the United States of America. Published simultaneously in
`Canada.
`
`Sponsoring Editor: Keith Wollman
`Project Manager: Eleanor McCarthy
`Production Coordinator: Lora L. Ryan
`Cover design: Barbara T. Atkinson
`Set in 10 point Palatino by MindShare, Inc.
`
`1 2 3 4 5 6 7 8 9 -MA- 9998979695
`First printing, February 1995
`
`Addison-Wesley books are available for bulk purchases by corporations, institutions,
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`To Nancy and Sheryl, two very understanding ladies.
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`Contenb
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`Contents
`_ Aci<?_o~ledg~eE:tS ····:···-··:·:·~··:·~··~···:····~:·:·······~-·:··-·~····:······~· .. ·~~·!_·~·····:~~ ................ , .. ._., ... xXx: .
`About This Book
`The MindShare Architecture Series ................................................................................ 1
`Organization of This Book ............................................................................................... 2
`Who this Book is For ......................................................................................................... 2
`Prerequisite Knowledge .................................................................................................... 3
`Object Size Designations ......................................................................................... ~ ........ 3
`Documentation Conventions ..... : ...................................................................................... 3
`Hex Notation ................................................................................................................ 3
`Binary Notation ............................................................................................................ 3
`Decimal Notation ......................................................................................................... 4
`Signal Name Representation ....................................................................................... 4
`Identification of Bit Fields (logical groups of bits or signals) ................................... 4
`We Want Your Feedback ................................................................................................... 4
`Bulletin Board ............................................................................................................... 5
`Mailing "Address .......... : ................................................................................................ 5
`
`Part 1: Introduction to the Local Bus Concept
`
`CHAPTER 1: The Problem
`Block-Oriented Devices .· ................................................................................................... 9
`Graphics Interface Performance Requirements ......................................................... 9
`SCSI Performance Requirements ................................................................................ 10
`Network Adapter Performance Requirements ................................................ ; ......... 10
`X-Bus Device Performance Constraints .................................................................... :10
`Expansion Bus Transfer Rate Limitations ...................................................................... 13
`ISA Expansion Bus ....................................................................................................... 13
`EISA Expansion Bus .................................................................. .' .................................. 13
`Micro Channel Architecture Expansion Bus .............................................................. 13
`Teleconferencing Performance Requirements ............................................................... 14
`
`CHAPTER 2: Solutions, VESA and PCI
`Graphics Accelerators: Before Local Bus ........................................................................ 19
`Local Bus Concept .............................................................................................................. 20
`Direct-Connect Approach ............................................ , ........................................ : ...... 20
`Buffered Approach ....................................................................................................... 22
`Workstation Approach ................................................................................................ 24
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`VESA VL Bus Solution ............................................................................................. ..
`Logic Cost .............................................................................................................. ..
`Performance ........................................................................................................... .
`Longevity ......................................................... .................................... , ................. .
`. Teleconferencing Support .................................................................................... .
`Electdcafintegrity :; ....... : ..... ; ............ : ............ , ........................... .................... ~ ... ~ ....... . _
`Add-in Connectors ............................................................................................... .
`Auto-Configuration ............................................................................................. ..
`Revision 2.0 VL Specification ............................................................................. ..
`PCI Bus Solution ....................................................................................................... ..
`Market Niche for PCI and VESA VL ...................................................................... ..
`PC! Device ..................... : ..................................................................................... ..
`Specifications Book is Based on ......................................................................... ..
`Obtaining PCI Bus Specification(s) ..................................................................... .
`
`Part II: Revision 2.1 Essentials
`
`CHAPTER 3: Intro to PCI Bus Operation
`Burst Transfer ............................................................................................................ .
`Initiator, Target and Agents ..................................................................................... .
`Single vs. Multi-Function PCI Devices .................................................................. .
`PCI Bus Clock ........................................................................................................... ..
`Address Phase ................... : ....................................................................................... .
`Claiming the Transaction ........................................................................ ; ............... .
`Data Phase(s) ............................................................................................................ .
`Transaction Duration .............................................................................................. ..
`Transaction Completion and Return of Bus to Idle State ................................. : ..
`"Green" Machine ..................................................................................................... .
`
`CHAPTER 4: Intro to Reflected-Wave Switching
`Each Trace Is a Transmission Line ........................................ ; .............................. ..
`Old Method: Incident-Wave Switching ............................................................... ..
`PCI Method: Reflected-Wave Switching ............................................................. .
`PCI Timing Characteristics .................................................................................... .
`Introduction ...................................................................................................... ..
`CLK Signal ...................... : .................................................................................. .
`Output Timing ................................................................................................... .
`·Input Timing ..................................................................................................... ..
`RST# /REQ64# Timing ......... : ............................................................................ .
`Slower Clock Permits Longer Bus ........................................................................ .
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`Contents
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`CHAPTER 5: The Functional Signal Groups
`Introduction ........................................................................................................................ 53
`System Signals ................................................................................................................... 56
`- '---PCI Clock-Signal-(CLK)~-~~-~~~~-~~-~--~~-~ .......... ~.n .. nmY~n_, .. n ........ n ......... ,56- ---· -
`CLKRUN# Signal ......................................................................................................... 57
`General ................................................................................................ ~ .................. 57
`Reset Signal {RST#) ...................................................................................................... 58
`Address/Data Bus ............................................................................................................... 58
`Preventing Excessive Current Drain ................................................................................ 62
`Transaction Control Signals ............................................................................................. 63
`Arbitration Signals ............................................................................................................ 64
`Interrupt Request Signals ................................................................................................. 65
`Error Reporting Signals ..................................................................................................... 65
`Data Parity Error .......................................................................................................... 65
`System Error ................................................................................................................. 66
`Cache Support (Snoop Result) Signals ........................................................................... 67
`64-bit Extension Signals .................................................................................................... 68
`Resource Locking ............................................................................................................... 69
`JT AGIBoundary Scan Signals ............................................................... _ ........................... 70
`Interrupt Request Lines .................................................................................................... 71
`Sideband Signals ............................... : ............................................................................... 71
`Signal Types ....................................................................................................................... 71
`Central Resource Functions .............................................................................................. 72
`Subtractive Decode ............................................................................................................ 73
`Background ................................................................................................................... 73
`Tuning Subtractive Decoder ........................................................................................ 74
`Reading Timing Diagrams ................................................................................................ 75
`
`CHAPTER 6: PCI Bus Arbitration
`Arbiter ................................................................................................................................. 77
`Arbitration Algorithm ....................................................................................................... 79
`Example ,A-rbiter with Fairness ......................................................................................... 80
`Master Wishes To Perform More Than One Transaction ............................................. 82.
`Hidden Bus Arbitration .................................................................................................... 82
`Bus Parking ......................................................................................................................... 82
`Request/Grant Timing ............................................................ : .......................................... 84
`Example of Arbitration Between Two Masters ............................................................... BS
`Bus Access Latency ............................................................................................................ B9
`Master Latency Timer: Prevents Master From Monopolizing Bus .......................... 91
`Location and Purpose of Master Latency Timer ................................................. 91
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`PCI System Architecture
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`How LTWorks ...................................................................................................... 91
`Is Implementation of LT Register Mandatory? ................................................... 92
`Can LT Value Be Hardwired (read-only)? ........ : ....................... : ................ :.; ..... : 92
`How Does Configuration Software Determine Timeslice To
`Be Allocated To Master? ..................................................................................... 92
`Treatment of Memory Write and Invalidate Command .................................... 92
`Limit on Master's Latency .................................................................................... 93
`Preventing Target From Monopolizing Bus ............................................................... 93
`General ................................................................................................................... 93
`Target Latency on First Data Phase ..................................................................... 95
`Options for Achieving Maximum 16 Clock Latency .......................................... 95
`Different Master Attempts Access To DeviCe With
`Previously-Latched Request ............................................................................... 97
`Special Cycle Monitoring While Processing Request .......................................... 97
`Delayed Request and Delayed Completion ........................................................ 97
`Handling Multiple Data Phases ........................................................................... 97
`Master or Target Abort Handling ........................................................................ 97
`Commands That Can Use Delayed Transactions ............................................... 98
`Delayed Read Prefetch ........................................................................................... 98
`Request Queuing and Ordering Rules ................................................................. 98
`Locking, Delayed Transactions and Posted Writes ............................................ 103
`Fast Back-to-Back Transactions ..................................................................... , .................. 103
`Decision to Implement Fast Back-to-Sack Capability ............. : ................................. 106
`Scenario One: Master Guarantees Lack of Contention ............................................. 106
`How Collision A voided On Signals Driven By Master ...................................... 106
`How Collision A voided On Signals Driven By Target.. ..................................... 107
`How Targets Recognize New Transaction Has Begun ....................................... 108
`Fast Back-to-Back and Master Abort ................................................................... 108
`Scenario Two: Targets Guarantee Lack of Contention .............................................. 110
`State of REQ# and GNT# During RST# .......................................................................... 111
`Pullups On REQ# From Add-In Connectors .................................................................. 112
`Broken Master .................................................................................................................... 112
`
`CHAPTER 7: The Commands
`Introduction ........................................................................................................................ 113
`Interrupt Acknowledge Command .................................................................................. 114
`Introduction .................................. ~ ............................................................................... 114
`Background ................................................................................................ : .................. 114
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence ........................... 115
`PCI Interrupt Acknowledge Transaction ................................................................... 116
`Special Cycle Command ................................................................................................... 119
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`General .......................................................................................................................... 119
`Special Cycle Generation ............................................................................................. 121
`Special Cycle Transaction ................................................................................... , ........ 121
`Single-Data Phase Special Cycle Transaction ...................................................... 121
`Multiple Data Phase Special Cycle Transaction .................................................. 122
`I/0 Read and Write Commands ....................................................................................... 124
`Accessing Memory.: .. : ... : ......... : .. :.:.:.-:-:.: ...... ::.: ...... ; ........... :; .............. .-...... : ........... · ............ :. 124
`Reading Memory ............................................................ , ............................................. 125
`Memory Read Comm.and ..................................................................................... 125
`Memory Read Line Command ................... .-.............. ~ .......................................... 125
`Memory Read Multiple Command ...................................................................... 125
`Writing Memory ...................................... ~ .................................................................... 126
`Memory Write Comm.and .................................................................................... 126
`Memory Write and Invalidate Command ........................................................... 126
`Problem ........................................................................................................... 126
`Description of Memory Write and Invalidate Command ........................... 127
`More Information On Memory Transfers ........................................ _ .......................... 127
`Configuration Read and Write-Commands .................................................................... 128
`Dual-Address Cycle ........................................................................................................... l28
`Reserved Bus Commands ................................................................................................. 128
`
`CHAPTER 8: The Read and Write Transfers
`Some Basic Rules ............................................................................................................... 129
`Parity .................................................................................................................................... 130
`Read Transaction ................................................................................................................ 130
`Description .................................................................................................................... 130
`Treatment of Byte Enables During Read or Write ..................................................... 134
`Byte Enable Settings May Vary from Data Phase to Data Phas.e ....................... 134
`Data Phase with No Byte Enables Asserted ........................................................ 135
`Target with Limited Byte Enable Support.. ......................................................... 136
`Rule for Sampling of Byte Enables ....................................................................... 136
`Ignore Byte Enables During Line Read ................................................................ 136
`Prefetching ............................................................................................................. 137
`Performance During Read Transactions .................................................................... 137
`Write Transaction ............................................................................................................... 139
`Description .................................................................................................................... 139
`Performance During Write Transactions ................................................................... 144
`Posted-Write Buffer ..................................................................................................... 146
`General ................................................................................................................... 146
`Combining .............................................................................................................. 146
`Byte Merging ........ · ................................................................................................. 147
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`PCI System Architecture
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`Collapsing .............................................................................................................. 147
`Cache Line Merging .............................................................................................. 147
`Addressing Sequence During Memory Burst ................................................................ 148
`Linear and Cacheline Wrap Addressing .................................................................... 148
`Target Response to Reservecl _S_etting o~ AD[1 :0] ...................................................... 150
`Do Not Merge Processor 110 Writes into Single Burst.::. ... : ...... ~:.: ... ~ ..... ;; .. ; ......... ;.;-.. .-... -1.50
`PCI I/0 Addressing ............................................................................................................ 150
`General .......................................................................................................................... 150
`Situation Resulting in Target-Abort ............................................................................ 151
`I/0 Address Management .......................................................................................... 153
`When 1/0 Target Doesn't Support Multi-Data Phase Transactions ............ ~ ............... 153
`Address/Data Stepping ..................................................................................................... 154
`Advantages: Diminished Current Drain and Crosstalk ............................................ 154
`Why Targets Don't Latch Address During Stepping Process .................................. 155
`Data Stepping ............................................................................................................... 155
`How Device Indicates Ability to Use Stepping ......................................................... 155
`Designer May Step Address, Data, PAR (and PAR64) and IDSEL.. ........................ 156
`Continuous and Discrete Stepping ............................................................................. 156
`Disadvantages of Stepping .......................................................................................... 157
`Preemption While Stepping in Progress ..................................................................... 157
`Broken Master .............................................................................................................. 158
`Stepping Exatnple ........................................................................................................ 159
`When Not to Use Stepping .................................................................. , ....................... 161
`Who Must Support Stepping? ..................................................................................... 161
`Response to Illegal Behavior ............................................................................................ 161
`
`CHAPTER 9: Premature Transaction Termination
`Introduction ........................................................................................................................ 163
`Master-Initiated Termination ........................................................................................... 163
`Master Preempted ........................................................................................................ l64
`Preemption During Timeslice ............................................................................... 164
`Ti.meslice Expiration Followed by Preemption ................................................... 165
`Master Abort: Target Doesn't Claim Transaction ..................................................... 167
`Introduction ........................................................................................................... 167
`Master Abort on Single Data Phase Transaction ................................................ 167
`Master Abort on Multi-Data Phase Transaction ................................................. 169
`Action Taken by Master in Response to Master Abort ...................................... 171
`General ............................................................................................................ 171
`Special Cycle and Configuration Access ...................................................... 171
`Target-Initiated Termination ...................................................................................... .-..... 171
`STOP# Signal ................................................................................................................ 171
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`Disconnect .. , ..................................................................................... · ............................. 172
`Description ................................... : ......................................................................... 172
`Reasons Target Issues Disconnect.. ...................................................................... 173
`Target Slow to Complete Data Phase ......................................................... , .. 173
`Memory Target Doesn't Understand Addressing Sequence ...................... 173
`··· Transfer Crosses Over Target's Address.Boti:ildary .. : ........ :: ...... : ..... : .......... 173
`Burst Memory Transfer Crosses Cache Line Boundary .............................. 174
`Type "A" Disconnect: Initiator Not Ready When Target Says STOP ............... 174
`Type "B" Disconnect: Initiator Ready When Target Says STOP ....................... 175
`Retry (Type C) Disconnect ........................................................................................... 178
`Description ............................................................................................................. 178
`Reasons Target Issues Retry ................................................................................. 179
`Memory Target Doesn't Understand Addressing Sequence ...................... 179
`Target Very Slow to Complete First Data Phase .......................... ; ............... 179
`Snoop llit on Modified Cache Line ............................................................... 179
`Resource Busy ................................................................................... .............. 180
`Memory Target Locked ............................................. : .................................... 180
`Retry Example ........................................................................................ : .............. 180
`Host Bridge Retry Counter ................... ................................................................ 182
`Target Abort ......................................... : ....................................................................... 182
`Description .......................................................................................................... ... 182
`Reasons Target Issues Target Abort .................................................................... 183
`Broken Target ....................... : .................................................................. -........ 183
`I/0 Addressing Error .................................................................................... 183
`Address Phase Parity Error ........................................................................... 183
`Master's Response to Target Abort ...................................................................... 183
`Target Abort Example ........................................................................................... 183
`How Soon Does Initiator Attempt to Re-Establish Transfer After
`Retry or Disconnect? .................................................................................................. 185
`Target-Initiated Termination Summary ..................................................................... 185
`
`CHAPTER 10: Error Detection and Handling
`Introduction to PCI Parity ................................................................................................. 187
`PERR# Signal. ..................................................................................................................... 189
`Data Parity .......................................................................................................................... 189
`Data Parity Generation and Checking on Read ......................................................