United States Patent £191
`Gulick et al.
`
`II 1111111111111
`
`US005748983A
`[l!J Patent Number:
`[45] Date of Patent:
`
`5,748,983
`May 5, 1998
`
`[54) COMPUTER SYSTEM HAVING A
`DEDICATED MULTIMEDIA ENGINE AND
`MULTIMEDIA MEMORY HAVING
`A.RBITRATION LOGIC WHICH GIUNTS
`MAIN MEMORY ACCESS TO EITHER THE
`CPU OR MULTIMEDIA ENGINE
`
`[75]
`
`Inventors: Dale E. Gulick; Andy Lambredlt;
`Mike Webb; Larry Hewitt, all of
`Austin; Brian Barnes. Round Rock. all
`of Tel{.
`
`[73] Assignee: Advanced Micro Devices, Inc..
`Sunnyvale. Calif.
`
`[21) Appl. No.: 474,S54
`Jun. 7, 1995
`(22] Filed:
`lot. CJ.6
`.................................. .................... G06F 13M
`(51)
`[52) U.S. Cl. .......................... :ml/842; 395/280; 3951800;
`395/853
`(58] Hdd or Search ............................... 327/108; 348113.
`348/8, 15; 369/124; 379190; 395/280, 650,
`440. 518. 507
`
`[56]
`
`Refer.nces Cited
`
`U.S. PATENT DOCUMENTS
`
`4,470,109
`4,549.273
`4 .81J.205
`4.991,169
`5,201,037
`5,325,423
`5,373,493
`5,440,336
`5,450,544
`5,487,167
`5,438,411
`5 .497,373
`
`911934 McNally ................ _ .............. 3951280
`1 0/19&5 Tin .......................................... 3951477
`3/1989 Norminl!ton et al. ·-·-····-·-·· 395/502
`211991 Davis et al . .............................. 370n7
`4/1993 Kobiyama et al. ..................... 3951518
`611994 Lewis ........................................ 379190
`12/1994 Lizuka .................................... 369/124
`8/1995 Buhro et al. .... .... ......... ...... .... ... 343113
`911995 Djxoo et al ............ - .............. 395/507
`111996 Djnallo et al. .......................... 395/650
`1/1996 Lewis ........................ : ................. 348/8
`3/1996 Hulen et al ............................. 37M59
`
`411996 Rossmere et al ................... 3641514 A
`5,508,940
`411996 Obno ......................................... 348/15
`5,512,938
`5/1996 Farrell el al . ........................... 327/108
`5,519,345
`7/1996 Kim ................... ~ ................... 395!280
`5.535,339
`5,574.662 1111996 Wmdrem et al . . - ................ 3641514 R
`5,584,007 1211996 BaD:ud .................................... 395/440
`FOREIGN PATENT DOCUMENTS
`
`0 537 932 A3
`94110641
`
`411993 European Pat. Off ..
`.511994 WlPO .
`
`CYfHER PUBUCATIONS
`PCI Local Bus--PC/ Multimedia Design Guide-Revision
`1.0 -Mar. 29. 1994. 43 pages.
`PrimLlry Etaminer- Thomas C. Lee
`Assistant Examiner-Po C. Huang
`Anomc)l Agmt, or Firm--Conley. Rose & Tayon; Jeffrey C.
`Hood
`
`(57)
`
`ABSTRACT
`
`A computer system optimized for real-time applicatioos
`whicb provides increased perfortiUnce for real-time appli(cid:173)
`cations over current computer architectures. The system
`includes a dedicated muhimedia engiDe coupled directly to
`the main memory which performs real-time operations.
`including audio and video functions. as well as others. The
`multimedia engine includes one or more DSP engiDes which
`couple through one or more 110 channels to respective
`video. audio and communication ports. The multimedia
`engine includes video ports for coupling to a video monitor.
`audio ports for coupling to speakers and one or more
`colllJillllli.cation ports. Multimedia memory is coupled to the
`local memory bus ud sta-es data fa- the multimedia engine.
`The multimedia memory in the multimedia engine com(cid:173)
`prises a portion of the main memory address space. Thus the
`multimedia is used for real-time a- multimedia data and is
`also used by the CPU as overOow memory space.
`
`15 Claims, 6 Dnwing Sheets
`
`102
`
`CPU
`Cliche
`
`110
`
`Main
`Memory
`
`Multimedia
`Engine
`
`112
`
`IZZ
`
`H8RI
`Drive
`
`AT
`Bridge
`
`Video
`Malitor
`
`Page 1 of 13
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`ZTE EXHIBIT 1017
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`U.S. Patent
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`May 5, 1998
`
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`5,748,983
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`U.S .. Patent
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`May 5, 1998
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`Sheet 3 of 6
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`Interface
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`U.S. Patent
`
`May 5, 1998
`
`Sheet 5 of 6
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`Page 6 of 13
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`

`
`U.S. Patent
`
`May 5, 1998
`
`Sheet 6 of 6
`
`5,748,983
`
`Multimedia Address
`Space
`
`I'\
`
`'
`
`Generat
`Address Space
`
`General
`Address Space
`
`Fig. 6
`
`Page 7 of 13
`
`

`
`5,748,983
`
`1
`COMPUTER SYSTEM HAVING A
`DEDICATED MULTIMEDIA ENGINE AND
`MULTIMEDIA MEMORY HAVING
`ARBITRATION WGIC WHICH GRANTS
`MAIN MEMORY ACCESS TO EITHER THE
`CPU OR MULTIMEDIA ENGINE
`
`FIELD OF THE INVENTION
`
`The present invention relat.es to a computer system having
`a dedicated multimedia engine coupled to the main memory
`and a look-aside multimedia memory that shares a common
`address space with the main memory. wherein the multime(cid:173)
`dia engine provides improved performance for real-time
`applications.
`
`2
`erally do not make efficient use of system resources. As an
`example. multimedia hardware cards typically include their
`own memory in addition to system memory. For example.
`video accelerator cards are typi.cally configured with one to
`s four Megabytes of video RAM. Audio cards. video capture
`cards. and other multimedia cards are also generally con(cid:173)
`figured with dedicated on-board memory. This requirement
`of additional memory adds undesirable cost to the :system.
`As multimedia applications become more prevalent. mul-
`IO timedia hardware will correspondingly become essential
`components in personal computer systems. Therefore. an
`improved computer system architecture is desired which is
`optimized for real-time multimedia applications as well as
`for non•.realtime applications.
`
`IS
`
`SUMMARY OF THE INVENTION
`
`DESCRll'TION OF THE RELATED ART
`The present invention comprises a computer system opti-
`Computer architectures generally include a plurality of
`mized for real-time applications which provides iocreased
`~i~!i.-,.i.oterconnected by one or more various buses. For
`performance over current computer architectures. The sys-
`exan;pw. modern computer systems typically include a CPU
`00~\1)pl~ough bridge logic to main memory. The bridge 20 tem includes a dedicated multimedia engine coupled directly
`~s~c ldso typically couples to a high bandwidth local
`to the main memory which perfonns a numbe.r of real-time
`eX:pansioo bus, such as the peripheral component intercon-
`operations. including audio and video functions. as well as
`others. A separate memory is also coupled to the main
`!X%i (PCI) bus or the VESA (Video Electronics Standards
`Association) VL bus. Examples of devices which can be
`memory and to the multimedia eogine and stores multimedia
`coupled to local expansion buses include video accelerator 25 data. The computer system of the present invention provides
`cards. audio cards, telephony cards, SCSI adapters, network
`much greater perfonnance for real-time applications than
`interface cards. etc. An older type expansion bus is generally
`prior systems.
`coupled to the local expansion bus. Examples of such
`The computa- system includes a CPU coupled through
`expansi on buses included the industry standard architecture 30 chip set or bridge logic to ma.in memory. The bridge logic
`(ISA) bus. also referred to as the XI' bus. the extended
`also couples to a local expansion bus such as the PCI bus.
`Various devices may be connerted to the PCI bus. including
`industry standard architecture (EISA) bus, or the mi.crochao-
`oel arcb.itecture (MCA) bus. Various devices may be coupled
`a hard drive. netwock interface card. etc. The bridge logic
`to this second expansion bus. including a fax/modem. sound
`and main memory are also coupled through a local bus to a
`3s dedicated multimedia engine. Thus the :nwltimedia engine is
`card. etc.
`Personal computer systems were originally developed for
`coupled directly to the main system memory, thus allowing
`more effi.cie.nt access to real time data.
`business applications such as word processing and
`In the preferred embodiment. a separate multimedia
`spreadsheets. among others. However, computer systems are
`currently being used to handle a number of real time
`memory and associated arbitration logic are situated! locally
`applications. including multimedia applications having 40 to the multimedia engine. The multimedia memory may
`video and audio components. video capture and playback.
`reside either in the multimedia engine or external to the
`engine. The multimedia memory is configured in a "look-
`telephony applications, and speech recognition and
`synthesis. among others. These real time applications typi-
`aside" fashion. and the arbitration logic arbitrates between
`the CPU and the multimedia engine for multimedia memory
`cally require a large amount of system resources and band-
`width.
`45 access. A DMA engine is preferably included in the arbitra-
`One problem that has arisen is that computer systems
`tion logic which performs high speed burst transfers
`between the main memory and the multimedia memory.
`originally designed for business applications are not well
`suited for the real-time requirements of modem multimedia
`Alternatively, the multimedia engine transfers data from the
`applications. For example. modem personal computer sys-
`main memory to the multimedia memory prior to perform-
`tern arChitectures still presume that the maj<rity of applica- 50 ing operations on the data. In the preferred embodiment. the
`tions executing on the computer system are non real-time
`multimedia memory in the multimedia engine comprises the
`business applications such as word processing and/or
`same address space as the main memory.
`spreadsheet applications. which execute primarily on the
`The multimedia engine includes one or more DSP
`maio CPU. In general. computer systems have not tradition-
`engines. The DSP engines may comprise either dedicated
`ally been designed with multimedia hardware as part of the ss audio or video engines or general purpose DSP engines. The
`system. and thus the system is not optimized for multimedia
`one or more DSP engines couple through one or more J/0
`applications. Rathu, multimedia hardware is typically
`channels to respective 110 ports, including video, audio and
`designed as an add-in card for optional insation in an
`communication ports. The multimedia engine includes video
`ports fo.r coupling to a video monitor. audio ports for
`expansion bus of the computer system.
`In many cases. multimedill! hardware cards situated on an QJ coupliog to an audio DAC or speakers, and one or more
`expansion bus do not have the required access to system
`communication ports.
`memory and other system resources for proper operation.
`The CPU writes video and/or audio commands and data
`For example. a multimedia hardware card situated on the
`to the main memory. and the DMA engine or multimedia
`PCI expansion bus must first arbitrate for control of the PCI
`engine retrieves the commands and data from main memory
`bus before the device can access system memory. In 6S into the multimedia memory. The CPU writes video and/or
`audio commands and data to the main memory instead of
`addition, since the computer system architecture is not
`optimiz.ed for multimedia, multimedia hardware cards gen-
`directly t o the multimedia memocy to minimize CPU access
`
`Page 8 of 13
`
`

`
`5,748,983
`
`BRIEF DESCRIPTION OF TilE DRAWINGS
`
`3
`to the multimedia memory. This ensw-es that the DSP ,engine
`has full access to the multimedia memory. Thus the multi(cid:173)
`media engine is not "locked out" of the multimedia memory
`due to CPU writes.
`In an embodiment including a DMA engine. the CPU and
`the DMA engine arbitrate for the main memory. In an
`embodiment which does not include a DMA engine. the
`CPU and the multimedia engine arbitrate for the main
`memory. In each embodiment. the CPU and the multimedia
`engine both arbitrate for the multimedia memory. In general.
`the CPU has priority access to the main memory. and the
`multimedia engine has priority access to the multimedia
`memory.
`Therefore. the present invention comprises a novel com(cid:173)
`puter system architecture which increases the perfonnance
`of real-time applications. A dedicated multimedia engine
`and a multimedia memory are coupled directly to the main
`memory. The multimedia memory comprises part of the
`main memory address space. and this allows the multimedia
`memory to be used for multimedia data as well as foe
`additional main memory storage.
`
`4
`sbown. the computer system inclcl&s a centtlil proce-<~Sing
`unit (CPU) 102 which is coupled through a CPU local bus
`104 to a bostiPCI/cache bridge or chipset 196. The chipset
`includes arbitration logic 107 as shown. The chipset 1t6 is
`s preferably similar to the Triton chipset available from Intel
`Corporation. including certain arbiter modifications to
`accommodate the multimedia engine of the present inven(cid:173)
`tion. A second level or Ll cache memory (not shown) may
`be coupled to a cache controller in the chipset. as desired.
`10 The bridge or chipset 106 couples through a memory bus
`108 to main memory 110. The main memory 110 is prefer(cid:173)
`ably DRAM (dynamic random access memory) or EDO
`(extended data out) memory. as desired.
`The host/PCIIcache bridge IN and the main memory 110
`15 also couple through the memory bus lt8 to the multimedia
`engine 112 according to the present invention. The multi(cid:173)
`media engine 112 perfonns video and audio processing
`functions. As shown. the multimedia engine 112 preferably
`includes a video port 172 for coupling to a video monitor
`20 114 and an audio port 174 which couples through an audio
`digital to analog converter (audio DAC) 115 to speakers 116.
`The audio DAC 115 includes aD/ A converter. such as those
`available from Crystal Semiconductor of Austin. Tex. The
`multimedia engine 112 may also include a communications
`A better understanding of the present invention can be 25 port.
`obtained when the following detailed description of the
`A multimedia memory 160 is coupled through an arbiter
`block 161 to the local bus 118. The multimedia memory 160
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`preferably comprises DRAM (dynamic random access
`FIG. 1 is a block diagram of a coDJpUter system incb,•<IU!g
`memory) or high speed SRAM. However. the multimedia
`a multimedia engine and a multimedia memory according to 30 memory 16t may comprise any of various types of memo-
`the present invention;
`ries. In the preferred embodiment. the multimedia memory
`FIG. 2 is a block diagram of the multimedia engine of
`160 is mapped to the main memory address space and thus
`FIG. 1·
`comprises a portion of the main memory address space. as
`ot.' alt-~•·
`shown in FIG. 6. Thus the multimedia memory 161 is
`f
`t
`bl k dia
`FIG' 3 ·
`bod.im
`JS a oc
`ailabl to
`gram
`an "' ........ em
`en o
`ul · edia data
`ceded 1o oth
`•
`35 av
`the multimedia engine of FIG. 1·
`.e
`stor:: non-m tim
`as n
`·
`. . er
`words. if the nwn memory llt becomes full and add.i.tlonal
`.
`•
`.
`.
`FIG. 4 IS a block diagram of an ~~e e~ent ~f memory is needed, the CPU 102 can store code and data in
`the .computer. system of FIG. ~ IDcl~g a multimedia
`the multimedia memory 16e. Thus. the multimedia memory
`. 16e is used for real-time or multimedia data and is also used
`engme according to the present mvention;
`FIG. 5 is a block diagram of the multimedia engine of 40 by the CPU 102 as overfiow memory space.
`As descnbed further below. the arbiter block 161 per-
`FIG. 4; and
`FIG. 6 illustrates the memory address space of the main
`forms arbitration between the CPU 102 and the multimedia
`engine 112 for the multimedia memory. The arbiter logic
`memory and the multimedia memory.
`151 preferably includes a DMA (direct memory access)
`DEI' AILED DESCRIPTION OF THE
`45 engine whlcb performs transfers between the main memory
`PREFERRED EMBODIMENT
`110 and the multimedia memory 160.
`The bost/PCllcache bridge or chipset 106 also interfaces
`Incorporation by Reference
`PC! Sy.stem Architecture by Tom Shanley and Don Ander-
`to a peripheral component interconnect (PC!) bus 121. In the
`preferred embodiment, a PCl. local bus is used. However. it
`son and available from Mindshare Press, 2202 Buttercup
`Dr .. Richardson, Tex. 75082 (214) 231-2216. is hereby so is noted that other local buses may be used. such as the
`incorporated by reference in its entirety.
`VESA (Video Electronics Standards Association) VL bus.
`Various types of devices may be connected to the PCI bus
`The Intel Peripherals Handbook. 1994 and 1995 editions.
`120. In the embodiment shown in FIG. 1. a hard disk 122
`available from Intel Corporation. are hereby incorporated by
`reference in their entirety. Also. data sheets on the Intel
`and a network interface controller 124 are coupled to the PCI
`82430FX PCiset chipset. also referred to as the Triton 's bus 120. A SCSI (small computer systems interface) adapta
`lUi may also be coupled to the PCI bus 120. as shown. The
`chipset. are hereby incorporated by reference in their
`entirety, including the 82430 Cache Memory Subsystem
`SCSI adapter 126 may couple to various SCSI devices. such
`as a CD-ROM drive and a tape drive (both not shown). as
`data sheet (Order No. 290482-004). the82420/82430PCiset
`desired. Various other devices may be connected to the PCI
`ISAand EISA bridge data sheet (Order No. 290483004). and
`the Intel 82430FX PCiset Product Brief (Order No. 297559- 60 bus 120. as is well known in the art.
`001). all of which are available from Intel Corporation.
`Expansion bus bridge logic l5t is also preferably coupled
`literature Sales. P.O. Box 764-1. Mt. Prospect. ill. 6005~
`to the PC1 bus 120. The expansion bus bridge logic 1SG
`7641 (1-800-879-4683). and all of which are hereby incor-
`interfaces to an expansion bus 152. The expansion bus 152
`may be any of varying types, including the industry standard
`porated by reference in their entirety.
`Computer System Block Diagram
`65 architecture (ISA) bus, also referred to as the AT bus. the
`Referring now to FIG. 1. a block diagram of a computer
`extended industry standard architecture (EISA) bus. or the
`system according to the present invention is shown. As
`microchannel architecture (MCA) bus. Various devices may
`
`Page 9 of 13
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`

`
`5,748,983
`
`5
`be ooupled to the expansion bus 152. such as expansion bus
`memory or a modem (both not shown). The expan.sioo bus
`bridge logic 150 also couples to a peripheral expansion bus
`(not shown). The peripheral expansion bus is used for
`connecting various peripherals to the computer system,
`including an interrupt system. a real time clock (RTC) and
`timers. a direct memory access (DMA) system. and ROM/
`flash m emory (all not shown). Other peripherals (not
`shown) are preferably connected to the peripheral expansion
`bus. including communications ports. diagnostics ports.
`command/status registers. and non-volatile static random
`access memory (NVSRAM).
`Multimedia Engine Block Diagram
`Referring now to FIG. 2. a more detailed block diagram
`illustrating the multimedia engine 112 is shown. In the
`.(:!'eferred embodiment shown in FlG. 2. the multimedia
`engine 112 includes one DSP engine 210 which preferably
`performs video and audio processing functions. In the pre(cid:173)
`ferred embodiment, the DSP engine 21t is a general purpose
`DSP engine that performs both video and audio processing
`functions as well as other real-time functions. In one
`embodiment. the DSP engine 21t includes one or more
`ROMs (not shown) which store microcode oorresponding to
`video and audio processing il'lStructions or commands. The
`DSP engine 2lt preferably performs video and graphics
`functions such as polygon rendering and texture mapping.
`among others. The DSP engine 2lt preferably performs
`audio functions such as MIDI and wavetable synthesis.
`among oUlers. The DSP engine 210 may also pcl'orm
`communication functions. st~ch as ISDN connectivity or
`modem functionality, as desired.
`Alternate embodiments of the multimedia engine 112
`include two or more DSP engines. The embodiment shown
`in F1G. 3 includes three separate hardware engines • .includ(cid:173)
`ing a video or graphics accelerator engine 212.. 21!11 audio
`engine 214. and a communications or modem engine 216.
`Referring again to flG. 2, the one or more DSP engines
`21t couple to one or more J/0 channels 220. In the preferred
`embodiment shown in FlG. 2 . the multimedia engine 112
`includes three J/0 channels 22tA. 2208, and 22«:. J/0
`channel 220A is preferably a dedicated video channel and
`couples to video port outputs 172 of the multimedia engine
`112. J/0 channel 220B is preferably a dedicated audio
`channel and couples to audio port 174 of the multimedia
`engine 112. J/0 channel 22tC couples to communication 4S
`port 176 of the multimedia engine 112. In one embodiment,
`the video and audio J/0 cbannels 221A and lltB are
`synchro.nized with each other to ensure synchronized audio
`and video during multimedia presentations.
`In the preferred embodiment. the multimedia engine 112
`includes video processing circuitry and/or firmware. includ(cid:173)
`ing a random access memory digital to analog converter
`(RAMDAC). for converting video data into appropriate
`analog signals. preferably red, green and blue (RGB)
`signals. for output directly to video monitor 114. In an
`alternate embodiment. the DSP engine 211 provides digital
`video pixel data through 110 channel llOA to the video port
`172, and a separate RAMDAC and associated logic circuitry
`(not shown) receives the video pixel data from the video port
`172 and generates the appropriate RGB signals to drive the
`display monitor 114.
`In the preferred embodiment. the DSP engine 211 gener(cid:173)
`ates digital audio data that is provided through the 110
`channel 2208 to the audio port 174. A separate audio digital
`to analo,g oonverter (audio DAC) (115 flG. 1) is preferably
`connected to the audio port 174 and converts the digital
`audio data to the appropriate analog signals to drive one or
`
`6
`more speakers 116. Alternatively. the audio DAC functions
`are included within the multimedia engine 112.
`Alternate Embodiment
`FlGS. 4 and S illustrate an alternate embodiment of the
`~ computer system and multimedia engine of FlG. 1. wherein
`the multimedia memory 160 is comprised in the multimedia
`engine 112 instead of external to the multimedia engine 112.
`In this embodiment. the multimedia memory 160 couples
`through the arbiter logic 161 to an internal bus inside the
`10 multimedia engine 112. The arbiter logic 161 preferably
`includes DMA transfer engine 164. as shown.
`Computer System Operation
`Referring again to flG. 1. in the preferred embodiment.
`the maiD memory 110 stores the operating system and
`n applications software as well .as driver software. including
`video drivers and audio drivers. The CPU 102 executes
`applications software and driver software from the main
`memocy lUI and writes any associated video and audio data
`to the main memory 110. The CPU 102then provides high
`20 level instructions directly to the multimedia memory 160
`and/or to the DMA engine 164, or to the multimedia engine
`112.
`In one embodiment. the CPU 102 provides the high level
`instructions directly to the multimedia memory 161. In this
`25 embodiment. the DMA engine 164 accesses the high level
`instructions from a des.ignated address space of the multi(cid:173)
`media memory 160 and uses the instructions to retrieve the
`video or audio data from mailn memory 110 and store the
`data in the multimedia mcmocy 160. In an alternate
`30 embodiment. the CPU 102 provides the high level instruc(cid:173)
`tions directly to one or more buffers or registers in the DMA
`engine 164 instead of to the multimedia memory Hi•. In this
`embodiment. the DMA engine 164 uses the high level
`insuuctions received fro!ll the CPU 1 t2 to transfa the video
`3.S or audio data from main memory no to the multimedia
`memory 16e. It is noted that this embodiment does not
`require lhe DMA engine 164 to access the multimedia
`memory 160 for these instructions.
`In an emOOdiment which i!oe ot include the DMA
`11.2 ~se~ the high
`-40 engine 1~. the multimedia en ·
`level instructions from the mul ·
`· memorJ l&hnd uses
`these high level instructions to transfer the video or audio'Jj
`data from main memocy no to the rnl.lltilm:dill Jnell"o¢¥)' 1~.
`Alternatively. the CPU 102 provides the b.l~1 level instruc(cid:173)
`tions directly to buffers or registers in the multimedia engine
`112. and the multimedia engine 11.2 uses these instructions
`to transfer the data from the main memory llt to the
`multimedia memory 160.
`In the .(:!'eferred embodiment. the high level instructions
`so provided from the CPU ttl a1s o include the actual graphical
`and/or audio commands used by the DSP engine 210 to
`process the video or audio data and to produce the appro(cid:173)
`priate signals at the video and audio ports 172 and 174.
`In one embodiment. the CPU 102 writes video and/or
`ss audio instructions or commands to the main memory lit in
`conjunction with the corresponding video and audio data. In
`this embodiment. the CPU ttl writes only pointer informa(cid:173)
`tion to the multimedia memO£}' 160 or DMA engine 164
`which points to the beginning address in main memory 110
`60 where the data and commands reside. The pointer informa(cid:173)
`tion includes the beginning address of the data. the length or
`number of bytes of the data. a.s well as other infotmation.
`In an embodiment including the DMA engine 1~. the
`DMA engine 164 uses the pointer information to retrieve the
`6S cornmand.s and data from main memory 110 into multimedia
`memory 160. The DMA engine 164 preferably reads the
`pointer iDfonnation from a designated address space in the
`
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`7
`8
`multimedia memory 160. or from its internal buffers. and
`wherein the multimedia memory 160 comprises part of the
`main memory address space. 'Ibus the multimedia memcxy
`retrieves the commands and data from the main memory 110
`160 is available to store non-multimedia data as oeeded.
`to the multimedia memory 160 using high speed burst
`Acccxdingly. the multimedia engine 112 and CPU 10:2 must
`transfers.
`5 also arbitrate for access to the multimedia memory 160. The
`The CPU 102 preferably writes video and/or audio com(cid:173)
`arbiter 1-61 handles the arbitration for the multimedia
`mands amd data to the main memory llt instead of dire<.tly
`memory 160. The multimedia. engine 112 prefaably has
`to the multimedia memory 1~0 in order to minimize CPU
`priority access to the multimedia memory 160.
`accesses to the multimedia memory 160. This ens111es that
`In one embodiment. the multimedia engine 112 simply
`the DSP engine 21t has ful!l access to the multimedia
`writes one or more bits to a register in the arbiter 161 to gain
`memory 160 for real-time processing. Further, the DMA
`control of the multimedia memory 160. and the CPU 102 is
`engine 164 and/or the multimedia engine 112 retrieves
`only granted access to the multimedia memory 160 after a
`commands and data from the main memory 110 only when
`certain starvation period. Alternatively. the local bus 108 is
`necessary. and the DSP engine 210 is not "locked out" of the
`an isochronous bus where each of the CPU 1t2 and the
`multimedia memory 160 due to CPU writes to the multi(cid:173)
`multimedia engine 1U have guaranteed bandwidth and
`media memory 160.
`IS latency on the bus 108 to the IWlin memory 110. Alternative
`In an alternate embodiment. the CPU 1t2 writes video
`arbitration schemes such as a round robin or priority based
`and/or audio data and commands directly to the multimedia
`scheme may be used as desired
`memory 160. In this embodiment, the CPU executes appli(cid:173)
`In an alternate embodiment, the aroiter 161 is not present.
`cations software and driver software from the main memory
`and arbitration fcx both the main memory llt and the
`20 multimedia memory 160 is performed by the aroitration
`lit and writes any associated video and audio data directly
`logic 1t7 in the chipset 106. This embodiment is considered
`to the multimedia memory 160. The driver software also
`less desirable since this dual arbitration to the aroitration
`writes high level commands directly to the multimedia
`logic 107 may impact the ability of the multimedia engine
`memory 160. Thus. the videc drivers write high level
`112 to access commands and data from the multiimedia
`commands to the multimedia memory l(it in a similar
`25 memory 160 while the CPU 102 is accessing main memory
`manner to current PCI-based graphics acceleration cards.
`110.
`In one embodiment, the multimedia memory 160 is sepa-
`Conclusion
`rated into two or more address spaces or buffers. and the
`hil th DSP
`·
`CPU 1..,.
`Therefore, the present invention comprises a novel com-
`addre
`b-..4
`hi
`hiclt ·
`th
`. ..&
`.,.., wntes to one
`ss space or UJ.ler w e e
`engine ::no accesses commaJilds and data from the other
`puter sy~tem arc. te~e w
`. mcreases . e ~uo~~e
`of real-time applications. A dedic.ued multimedia enfS1!1e 1s
`.
`.
`address SJ>a:Ce or buffer. This ensures that the DSP e_ngme 30 coupled directly to the main memory. and the multimedia
`210 ~as u_wnterrupted access. to command~ and data •n the
`engine includes dedicated multimedia memory which is part
`mul~edia ~mory 1~ while also allowmg the CPU 1t2
`of the main memory address space. This allows the multi-
`t? dir~ctly wnte real-time commands and data to the mul-
`media memory to be used for multimedia data as well as for
`timedia memo.ry 160.
`additional main memory storage.
`Once real-time or multimedia data and commands have 3S Although the system and method of the present invention
`been placed in the multimedia memory 16t. either by the
`bas been described in conoection with the preferred
`CPU lt2 or retrieved from main memory 110. the one or
`embodiment. it is not intended to be limited to the specific
`form set forth herein, but on the contrary. it is inteoded to
`more DSP engines 210 in the multimedia engi.oe 112 read
`the commands and data from the multimedia memay 16t
`cover such alternatives. modifications. and equivalents. as
`and perform the necessary graphics and audio pro-cessing 40 can be n:asonably included within the spirit and scqx: of the
`invention as defined by the appended claims.
`functions. to generate the appropriate video and audio signals
`to the video and audio ports 172 and 174. In one
`We claim:
`embodiment. the multimedia memory 16t is partitioned into
`1. A computer system. comprising:
`separate address spaces for commands and data, and the DSP
`a CPU;
`chip set logic coupled to the CPU. wherein the chip set
`engine ~10 retrieves commands from a first address space 4S
`and re~'eves data from a s~nd ~ess space. In the
`logic includes arbitration logic for coupling to a
`embodime~t of ':~G. 3. the multimedia memory 1~ can be
`memory bus, and whaein the chip set logic includes
`~er split. havmg a separate address space for each of the
`expansion bus bridge logic for coupling to an expan-
`engmes 212. 214 and 216.
`sion bus·
`·' b
`·
`t 1
`1 d
`th chi
`Arbitration Logic
`1&£
`" abl - 1 d -~ . 1
`. 107
`·
`an expans1on us coup e to e
`p se og~c;
`'ph
`.
`·
`
`Th e chipset ...., pre.er y mc u es ... .,.tration og1c
`d
`on~ or mcxe pen eral devtces couple to the expanswn
`which determines access to the main memory llO. The
`arbitration logic 187 is coupled to the CPU 102. the main
`us;
`.
`.
`a ~mory bus coupled to the chip set logic;
`memory 110 and the multimedia engine 112. In an embod.i-
`.
`ment including