United States Patent [19J
`Chang et al.
`
`111111111111111111111111111111111111111111111111111111111111111111111111111
`US005442748A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,442,748
`Aug. 15, 1995
`
`[75)
`
`(54] ARCHITECTURE OF OUTPUT SWITCHING
`CIRCUITRY FOR FRAME BUFFER
`Inventors: Shuen C. Chang, San Jose; Hai D. Ho,
`Milpitas; Szu C. Sun, Mountain
`View; Jawii Chen, Cupertino, all of
`Calif.
`[73] Assignees: Sun Microsystems, Inc., Mountain
`View; Samsung Semiconductor Inc.,
`San Jose, both of Calif.
`
`[21] Appl. No.: 145,754
`[22] Filed:
`Oct. 29, 1993
`Int. Cl.6 .............................................. G06F 12/00
`[51]
`[52] u.s. Cl ..................................................... 395/164
`[58] Field of Search ................................ 395/162-166,
`395/250, 275, 425; 345/185-187, 189, 190, 197,
`198, 200
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,747,081 5/1988 Heilveil eta! . ..................... 365/219
`4,947,373 8/1990 Yamaguchi et al. ........... 365/189.04
`5,023,838 6/1991 Herbert .......................... 365/189.08
`5,042,013 8/1992 Sato ................................ 365/230.05
`5,170,157 12/1992 Ishii ..................................... 3401799
`5,249,159 9/1993 Sato ................................ 365/230.65
`5,305,278 4/1994 Inoue .............................. 365/230.03
`
`Primary Examiner-Raymond J. Bayer!
`Assistant Examiner-D. Chauhan
`Attorney, Agent, or Firm-Blakely Sokoloff Taylor &
`Zafman
`
`[57]
`ABSTRACT
`A frame buffe.r including a plurality of .array planes of
`memory cells, row decoding circuitry for selecting
`rows of memory cells in each of the array planes to be
`accessed, column decoding circuitry for selecting col(cid:173)
`umns of memory cells in each of the array planes to be
`accessed, a plurality of bitlines associated with the col(cid:173)
`umns of memory cells of each array plane, each of the
`bitlines connecting to a column of memory cells and
`including a bitline sensing amplifier and a column select
`switch for providing access to the memory cells of that
`column of the array plane, a plurality of output sense
`amplifiers adapted to be connected to a selected number
`of bitlines in an array plane by closing of particular ones
`of the column select switches in the bitbnes, first appa(cid:173)
`ratus for providing output signals from the plurality of
`output sense amplifiers associated with e.ach array plane
`to a data bus, and second apparatus for providing output
`signals from the plurality of output sense amplifiers
`associated with each array plane to a shift register.
`
`20 Claims, 5 Drawing Sheets
`
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`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 5 of 5
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`1
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`5,442,748
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`2
`Each row of pixels is rendered from left to right across
`the display before a next row in sequence is begun,
`When a row is completed, the next row below is begun
`at the left side of the screen. Each row is rendered in
`5 order until the last row at the bottom of the screen is
`completed. This completes one frame. Then the process
`starts over from the beginning with the next frame at
`the upper left comer of the display. As explained above,
`in the typical display sixty individual frames are pres(cid:173)
`ented each second.
`In order to cause each of the pixels stored in the
`frame buffer to be presented at the appropriate position
`on the display, it is necessary to read the data for each
`pixel and transfer that data to the circuitry which con(cid:173)
`trols its rendering on the output · display device. In a
`typical VRAM, the pixel data to be displayed is read a
`row at a time and placed in a shift register at the output
`of the frame buffer. This is accomplished by providing
`one stage of shift register memory for each column of
`the array and writing into the shift register in response
`to a row selection accomplished by the row decode
`signal. The data stored at each cell of the row is ampli(cid:173)
`fied by a bitline sense amplifier for that column and
`transferred to the associated shift register stage. The
`data is then available in the shift register so that it may
`be shifted to the display a pixel at a time in order to fit
`the above-described sequence in which the pixels of a
`frame are displayed on a display device.
`Such a prior art shift register stores an entire row of
`pixel data stored in the array of the fr.ame buffer. Such
`a shift register size has always been necessary because of
`the architectural arrangement by which a stage of the
`output shift register is associated with each column of
`the array. However, to hold this mount of data such a
`shift register must be capable of holding the number of
`pixels in a row multiplied by the largest number of bits
`in a pixel. For thirty-two bit color dispJays having a size
`of 512XS12 pixels, this requires a shift register capable
`of holding 512 X 32 or a total of over sixteen thousand
`bits. A shift register capable of storing this amount of
`data and the attendant circuitry for transferring the data
`from the frame buffer array to the shift register require
`a very substantial amount of die space. Moreover, the
`pixel data stored by such a shift register must further
`amplified before it is furnished to the display control
`circuitry because the bitline sense amplifiers do not
`provide a sufficient amount of amplification. This addi(cid:173)
`tion amplification slows the operation of writing to the
`display.
`It has now been determined that such a large shift
`register is unnecessary for providing sufficient data to
`keep up with the display of pixel data on an output
`display device. It is therefore desirable to provide an
`architecture which allows the size of the shift register to
`be reduced in order to reduce the complexity and ex-
`pense of frame buffer circuitry. It is also desirable to
`provide a more rational arrangement of circuit architec(cid:173)
`ture for transferring data from a frame buffer array to a
`shift register used for furnishing pixel data to an output
`display device.
`
`ARCHITECfURE OF OUTPUT SWITCHING
`CIRCUITRY FOR FRAME BUFFER
`
`10
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to computer systems and, more
`particularly, to apparatus for transferring data from a
`memory array of a frame buffer to a shift register used
`to provide data to an output display device.
`2. History of the Prior Art
`One of the significant problems involved in increas(cid:173)
`ing the operational speed of desktop computers has
`been in finding ways to increase the rate at which infor(cid:173)
`mation is transferred to an output display device. Many 15
`of the various forms of data presentation which are
`presently available require that copious amounts of data
`be transferred. For example, if a computer output dis(cid:173)
`play monitor is operating in a color mode in which
`1024 X 780 pixels are displayed on the screen at once 20
`and the mode is one in which thirty-two bits are used to
`defme each pixel, then a total of over twenty-five mil(cid:173)
`lions bits of information must be transferred to the
`screen with each individual picture (called a "frame")
`that is displayed. Typically, sixty frames are displayed 25
`each second so that over one and one-half billion bits
`must be transferred each second in such a system. This
`requires a very substantial mount of processing power.
`In order to provide such a large amount of informa(cid:173)
`tion to an output display device, computer systems 30
`typically utilize a frame buffer which holds the pixel
`data which is to be displayed on the output display.
`Typically a frame buffer offers a sufficient amount of
`dynamic random access memory (DRAM) to store one
`frame of data to be displayed. The information in the 35
`frame buffer is transferred to the display from the frame
`buffer sixty or more times each second. After (or dur(cid:173)
`ing) each transfer, the pixel data in the frame buffer is
`updated with the new information to be displayed in the
`next frame. Prior art frame buffers capable of holding 40
`the necessary amount of information are quite large and
`complicated.
`In fact, a number of operations which might help to
`increase the speed of operation of a frame buffer and the
`transfer of the data in the frame buffer to the output 45
`display device are not implemented because the mount
`of circuitry required is too extensive and too compli(cid:173)
`cated to be economic.
`For example, transfe.rring the data to and from the
`frame buffer is very slow because of the manner in 50
`which the frame buffers are constructed. Various im(cid:173)
`provements have been made to speed access in frame
`buffers. For example, two-ported video random access
`memory (VRAM) has been substituted for dynamic
`random access memory so that information may be 55
`transferred from the frame buffer to the display at the
`same time other information is being loaded into the
`frame buffer.
`One of the problems which all frame buffers have
`faced is caused by the method by which data is trans- 60
`ferred from the frame buffer to an output display de(cid:173)
`vice. Typically, the display device is a cathode ray tube
`which renders the pixel data stored in the frame buffer
`on a screen in a series of rows. A typical display is
`comprised of 780 horizontal rows, each of which in- 65
`eludes as many as 1024 individual pixels. A frame is
`described on the display by writing individual rows of
`pixels starting at the upper left comer of the display.
`Page 7 of 14
`
`SUMMARY OF THE INVENTION
`It is, therefore, an object of the present invention to
`provide a new design of circuitry for providing output
`from a frame buffer.
`It is another more specific object of the present inven(cid:173)
`tion to provide a new design of output circuitry for
`
`

`
`5,442,748
`
`4
`in any of the operations described herein which form
`part of the present invention; the operations are ma(cid:173)
`chine operations. Useful machines for performing the
`operations of the present invention include general pur(cid:173)
`pose digital computers or other similar devices. In all
`cases the distinction between the method operations in
`operating a computer and the method of computation
`itself should be borne in mind. The present invention
`relates to a method and apparatus for operating a com(cid:173)
`puter in processing electrical or other (e.g. mechanical,
`chemical) physical signals to generate other desired
`physical signals.
`
`3
`switching pixel data from a frame buffer to an output
`display device which output circuitry is reduced in size
`and more capable in operation than prior art arrange(cid:173)
`ments.
`These and other objects of the present invention are 5
`realized in a frame buffer comprising a plurality of array
`planes of memory cells, row decoding circuitry for
`selecting rows of memory cells in each of the array
`planes to be accessed, column decoding circuitry for
`selecting columns of memory cells in each of the array 10
`planes to be accessed, a plurality of bitlines associated
`with the columns of memory cells of each array plane,
`each of the bitlines connecting to a column of memory
`cells and including a bitline sensing !UDPlifier and a
`column select switch for providing access to the mem- 15
`ory cells of that column of the array plane, a plurality of
`output sense amplifiers adapted to be connected to a
`selected number of bitlines in an array plane by closing
`of particular ones of the column select switches in the
`bitlines, a frrst means for providing output signals from 20
`the plurality of output sense amplifiers associated with
`each array plane to a data bus, and a second means for
`providing output signals from the plurality of output
`sense amplifiers associated with each array plane to a
`shift register.
`These and other objects and features of the invention
`will be better understood by reference to the detailed
`description which follows taken together with the
`drawings in which like elements are referred to by like
`designations throughout the several views.
`
`25
`
`D ETAILED DESCRIPTION OF THE
`INVENTION
`Referring now to FIG. 1, there is illustrated a com(cid:173)
`puter system 10. The system 10 includes a central pro(cid:173)
`cessor 11 which carries out the various instructions
`provided to the computer 10 for its operations. The
`central processor 11 is joined to a bus 12 adapted to
`carry information to various components of the system
`10. Also connected to the bus U is main memory 13
`which is typically constructed of dynamic random ac(cid:173)
`cess memory arranged in a manner well known to those
`skilled in the prior art to store information being used
`by the central processor during the period in which
`power is provided to the system 10. A read only mem(cid:173)
`ory 14 which may include various memory devices
`(such as electrically programmable read only memory
`30 devices (EPROM)) well known to those skilled in the
`art which are adapted to retain a memory condition in
`the absence of power to the system 10. The read only
`memory 14 typically stores various basic functions used
`by the processor 11 such as basic input/output and
`startup processes.
`Also connected to the bus 12 are various peripheral
`components such as long term memory 16. The con(cid:173)
`struction and operation of long term memory 16 (typi(cid:173)
`cally an electro-mechanical hard disk drive) are well
`known to those skilled in the art. Also coupled to the
`bus 12 is circuitry such as a frame buffer 17 to which
`data may be written which is to be transferred to an
`output device such as a monitor 18 for display. For the
`purposes of the present explanation, the frame buffer 17
`may be considered to include in addition to various
`memory planes necessary to store information, various
`circuitry well known to those skilled in the art such as
`addressing circuitry, sensing amplifiers, color lookup
`tables (where color indexing is utilized), cligital-to(cid:173)
`analog converter circuitry, and circuittry for controlling
`the scan of iriformation to the output display. In addi-
`tion, the frame buffer 17 may be connected to the bus U
`through circuitry such as graphic accelerating circuit 15
`used for providing fast rendering of graphical data to be
`furnished to the frame buffer 17.
`F IG. 2 illustrates a frame buffer 17 constructed in
`accordance with the· prior art. Typically, such a frame
`buffer 17 includes a dynamic random access memory
`array 20 designed to store information defining pixels
`on the output display. Such an array 20 may be designed
`to provide two ports so that information may be read
`from the array during a period in which information is
`being written to the array. An array 20 so constructed is
`referred to as video random access memory or VRAM.
`Typically, pixel data is transferred to the array 20 in
`a binary pattern. In a typical computer system having a
`thirty-two bit data bus portion of the bus 12, thirty-two
`bits of information may be written to the frame buffer
`
`BRIEF D ESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram illustrating a computer
`system which may include the present invention.
`FIG. 2 is a block diagram illustrating a frame buffer 35
`designed in accordance with the prior art.
`FIG. 3 is a block diagram illustrating another frame
`buffer designed in accordance with the prior art.
`FIG. 4 is a block diagram illustrating an arrangement
`in accordance with the present invention.
`FIG. 5 is a circuit diagram showing a preferred em(cid:173)
`bodiment of the present invention.
`
`40
`
`NOTATION AND NOMENCLAT URE
`Some portions of the detailed descriptions which 45
`follow are presented in terms of symbolic representa(cid:173)
`tions of operations on data bits within a computer mem(cid:173)
`ory. These descriptions and representations are the
`means used by those skilled in the data processing arts
`to most effectively convey the substance of their work 50
`to others skilled in the art. The operations are those
`requiring physical manipulations of physical quantities.
`Usually, though not necessarily, these quantities take
`the form of electrical or magnetic signals capable of
`being stored, transferred, combined, compared, and 55
`otherwise manipulated. It has proven convenient at
`times, principally for reasons of common usage, to refer
`to these signals as bits, values, elements, symbols, char(cid:173)
`acters, terms, numbers, or the like. It should be borne in
`mind, however, that all of these and similar terms are to 60
`be associated with the appropriate physical quantities
`and are merely convenient labels applied to these quan(cid:173)
`tities.
`Further, the manipulations performed are often re(cid:173)
`ferred to in terms, such as adding or comparing, which 65
`are commonly associated with mental operations per(cid:173)
`formed by a human operator. No such capability of a
`human operator is necessary or desirable in most cases
`Page 8 of 14
`
`

`
`5,442,748
`
`5
`memory and appear at thirty-two input pins. This data
`may defme one or more pixels depending upon the
`number of bits required to define a pixel in the particular
`mode of operation. This pixel data is transferred to
`memory addresses within the array 20 from which it 5
`may later be retrieved for display. The positions to
`which the pixel data is transferred within the array are
`designated by addresses transferred to the array on an
`address bus.
`Typically, the pixel data is transferred to the frame 10
`buffer on the data bus portion of the bus 12, and the
`address for that data is transferred on the address bus
`portion of the bus 12. The address includes a row ad(cid:173)
`dress portion and a column address portion. These por(cid:173)
`tions of the address are decoded by row and column 15
`address decoding circuits 22 and 23, respectively. The
`selected row and column identify a specific memory
`cell so that a bit of data may be written to that selected
`position. If data defining an individual pixel is more than
`one bit (four, eight, sixteen, or thirty-two bits of color 20
`data), then the address typically identifies a plurality of
`positions within the array 20 (often in individual planes
`of the array) in which the bits defming one or more
`pixels are to be stored. Data stored in the frame buffer
`17 may be read from the array 20 on the data bus by 25
`addressing the appropriate pixel position using the row
`and column addresses of the memory cells in the array
`and providing a read command. Such data may then be
`utilized within the computer system of which the frame
`buffer 17 is a part in accordance with instructions sent 30
`by, for example, a central processing unit. As may be
`seen, both writing to and reading from the frame buffer
`17 require that the memory positions of the array be
`addressed.
`Although data may be read from the array on the 35
`data bus, it is typical that the largest amount of informa(cid:173)
`tion transferred from the array is pixel data transferred
`to an output display device such as the device 18 illus(cid:173)
`trated in FIG. 1. And although information being writ(cid:173)
`ten to the array 20 of the frame buffer 17 tends to 40
`change in a somewhat varied manner because of the
`way data is furnished to a computer, data is typically
`being constantly transferred from the array 20 of the
`frame buffer 17 to the display in an orderly, row by row
`fashion. In order to allow pixel data to be written to the 45
`array while information is constantly being written to
`the output display device, a second output port apart
`from the system bus is used. This second output port
`includes a large shift register 25 having an individual
`shift register stage associated with each column of the 50
`array. Thus, a typical shift register 25 for transferring
`data to the display holds one entire row of bits of pixel
`data for each plane of the array 20. To load the shift
`register 25, an address designating a row is transferred
`to the frame buffer on the address bus and decoded. All 55
`of the memory cells in the row of the array addressed
`are read and written in parallel into the shift register 25
`through the bitline sense amplifiers. This data is then
`shifted sequentially, pixel by pixel, out of the shift regis(cid:173)
`ter 25 to the display. Then a next row address in se- 60
`quence is received on the address bus from the unit
`controlling the transfer of the pixel data to the display.
`The pixel data in this next addressed row is read and
`written to the shift register 25 for transfer to the output
`display. This operation continues as long as information 65
`is being displayed. As will be understood, since the pixel
`data being transferred to the output display has been
`transferred from the frame buffer to the shift register in
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`6
`a single access, the operations of the frame buffer may
`be accelerated since new information may be written to
`the frame buffer while pixel data is being sequentially
`transferred from the shift register to the display. This
`also frees the data buses for purposes other than trans(cid:173)
`ferring the pixel data to the output display device 18.
`FIG. 2 illustrates one well known prior art arrange(cid:173)
`ment for providing individual ports for the data bus and
`for the output shift register. In the arrangement illus(cid:173)
`trated, each plane of the array 20 is divided into two
`individual halves. Similarly, the column address decod(cid:173)
`ing circuitry is divided into two halves which are physi(cid:173)
`cally arranged outside of the memory cell portion of the
`array itself in each plane of the array. Each of the halves
`of the column decoding circuitry 23 includes bitline
`sensing amplifiers and switching circuitry for selecting
`the particular addressed columns in each operation
`practiced with respect to the array.
`A series of column decoding switches 27 is positioned
`between the two halves of each plane of the array 20.
`The switches 27 provide the circuitry necessary to de(cid:173)
`code the addresses of the columns of the array which
`are to be transferred to the output shift register 25 for
`transfer to the output display device. In known embodi(cid:173)
`ments, the circuitry 27 is adapted to switch pixel data
`from upper and lower halves of each of the two halves
`of the array 20. This arrangement is utilized in order to
`reduce the power required to read out the memory cells
`and to reduce the size of the circuitry 27. In order to
`accomplish this, a signal is provided to designate each
`of the four areas of the plane of the array from which
`data is being read. Thus one signal reads the upper left
`half of the plane, another reads the lower left half, a
`third reads the upper right half, while a fourth reads the
`lower right half.
`Because each of the two halves of the column decode
`circuits 23 and the circuit 27 are directly adjacent to the
`array halves, it is necessary to provide redundant output
`circuitry for each of these sets of circuits in order to be
`able to build such circuits economically. Such redun(cid:173)
`dant circuits 28 and 29 are illustrated in FIG. 2 to the
`right of the other circuitry of the frame buffer 17. In the
`case of the column decode circuitry, this redundant
`circuitry includes the column address decoding cir(cid:173)
`cuitry, the switches for selecting the columns, and the
`bitline sense amplifiers. The circuitry 27 for transferring
`pixel data to the shift register 25 includes decoding
`circuitry for selecting the proper portion of the row of
`the array to transfer to the shift register 25 and the
`actual switches for accomplishing this operation.
`It will be linderstood by those skilled in the art that
`the redundant circuitry 28 and 29 for both the column
`decode circuitry 23 and the circuitry 27 and the large
`shift register 25 require very substantial areas of the
`frame buffer. These areas are expensive to manufacture
`and large in size. The areas are often so large that the
`completed circuitry· will not easily fit within the re(cid:173)
`stricted areas available in desktop and portable comput(cid:173)
`ers. Typical circuitry used to provide the necessary
`redundancy occupies approximately four percent of the
`total die space used for the frame buffer.
`FIG. 3 is a block diagram of another frame buffer 37
`designed in accordance with the teachings of the prior
`art. In the frame buffer 37 illustrated, the array 40 is
`divided into two halves in each plane as with the ar(cid:173)
`rangement illustrated in FIG. 2. However, the column
`decode circuitry 43 and its associated bitline sense am(cid:173)
`plifiers, decoding circuits, and switches activated by the
`
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`5,442,748
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`8
`7
`size of the array and decreases its cost while providing
`decoding circuitry are placed between the two halves
`40 of the array. Since the center of the array is filled, the
`a shift register of sufficient size to process the pixel data
`at an appropriate rate for the output display. Because of
`circuitry 47 for transferring pixel data to a shift register
`its position at the output of the column sense amplifiers,
`45 is divided into two halves and placed outside the
`memory cells of the array 40. Again, the arrangement of 5 the shift register 58 receives pixel data with the full
`FIG. 3 requires that redundant circuitry be provided for
`amplification provided by the column sense amplifiers
`each of the column decode circuitry 43 and the shift
`and need not be further amplified when furnished to the
`register decoding circuitry 47. Typically, the amount of
`display output circuitry. For this reason, the delay due
`redundant circuitry is the same as the redundant cir-
`to the additional output amplification in prior art cir-
`cuitry needed for the arrangement of FIG. 2.
`10 cuits is eliminated.
`The present invention provides a new arrangement
`FIG. 5 is a circuit diagram showing a preferred em-
`for transferring pixel data from a frame buffer to an
`bodiment of the invention. In FIG. 5, the various ele-
`output shift register.
`ments of the circuitry necessary to accomplish the type
`Referring now to FIG. 4, there is illustrated a block
`of physical layout illustrated in FIG. 4 are shown. How-
`diagram showing an architectural arrangement of a IS ever, the elements of FIG. 5 are not themselves ar-
`ranged as they might be arranged in a specific physical
`frame buffer SO designed in accordance with the present
`invention. The frame buffer SO includes first and second
`arrangement. For example, although each plane of the
`halves 51 of two planes of a memory array. Each of the
`array is typically divided into two halves which are
`halves 51 of each of the planes of the memory array 50
`separately addressed, only a single array of memory
`is accessed by means of addresses furnished on an ad- 20 element is shown in FIG. 5 for each. plane since to in-
`elude both halves would make the circuitry very diffi-
`dress bus to a row decode circuit 52 and to a column
`decode circuit 53. The column decode circuit 53 fur-
`cult to understand.
`FIG. 5 shows a frame buffer 61 with a plurality of
`nishes signals to select particular columns to be ac-
`cessed through the operation of column select gates and
`array planes 62 each having memory cells 63 arranged
`bitline se.nse amplifiers located in an area 55 centrally 25 in row and column fashion. Row decode circuitry ~·
`arranged between the two halves 51 of the array. The
`receives row addresses while column decode circuitry
`65 receives column addresses by which individual mem-
`bitlines run from the area 55 separating the two halves
`51 of the array to a plurality of column sense amplifiers
`ory cells in each plane of the array are accessed. As may
`57. The figure includes a pair of groups of such column
`be seen, the row and column decode circuitry are posi-
`sense amplifiers arranged to sense the output of two 30 tioned alongside the array planes 62. The column de-
`individual planes of the array which are illustrated.
`code circuitry decodes column addresses and uses col-
`From the output of the sense amplifiers, the data may be
`umn select switches 67 to select among the particular
`transferred to an output shift register 58 or to the data
`columns for each access·of the array. As may be seen, a
`series of plane select transmission gates 74 are used to
`bus.
`The output arrangement utilized by the frame buffer 35 select particular planes of the array to be accessed.
`Each switch 67 is joined in a column to a bitline sense
`50 to trausfer pixel data from the memory array to the
`shift register 58 is thus the same circuitry used to trans-
`amplifier 73. The bitline sense amplifier 73 is used to
`fer pixel data from the array to the data bus. Because the
`refresh the memory cells 63 of a selected row of the
`circuitry included in the area 55 provides output signals
`array and to write new data to the memory cells of the
`to both the shift register 58 and to the data bus, it is 40 array.
`Data is furnished to the cells of a selected row from a
`necessary to provide only a single set of redundancy
`circuits to correct imperfections in the manufacture of
`data bus shown as a 32 bit bus in the figure. As the frame
`the array circuitry. This set of circuits 60 is illustrated to
`buffer is optimized for eight bit color pixels, eight input
`conductors are shown connecting from a single one of
`the right of the frame buffer in the figure. Because of
`this reduction in redundancy circuitry, this architecture 45 the conductors of the data bus through eight write driv-
`ers 83 and eight write enable switches 81 to every
`substantially reduces the area required by each plane of
`the frame buffer memory array and reduces the cost
`eighth one of the bitlines of one plane of the array.
`thereof. In a preferred embodiment, the redundancy
`Similar conductors, write drivers, and write enable
`circuitry requires only one-half the die area required by
`switches con