"
`
`scsaaese a Essnesezaaeais *ii;%E§§Si¢“u’
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`
`
`
`
`iPCI System
`Architecture
`
`Third Edition
`
`MINDSHARE, INC.
`
`TOM SHANLEY
`
`_
`AND
`_
`DON ANDERSON
`
`a E C E I V E E
`
`A
`
`YY
`
`sessea §©%E%%€‘;%
`
`Addison-Wesley Publishing Company
`Reading, Massachusetts 0 Menlo Park, California 0 New York
`
`Don Mills, Ontario 0 Wokingham, England 0 Amsterdam
`
`Bonn 0 Sydney 0 Singapore 0 Tokyo 0 Madrid - San Juan
`Paris 0 Seoul 0 Milan 0 Mexico City 0 Taipei
`
`Page 1 of 235
`
`ZTE EXHIBIT 1019
`
`

`
`Many of the designations used by manufacturers and sellers to distinguish their
`products are claimed as trademarks. Where those designations appear in this book,
`and Addison-Wesley was aware of a trademark claim, the designations have been
`printed in initial capital letters or all capital letters.
`book, but make. no I
`The authors and publishers have taken care in preparation of
`expressed or implied warranty of any kind and assume no responsibility for errors or
`omissions. No liability is assumed for incidental or consequential: damages in
`connection with or arising out of the use of the information or programs contained
`herein.
`
`Library of Congress Cataloging-in-Publication Data
`
`ISBN: 0-201-40993-3
`
`Copyright © 1995 by MindShare, Inc.
`All rights reserved. No part of this publication may be reproduced, stored in a
`retrieval .system, or transmitted, in any form or by any means, electronic, mechanical,
`photocopying, recording, or otherwise, without the prior written permission of the .
`publisher. Printed in the United States of America. Published simultaneously in
`Canada.
`'
`
`Sponsoring Editor: Keith Wollman
`Project Manager: Eleanor McCarthy
`Production Coordinator: Lora L. Ryan
`Cover design: Barbara T. Atkinson‘
`Set in 10 point Palatino by MindShare, Inc.
`
`1 2 3 4 5 6 '7 8 9 -MA- 9998979695
`First printing, February 1995
`Addison-Wesley books are available for bulk purchases by corporations, institutions,
`and other organizations. For more information please contact the Corporate,
`Government, and Special Sales Department at (800) 238-9682.
`
`Page 2 of 235
`
`

`
`To Nancy and Sheryl, two very understanding ladies.
`
`Page 3 of 235
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`

`
`Contents
`
`
`‘
`5
`
`Contents
`
`_ Ackr1_onr1edgrr_1e_I_1ts
`....
`......
`.......,....__..._._......._.:...............
`
`
`About This Book
`
`The MindShare Architecture Series ................................................................................ 1
`
`Organization of This Book ............................................................................................. .. 2
`' Who this Book is For ....................................................................................................... ..2
`Prerequisite Knowledge.................................................................................................... 3
`Object Size Designations ....................................................................................... ..'. ........ 3
`Documentation Conventions .... .; .................................................... ._. .............................. .. 3
`Hex Notation .............................................................................................................. .. 3
`
`Binary Notation .......................................................................................................... .. 3
`Decimal Notation ....................................................................................................... .. 4
`
`4
`Signal Name Representation
`Identification of Bit Fields (logical groups of bits or signals) ................................. .. 4
`.
`We Want Your Feedback ................................................................................................. .. 4
`Bulletin Board ............................................................................................................. .. 5
`
`Mailing "Address ......... .; .............................................................................................. .. 5
`
`
`Part I: Introduction to the Local Bus Concept
`
`
`CHAPTER 1: The Problem
`Block-Oriented Devices .'................................................................................................. .. 9
`Graphics Interface Performance Requirements ....................................................... .. 9
`SCSI Performance Requirements ................................................................................ 10
`Network Adapter Performance Requirements ............................................... .; ....... .. 10
`X-Bus Device Performance Constraints ................................................................... 10
`
`Expansion Bus Transfer Rate Limitations .................................................................... .. 13
`ISA Expansion Bus ..................................................................................................... .. 13
`EISA Expansion Bus .................................................................
`................................ .. 13
`Micro Channel Architecture Expansion Bus ............................................................ .. 13
`Teleconferencing Performance Requirements ............................................................. .. 14
`_
`
`E
`
`'
`
`1
`
`v
`
`‘
`
`....................................... .;.... .. 20
`Direct-Connect Approach...........................................
`Buffered Approach..................................................................................................... .. 22
`
`CHAPTER 2: Solutions, VESA and PCI
`Graphics Accelerators: Before Local Bus ...................................................................... .. 19
`‘ Local Bus Concept.............................................................................................................. 20
`i
`Workstation Approach ................................................................................................ 24
`R
`_
`|
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`Page 4 of 235
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`
`
`__
`
`..............................
`VESA VL Bus Solution ...............................................................
`Logic Cost ...............................................,...............................................................
`Performance ...........................................................................................................e
`Longevity ........................................................................................... .=..................
`Teleconferencing Supp ort................................................................................... ..
`' Elect-'rical_Integrity.'...............-...........
`...........
`..........................
`.......
`....
`Add-in Connectors ................................................................................................
`Auto—Configuration...............................................................................................
`Revision 2.0 VL Specification ...............................................................................
`PCI Bus Solution.......................
`....................................L..........................................
`Market Niche for PCI and VESA VL........................................................................
`PCI Device ........................................................................................................... ..
`Specifications Book is Basedon ......................................................................... ..
`Obtaining PCI Bus Specification(s) ......................................................................
`Part II:'Revision 2.1 Essentials
`
`CHAPTER 3: Intro to PCI Bus Operation
`Burst Transfer.............................................................................................................
`Initiator, Target and Agents......................................................................................
`Single vs. Multi-Function PCI Devices ...................................................................
`PCI Bus Clock.............................................................................................................
`Address Phase ...................L........................................................................................
`Claiming the Transaction........................................................................;................
`Data Phasets) .............................................................................................................
`Transaction Duration................................................................................................
`Transaction Completion and Return of Bus to Idle State................................
`"Green" Machine ......................................................................................................
`CHAPTER 4: Intro to Reflected-Wave Switching
`Each Trace Is a Transmission Line ....................................................................... ..
`Old Method: Incident-Wave Switching.................................................................
`PCI Method: Reflected-Wave Switching ..............................................................
`PCI Timing Characteristics .....................................................................................
`Introduction ...................................................................................................... ..
`CLK Signal .................... ..:...................................................................................
`Output Timing.................................................................................................. ..
`‘input Timing .......................................................................................................
`RST#/ REQ64# Timing .........§.............................................................................
`Slower Clo ck Permits Longer Bus .........................................................................
`
` "j—"
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`Page 5 of 235
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`

`
`Contents
`
`
`
`CHAPTER 5: The Functional Signal Groups
`Introduction.... ....................................
`.......................
`.....................................
`
`...... 53
`
`.
`
`................................ .. 56
`......................................
`...............................
`System Signals
`.
`.-PCI. C1ocl¢Signa.1.(CLI.().... ............ .........................ff...._......... .......,......56n ,-_. -
`CLKRUN# Signal ....................................................................................................... .. 57
`General ............................................................................................... .L ................ .. 57
`
`A
`
`.-r
`
`Reset Signal (RST#) .................................................................................................... .. 58
`Addressl’Data Bus.....-....... ....
`..............
`..........................................
`........................ 53
`
`62
`Preventing Excessive Current Drain..........................................................................
`Transaction Control Signals .,........
`...................
`.....................................
`................ .. 63
`Arbitration Signals .. ...............
`...................
`.............................................
`64
`Interrupt Request Signals
`.......
`...............
`..................
`.......................... 65
`...........
`Error Reporting
`....................................................................
`........... .. 65
`Data Parity Error ........................................................................................................ .. 65
`System Error ............................................................................................................... .. 66
`Cache Support (Snoop Result) Signals ..............................................................
`....
`67
`64-bit Extension Signals .........................................
`................................................. .. 68
`Resource Locking .....
`.................................................................................................... .. 69
`]TAGfBoundary Scan Signals ................................
`........................
`......................... .. 70
`Interrupt Request Lines ......
`.........
`.........
`..............
`........................
`........
`71
`Sideband Signals ....
`............. ..‘.............................................................................. .. 71
`Signal Types
`............
`........
`.....
`............................................................................ .. '71
`Central Resource Functions ...............................................................
`..............
`........ .. 72
`Subtractive Decode ................
`.............................
`......
`............................
`..... .. 73
`
`Background ................................................................................................................. .. 73
`Tuning Subtractive Decoder...................................................................................... .. 74
`Reading Timing Diagrams .............................................................................................. .. '75
`
`
`CHAPTER 6: PCI Bus Arbitration
`Arbiter ....
`....
`.........
`.............................................................................................. 77
`
`........ .. 79
`........................................
`Arbitration Algorithm ............................................
`..........................
`............. .. 80
`Example Arbiter with Fairness .................
`................
`Master Wishes To Perform More Than One Transaction ........................................... .. 82
`Hidden Bus Arbitration ..............
`............................................................................. .. 82
`
`Bus Parking......................................................................................................................... 82
`RequestlGrant Timing........................
`.................
`.......................................... 84
`Example of Arbitration Between Two Masters ..........................
`............
`.........
`85
`Bus Access Latency .......................................................................................................... .. 89
`Master Latency Timer: Prevents Master From Monopolizing Bus ........................ .. 91
`Location and Purpose of Master Latency Timer............................................... .. 91
`
`m____*;%_
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`, vii
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`Page 6 of 235
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`- PCI System Architecture
`
`How LT Works .................................................................................................... .. 91
`Is Implementation of LT Register Mandatory? ................................................... 92
`Can LT Value Be Hardwired (read-only)? '..i.....
`..............
`...... .2 ............... .;.'. .... .; 92
`How Does Configuration Software Determine Tirneslice To
`Be Allocated To Master? ................................................................................... .. 92
`Treatment of Memory Write and Invalidate Command .................................. .. 92
`Limit on Master's Latency .................................................................................. .. 93
`Preventing Target From Monopolizing
`93
`General ................................................................................................................. .. 93
`Target Latency on First Data Phase ................................................................... .. 95
`Options for Achieving Maximum 16 Clock Latency ........................................ .. 95
`Different Master Attempts Access To Device With
`Previously—Latched Request ............................................................................. .. 97
`Special Cycle Monitoring While Processing Request .....................
`................ .. 97
`Delayed Request and Delayed Completion ........................................................ 97
`Handling Multiple Data Phases ........................................................................... 97
`Master or Target Abort Handling ...................................................................... .. 97
`Commands That Can Use Delayed Transactions ............................................. .. 98
`Delayed Read Prefetch ........................................................................................ .. 98
`Request Queuing and Ordering Rules ............................................................... .. 98
`Locking, Delayed Transactions and Posted Writes .......................................... .. 103
`Fast Back-to-Back Transactions .................................................................... ., ................ .. 103
`Decision to Implement Fast Back-to-Back Capability ............ ..'............................... .. 106
`Scenario One: Master Guarantees Lack of Contention ........................................... .. 106
`How Collision Avoided On Signals Driven By Master.................................... .. 106
`How Collision Avoided On Signals Driven By Target..................................... .. 107
`How Targets Recognize New Transaction Has
`108
`Fast Back-to-Back and Master Abort ................................................................. .. 108
`Scenario Two: Targets Guarantee Lack of Contention.............................................. 110
`State of REQ# and GNT# During RST# ........................................................................ .. 111
`Pullups On REQ# From Add-In Connectors .................................................................. 112
`Broken Master .................................................................................... ..-. ........................... .. 112
`
`
`CHAPTER 7: The Commands
`Introduction ...................................................................................................................... .. 113
`Interrupt Acknowledge Command................................................................................ .. 114
`Introduction ................................
`.............................................................................. .. 114
`Background............................................................................................... .; .................. 114
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence 115
`PCI Interrupt Acknowledge Transaction ................................................................. .. 116
`Special Cycle Command ................................................................................................... 119
`
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`viii
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`Ii
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`Page 7 of 235
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`General ........................................................................................................................ .. 119
`Special Cycle Generation ........................................................................................... .. 121
`Special Cycle Transaction ..................................................................................., ...... ..121
`Single-Data" Phase Special Cycle Transaction.................................................... .. 121
`Multiple Data Phase Special Cycle Transaction ................................................ .. 122
`I10 Read and Write Commands ..................................................................................... .. 124
`
`124
`...........
`......: .........
`................. ..'.‘ .............
`' Accessing Memory.."....'...I.........:..:.L.;.:..'.....
`Reading Memory ........................................................................................................ .. 125
`Memory Read Command ................................................................................... .. 125
`Memory Read Line Command...................; ............. .'......................................... .. 125
`Memory Read Multiple Command .................................................................... .. 125
`Writing Memory..................................... .; .................................................................. .. 126
`Memory Write Command .................................................................................... 126
`Memory Write and Invalidate Command ...........................................................126
`Problem ......................................................................................................... .. 126
`Description of Memory Write and Invalidate Command ......................... .. 127
`More Information 011 Memory Transfers ......................................
`........................ .. 127
`Configuration Read and Write-Commands .................................................................. .. 128
`Dual-Address Cycle........................................................................................................... 123
`Reserved Bus Commands ............................................................................................... .. 128
`
`
`CHAPTER 8: The Read and Write Transfers
`Some Basic Rules ............................................................................................................. .. 129
`Parity.................................................................................................................................. .. 130
`Read Transaction.............................................................................................................. .. 130
`Description.................................................................................................................... 130
`Treatment of Byte Enables During Read or Write ................................................... .. 134
`Byte Enable Settings May Vary from Data Phase to Data Phase ..................... .. 134
`Data Phase with No Byte Enables Asserted ...................................................... .. 135
`Target with Limited Byte Enable Support........................................................... 136
`Rule for Sampling of Byte Enables ..................................................................... .. 136
`Ignore Byte Enables During Line Read.............................................................. ..136
`Prefetching ........................................................................................................... .. 137
`Performance During Read Transactions .................................................................. .. 137
`Write Transaction...............................................................................................................139
`Description.................................................................................................................. .. 139
`Performance During Write Transactions ................................................................. .. 144
`Posted—Write Buffer ................................................................................................... .. 146
`General ................................................................................................................. .. 146
`Combining............................................................................................................ .. 146
`Byte Merging ...... ..~. .............................................................................................. .. 147
`
`
`
`ix
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`Page 8 of 235
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` _
`
` PCI System Architecture
`Collapsing .............................................................................................................. 147
`Cache Line Merging .............................................................................................. 147
`Addressing Sequence During Memory Burst ................................................................ 148
`Linear and Cacheline Wrap Addressing .................................................................... 148
`Target Response. to Reserved_S_etting on AD[1:0]................................................... 150
`
`Do Not Merge'Processor IIO Writes into Single Burst.If...f.......'.£.‘..;.;....
`PCI IIO Addressing............................................................................................................
`General.......................................................................................................................... 150
`Situation Resulting in Target-Abort............................................................................ 151
`I/0 Address Management .......................................................................................... 153
`When 110 Target Doesn't Support Multi-Data Phase Transactions..........
`................153
`AddressfData Stepping ..................................................................................................... 154
`Advantages: Diminished Current Drain and Crosstalk............................................ 154
`Why Targets Don't Latch Address During Stepping Process .................................. 155
`Data Stepping ............................................................................................................... 155
`How Device lndicates Ability to Use Stepping .........................................................155
`Designer May Step Address, Data, PAR (and PAR64) and IDSEL.......................... 156
`Continuous and Discrete Stepping ............................................................................. 156
`Disadvantages of Stepping.......................................................................................... 157
`Preemption While Stepping in Progress.....................................................................157
`Broken Master .............................................................................................................. 158
`Stepping Example ........................................................................................................ 159
`W’hen Not to Use
`161
`Who Must Support Stepping? ..................................................................................... 161
`Response to Illegal Behavior............................................................................................161
`
`
`Introduction........................................................................................................................ 163
`Master-Initiated Termination........................................................................................... 163
`Master Preempted........................................................................................................ 164
`Preemption During Tirneslice............................................................................... 164
`Timeslice Expiration Followedby Preemption................................................... 165
`Master Abort: Target Doesn't Claim Transaction ..................................................... 167
`Introduction ........................................................................................................... 167
`Master Abort on Single Data Phase Transaction
`167
`Master Abort on Multi-Data Phase
`169
`Action Taken by Master in Response to Master Abort ...................................... 171
`General ............................................................................................................ 171
`Special Cycle and ConfigurationAccess 1'71
`Target-Initiated Termination.....................................................................................
`1'71
`STOP# Signal ................................................................................................................ 1'71
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`Page 9 of 235
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`_
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`'
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`Disconnect";................................................................................................................ .. 172
`Description..................................., ....................................................................... .. 172
`Reasons Target Issues Disconnect...................................................................... ..173
`Target Slow to Complete Data Phase.......................................................
`173
`Memory Target Doesn't Understand Addressing Sequence ...................... 173
`" 'Transfer' Crosses Over Target’s Address'Bour1d'ary..L.'....
`.... .f........ .. 173 I
`Burst Memory Transfer Crosses Cache Line
`174
`Type ”A” Disconnect: Initiator Not Ready When Target Says STOP ............. .. 174
`Type ”B” Disconnect: Initiator Ready When Target Says STOP ..................... .. 175
`Retry (Type C) Disconnect ...............................................................
`....................... .. 178
`Description ........................................................................................................... .. 178
`Reasons Target Issues Retry ............................................................................... .. 179 .
`Memory Target Doesn't Understand Addressing Sequence .............
`....... 179
`Target Very Slow to Complete First Data Phase........................ ..-. ............. .. 179
`Snoop Hit on Modified Cache Line............................................................. ..179
`Resource Busy ............................................................................................... .. 180
`Memory Target Locked ............................................ .1 .................................. .. 180
`Retry Example ...................................................................................... .._............. .. 180
`Host Bridge Retry Counter ................................................................................. .. 182
`Target Abort ........................................ .I ..................................................................... .. 182
`Description ........................................................................................................... .. 182
`Reasons Target Issues Target Abort .................................................................... 183
`Broken Target..................... ..L ................................................................
`...... .. 183
`1/0 Addressing Error .................................................................................. .. 183
`Address Phase Parity Error ......................................................................... .. 183
`Master's Response to Target Abort...................................................................... 183
`Target Abort Example..........................: ................................................................ 183
`How Soon Does Initiator Attempt to Re-Establish Transfer After
`Retry or Disconnect? ................................................................................................ .. 185
`Target-Initiated Tennination Summary ..................................................................... 185
`
`CHAPTER 10: Error Detection and Handling
`Introduction to PCI Parity................................................................................................. 187
`PERR# Signal.................................................................................................................... .. 189
`Data Parity .......................................................................................................................... 189
`Data Parity Generation and Checking on Read ......................................................... 189
`Introduction ......................................................................................................... .. 189
`Example Burst Read ............................................................................................ .. 190
`Data Parity Generation and Checking on Write ........................................................ 193
`Introduction ......................................................................................................... .. 193
`Example Burst Write ........................................................................................... .. 193
`
`$“*“
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`Page 10 of 235
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`
`PCI System Architecture
`
`~
`
`196
`Data Parity
`196
`General
`Parity Error During Read ........................................................................ .;........... 196
`Parity Error During Write ........................................................;......................... .. 197
`_ Data Parity Error Recovery ......................................................................................... 198
`Special Case: Data Parity Error During Special Cycle
`........7..;.......:: ....
`199 "
`Devices Excluded from PERR# Requirement .......................................................... .. 199
`Chipsets ................................................................................................................ .. 200
`Devices That Don't Deal with OS/ Application Program or Data
`200
`SERR# Signal...................................................................................................................... 201
`Address Parity ........................................................................................................