APPENDIX B
`
`APPENDIX B
`
`Page 1 of 7
`
`
`
`ZTE Exhibit 1038
`
`
`
`APPENDIX B
`
`Page 1 of 7
`
`
`
`ZTE Exhibit 1038
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`Claim Construction Chart
`
`"bus"
`
`No constmction necessaty.
`
`"a signal line or set of
`associated signal lines to
`which a number of devices are
`directly connected and over
`which infmmation may be
`"a signal line or a set of
`transfened by only one device
`associated signal lines to
`which a number of devices are at a time"
`coupled and over which
`infmmation may be
`transfened between them"
`
`789: claims 1, 13, 15, 28 Altem ative constm ction:
`459: claims 1-2, 7, 11 , 13
`194: claims 1-2, 9, 11 ,
`16-18, 23
`368: claims 1, 5, 7, 13,
`19-20, 23
`045: claims 1, 4-5, 12, 15
`753: claims 1, 7
`315: claims 1
`164: claims 1, 6, 7
`"memmy bus"
`
`No constmction necessaty.
`
`164: claims 1, 6, 7
`
`Altem ative constm ction:
`
`1.
`
`2.
`
`"a signal line or a set of
`associated signal lines to
`which a number of devices,
`including a memmy, m·e
`coupled and over which
`infmmation may be
`transfened"
`"fast enough to keep up with
`an input data stream"
`
`"in real time"
`
`3.
`
`789: claims 1, 13, 15, 28
`315: claim 1
`164: claims 1, 6
`
`Page 2 of 7
`
`"bus [as constm ed] that
`connects directly with a
`memmy"
`
`Indefinite
`
`In the altem ative:
`
`"fast enough to keep up with
`the input data stream, wherein
`
`1
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`obtaining bus mastership does
`not consume bus cycles"
`
`Other elements affected
`by this te1m:
`
`a. "the bus having a
`sufficient bandwidth to
`enable the decoder to
`access the memmy and
`operate in real time when
`the first device
`simultaneously accesses
`the bus"
`
`789: claim 1
`
`a. "the bus having a
`sufficient bandwidth to
`enable the decoder to
`access the memmy and
`operate fast enough to
`keep up with an input data
`stream when the first
`devices simultaneously
`accesses the bus"
`
`having b.
`"the bus
`b.
`sufficient bandwidth to
`transfer data in real time
`between
`the
`shared
`memmy
`and
`the
`decoder"
`
`"the bus having sufficient
`bandwidth to transfer data
`in fast enough to keep up
`with an input data stream
`between the shared
`memmy and the decoder"
`
`315: claim 1
`
`"arbiter"
`
`"arbitration circuit"
`
`4.
`
`"memmy arbiter"
`
`"arbiter circuit"
`
`"circuitry that uses a pnonty "circuitiy that uses a priority
`scheme to dete1mine which scheme to dete1mine which
`requesting device will gam requesting device will gam
`access"
`direct access"
`
`Page 3 of 7
`
`2
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`789: claims 1, 19
`459: claims 1-3, 7, 9, 11,
`13
`194: claims 1-3, 7, 9, 11,
`16-1 8, 22-23
`368: claims 1, 5, 7, 13,
`17, 19-20,23
`045: claims 1, 4-5, 9, 12,
`15
`753: claims 1, 4, 7-10, 12
`164: claims 1, 8, 12
`
`"control circuit"
`
`No construction necessaty.
`
`5.
`
`464: claims 1, 2, 7-13,
`16-24, 32
`
`a. "directly supplied"
`
`194: claim 15
`368: claim 3
`
`6.
`
`b. "directly supplies"
`
`194: claim 2
`368: claims 2, 14, 21
`045: claims 2, 6, 13
`753: claim 3
`
`a. "supplied without being
`stored in main mem01y for
`pmposes of decoding
`subsequent images"
`
`b. "supplies without being
`stored in main mem01y for
`pmposes of decoding
`subsequent images"
`
`7.
`
`"monolithically
`
`"f01med on a single
`
`Page 4 of 7
`
`"an electJ.·onic contJ.·ol device
`that is separate from the CPU
`or processor"
`
`a. Plain and ordinaty meaning.
`
`Altemative constm ction:
`
`"supplied without intervening
`components"
`
`b. Plain and ordinaty meaning.
`
`Altemative constmction:
`
`"supplies without intervening
`components"
`"f01med within"
`
`3
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`integrated into"
`
`semiconductor chip with"
`
`"integrated into"
`
`789: claims 6, 21 , 23
`194: claim 19
`368: claims 17, 23
`045: claims 9, 15
`753: claim 12
`164: claim 12
`third] No constmction necessaty.
`second,
`" [first,
`onboard memor[y, ies ]"
`
`315 : claims 1 , 8
`
`" [first, second, third] mem01y
`within the decoder"
`
`a. "contiguous"
`
`No constmction necessaty.
`
`a. "adjacent"
`
`b. "non-contiguous"
`
`464: claims 1, 7, 9-10,
`16, 19, 22, 32-36
`a. "coupled"
`
`b. "non-adjacent"
`
`"directly
`a.
`connected"
`
`or
`
`indirectly a. Plain and ordinaty meaning.
`No constmction necessaty.
`
`789: claims 1, 5, 15
`"directly or
`464: claims 1, 8, 10 , 12, b.
`13, 17, 19, 20, 21, 23, connectable"
`33,34,35
`"directly or
`368: claims 1, 7, 13, 19, c.
`c01mecting"
`20
`045: claims 1, 4, 5, 12
`753: claims 1, 7
`
`indirectly b. Plain and ordinaty meaning.
`No constmction necessaty.
`
`indirectly c. Plain and ordinaty meaning.
`No constmction necessaty.
`
`8.
`
`9.
`
`10.
`
`Page 5 of 7
`
`4
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`315: claims 1, 14, 15
`164: claims 1, 8-9, 11
`
`b. "coupleable"
`
`045: claims 1, 4, 12
`753: claim 7
`315: claim 1
`164: claim 1
`
`c. "coupling"
`
`789: claim 1
`194: claims 1, 16-1 7
`
`11.
`
`12.
`
`13.
`
`14.
`
`"simultaneously accesses
`the bus"
`
`[AGREED]
`
`[AGREED]
`
`"accesses the bus at the same
`time"
`
`789: claim 1
`"translate"
`
`464: claims 1, 7, 10, 16,
`19, 22
`"algorithmically
`translate"
`
`464: claims 7, 22
`"display device"
`
`194: claims 1, 3, 7, 11,
`16-17
`
`[AGREED]
`
`[AGREED]
`
`"convert"
`
`[AGREED]
`
`[AGREED]
`
`"conveli usmg at least one
`mathematical operation"
`
`[AGREED]
`
`[AGREED]
`
`"screen and its circuitry"
`
`Page 6 of 7
`
`5
`
`
`
`No.
`
`Term(s)
`
`PUMA's Construction
`
`Defendants' Construction
`
`Court's Construction
`
`368: claims 1, 7, 13-14,
`20-21
`045: claims 1, 4-6, 12-13
`753: claims 1, 7
`"display adapter"
`
`15. 368: claims 2-3
`045: claim 2
`753: claim 3
`
`[AGREED]
`
`[AGREED]
`
`"an adapter
`that processes
`images for a display device"
`
`Page 7 of 7
`
`6
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