980484
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`~~
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`PATENT
`NUMBER'
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`CLASS
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`? II
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`SUBCLASS
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`~· 2.-bt
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`GROUP ART UNIT
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`EXAMINER E 114, I<
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`1'\0-
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`....... 1!!!
`
`FILING FEE
`RECEIVED
`
`ATTORNEY'S
`DOCKET NO.
`
`U.S. DEF».T· of COMMERCE • Patent and Trademark Office-PeT -436L (rev. 7·94)
`
`Assistant Examiner
`
`Total Claims
`4o
`
`Sheets Drwg.
`3
`ISSUE ~ 0 3
`BATCH
`Examiner NUMBER
`
`Print Fig.
`~
`
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited
`by the United States Code Title 35, Sections 122, 181 and 368. Possession outside the U.S.
`Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Form PT0-436A
`(Rev. 8/92}
`
`ZTE Exhibit 1002
`
`Page 1 of 258
`
`

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`Date
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`SYMBOLS
`../ ................................. Rejected
`= ................................. Allowed
`• (Through numberal) Canceled
`+ ................................. Restricted
`· N ................................. Non-elected
`I ................................. Interference
`A ................................. Appeal
`0 ................................. Objected
`
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`Page 3 of 258
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`-
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`AREA
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`~U.S. GOVERNMENT PRINTING OFFICE: 1998-440· 769
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`_,_
`'"'1
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`'
`ORIGINAL .CLASSIFICATION
`SUBCLASS
`
`206
`CROSS REFERENCE(S)
`SUBCLASS
`(ONE SUBCLASS PER BLOCK)
`
`STAPLE
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`APPLICANT'S NAME (PLEASE PRINT)
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`IF REISSUE, ORidtNAL PATENT NUMBER
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`ISSUE CLASSIFICATION ~~~tHVI~UI1Y t'AI
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`PT0270
`(REV. 5 91)
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`Page 4 of 258
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`Sub.
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`•
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`
`BAR CODE LABEL
`
`·11111111111111111111111111111111111111111111111111
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`U.S. PATENT APPLICATION
`
`SERIAL NUMBER
`
`FILING DATE
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`CLASS
`
`GROUP ART UNIT
`
`08/701,890
`
`08/23/96
`
`395
`
`2309
`
`CHRISTOPHER S. LAM, SAN JOSE, CA.
`
`t(cid:173)z
`()
`::i
`a..
`a..
`<(
`
`**CONTINUING DATA*********************
`VERIFIED
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`**FOREIGN/PCT APPLICATIONS************
`VERIFIED
`
`FOREIGN FILING LICENSE GRANTED 10/17/96
`TOTAL
`CLAIMS
`
`INDEPENDENT
`CLAIMS
`
`FILING FEE
`RECEIVED
`
`ATTORNEY DOCKET NO.
`
`STATE OR
`COUNTRY
`
`SHEETS
`DRAWING
`
`CA
`
`3
`
`40
`
`5
`
`$1,346.00
`
`96-S-001
`
`LISA K JORGENSON
`SGS-THOMSON MICROELECTRONICS INC
`1310 ELECTRONICS DRIVE
`CARROLLTON TX 75006
`
`MEMORY SHARING ARCHITECTURE FOR A DECODER IN A COMPUTER SYSTEM
`
`U)
`U)
`w
`a:
`0
`0
`<(
`
`w
`...I
`t:
`t-
`
`I
`This is to certify that annexed hereto is a true copy from the records of the United States
`Patent and Trademark Office of the application whrch is identified above.
`By autho~ity of the
`COMMISSIONER OF PATENTS AND TRADEMARKS
`
`Date
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`Certifying Officer
`
`Page 7 of 258
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`

`
`SEED and BERRY LLP
`6300 Columbia Center
`Seattle, Washington 98104-7092
`Phone (206) 622-4900
`Fax (206) 682-6031
`
`08 ·1bt890 ;._
`
`Express Mail Certificate No.:
`Docket No.:
`Date:
`
`EM330684222US
`96-S-001
`August 23, 1996
`
`BOX PATENT APPLICATION
`ASSIST ANT COMMISSIONER FOR PATENTS
`WASHINGTON DC 20231
`
`Sir:
`
`Inventor:
`
`Transmitted herewith for filing is the patent application of:
`Christopher S. Lam
`MEMORY SHARING ARCHITECTURE FOR A DECODER IN A
`COMPUTER SYSTEM
`
`Enclosed are:
`
`3 sheets of drawings (Figs. 1-4).
`An assignment of the invention to: SGS-Thomson Microelectronics, Inc., a corporation of the State of Delaware.
`A Declaration and Power of Attomey.
`A verified statement to establish small entity status under 37 C.F.R. 1.9 and 37 C.F.R. 1.27.
`A certified copy of Application No. , filed , from which priority is claimed, .
`The filing fee has been calculated as shown below.
`Filed without fee or formal papers.
`
`For:
`
`[X]
`[ X]
`[ X]
`[ J
`[ )
`[ X]
`[ ]
`
`For:
`
`No. Filed
`
`No. Extra
`
`Small Entity
`Rate
`
`Fee
`
`Utility Fee
`
`Total Claims
`
`Independent Claims
`( ) Multiple Dependent
`Claim Presented
`
`ASSIGNMENT
`
`40
`
`5
`
`20
`
`2
`
`$375
`
`xll
`
`X 39
`
`+ 125
`
`+ 40
`
`$
`
`$
`
`$
`
`$
`
`TOTAL $
`
`Other Than A
`Small Enti_t:
`Rate
`
`Fee
`
`$750
`
`$440
`
`$ 156
`
`X 22
`
`X 78
`
`+ 250
`
`$
`
`+ 40
`
`$40
`
`TOTAL $ 1386
`
`or
`or
`
`or
`
`or
`
`or
`
`or
`
`or
`
`or
`
`[ J
`[ X]
`[ X]
`
`Please charge my Deposit Account No. 19-1090 in the amount of$_. A duplicate copy of this sheet is enclosed.
`A check in the amount of$ 1386 is enclosed.
`The Assistant Conunissioner is hereby authorized to charge payment of the following fees associated with this
`conununication or credit any overpayment to Deposit Account No. 19-1090. A duplicate copy of this sheet is enclosed.
`[ X] Any additional filing fees required under 37 C.F.R. 1.16.
`[X] Any patent application processing fees under 37 C.F.R. 1.17.
`
`Rcspectfui!Yr" mi
`SEEr;rf'1m ,.
`·
`
`L;··"
`
`\cjd\3669
`
`Page 8 of 258
`
`

`
`i
`FORM PT0-1 082
`
`\
`
`SEED and BERRY LLP
`6300 Columbia Center
`Seattle, Washington 981 04-7092
`Phone (206) 622-4900
`Fax (206) 682-6031
`
`'_:.:,,(;.·.
`
`09.·_ '701890
`
`Express Mail Certificate No.:
`Docket No.:
`Date:
`
`EM330684222 US
`96-S-001
`August 23, 1996
`
`Sir:
`
`Inventor:
`
`For:
`
`Transmitted herewith for filing is the patent apJ,Iication of:
`Christopher S. Lam
`MEMORY SHARING ARCHITECTURE FOR A DECODER IN A
`COMPUTER SYSTEM
`
`Enclosed are:
`
`3 sheets of drawings (Figs. 1-4).
`An assignment of the invention to: SGS-Thomson Microelectronics, Inc., a corporation of the State of Delaware.
`A Declaration and Power of Attorney.
`A verified statement to establish small entity status under 37 C.F.R. 1.9 and 37 C.F.R. 1.27.
`A certified copy of Application No. , t11ed , from which priority is claimed, .
`The filing fee has been calculated as shown below.
`Filed without fee or formal papers.
`
`[ X]
`[ X]
`[ X]
`{ ]
`[ ]
`[ X]
`[ ]
`
`For:
`
`No. Filed
`
`No. Extrn
`
`Small Entitv
`Rnte
`
`Fee
`
`Utility Fee
`
`Total Claims
`
`Independent Claims
`() Multiple Dependent
`Claim Presented
`
`ASSIGNMENT
`
`40
`
`5
`
`20
`
`2
`
`$375
`
`xll
`
`X 39
`
`+ 125
`
`+ 40
`
`$
`
`$
`
`$
`
`$
`
`TOTAL $
`
`Other Than A
`Small Entit
`Rate
`
`Fee
`
`$750
`
`$440
`
`$ 156
`
`X 22
`
`X 78
`
`+ 250
`
`$
`
`+40
`
`$40
`
`TOTAL s1386
`
`or
`or
`
`or
`
`or
`
`or
`
`or
`
`or
`
`or
`
`[ ]
`[ X]
`[ X]
`
`Please charge my Deposit Account No. 19-1090 in the amount of$_. A duplicate copy of this sheet is enclosed.
`A check in the amount of$ 1386 is enclosed.
`The Assistant Commissioner is hereby authorized to charge payment of the following fees associated with this
`communication or credit any overpayment to Deposit Account No. 19-1090. A duplicate copy of this sheet is enclosed.
`[ X] Any additional tiling fees required under 37 C.F.R. 1.16.
`[ X] Any patent application processing fees under 37 C.P.R. 1.17.
`
`\ojd\3669
`
`Page 9 of 258
`
`

`
`THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`PATENT
`
`Filed
`
`For
`
`Christopher S. Lam
`
`August 23, 1996
`
`MEMORY SHARING ARCHITECTURE FOR A DECODER IN
`A COMPUTER SYSTEM
`
`Docket No.
`
`96-S-001
`
`Date
`
`August 23, 1996
`
`Box Patent Application
`Assistant Commissioner for Patents
`Washington, DC 20231
`
`CERTIFICATE OF MAILING BY "EXPRESS MAIL"
`
`Sir:
`
`I hereby certifY that the enclosures listed below are being deposited with the.
`
`United States Postal Service "EXPRESS MAIL Post Office to Addressee" service under 37
`
`C.F.R. § 1.10, Mailing Label Certificate No. EM330684222US, on August 23, 1996,
`
`addressed to: Box Patent Application, Assistant Commissioner for Patents, Washington, DC
`
`20231.
`
`CJD:kh
`
`Marco Vargas
`
`Enclosures:
`Postcard
`Check
`Form PT0-1082 (+copy)
`Specification, claims, abstract
`Drawings (Figures 1-4)
`Declaration and Power of Attorney
`Form PT0-1595
`Assignment
`
`\cjd\3671 (850063.452)
`
`Page 10 of 258
`
`

`
`EXP
`
`1
`
`Description
`
`MEMORY SHARING ARCHITECTURE FOR A DECODER
`
`IN A COMPUTER SYSTEM
`
`5 ¥ro~e toRe ted A
`lications
`..! ~/ Thi~\~ppli tion relates to pending U.S. Patent Applications entitled:
`"VIDEO AND/OR AlfoiO D COMPRESSION AND/OR COMPRESSION DEVICE
`THAT SHARES A ~tv.IORY TERFACE" (Attorney's Docket No. 96-S-b~Tl),
`lV.ll"'"'""""SSION AND/OR COMPRESSION DEVICE
`
`10
`
`THAT SHARES A MEMOR " (Att ney's Docket No. 96-S-012), and "MPEG
`
`DECODER TO BE USED IN
`
`COMPUTER" (Attorney's Docket No ..
`
`9 5-GR2-041 ), all filed concurrently he with.
`
`15 Technical Field
`
`The present invention relates to the field of electronic systems requiring
`
`blocks of memory, and
`
`is more specifically directed
`
`to systems employing
`
`decompression devices, such as audio and/or video decompression.
`
`20 Background of the Invention
`
`In the past, moving images were transmitted via analog signals, such as
`
`television signals. To improve signal to noise ratio and improve security, while also
`
`potentially providing additional signals over a given channel, moving images are
`
`digitized and transferred digitally. The size of a digital representation of moving images
`
`25
`
`(i.e., video) is dependent on the resolution of the image. If a display device, such as a
`
`CRT, has a resolution of 1024 x 768 picture elements (pels or pixels), where each pixel
`
`can have an 8-bit color value, one image requires approximately 3/4 of a megabyte of
`
`memory. At a minimum, 30 images must be displayed per second, thereby requiring over
`
`22 megabytes of memory per second. A typical 90-minute movie would thus require
`
`30
`
`nearly 120 gigabytes of memory.
`
`Page 11 of 258
`
`

`
`2
`
`As a result of such need for memory to store a typical movie, digitized
`
`video is compressed using various digital compression techniques. One such technique
`
`for compressing video is the Digicypher II system by General Instruments. Such a
`
`system allows for compressed video and audio images to be transmitted over high
`
`5
`
`bandwidth channels such as satellite transmission. Other known techniques for
`
`encoding/decoding video images include the Motion Picture Expert Group (MPEG)
`
`techniques MPEG 1 and MPEG 2. Current encoding/decoding standards for video
`
`telephony include the H.261 and H.263 standards.
`
`Many of the compression/decompression standards employ the known
`
`10
`
`discrete cosine transfer algorithm (DCT). The MPEG 1, MPEG 2, H.261 and H.263
`
`standards are decompression protocols that describe how an encoded bit stream is to be
`
`decoded. As a result, the video can be encoded in any manner, as long as the resulting
`
`bit stream complies with the particular standard.
`
`Once encoded, the images can be decoded and displayed on an electronic
`
`15
`
`system dedicated to displaying video and audio, such as a television or digital video disk
`
`(DVD) player, or on electronic systems where displaying images are just one of the
`
`features of the system, such as a computer. A given electronic system must include an
`
`appropriate decoder to allow it to display digital sequences of images compressed under
`
`one of the above standards, assuming the original video was compressed using an
`
`20
`
`encoder under that standard.
`
`Current computers, such as personal computers, employ graphics or
`
`video accelerator cards that permit the computer to rapidly display static images.
`
`Personal computers are typically unable to decompress and display video images
`
`because the decompression or decoding routines typically require substantial processor
`
`25
`
`overhead. For example, the MPEG 2 standard decodes 720 pixels per line and 576 lines
`
`per frame for a single image, and approximately 30 frames per second. As is known,
`
`each frame is divided into a series of 16 pixel by 16 pixel macroblocks, so that for each
`
`second, the processor must .decode 48,600 macroblocks per second. Consequently, the
`
`time interval between decoding each macroblock is approximately 2.0576 microseconds.
`
`30
`
`If a CPU in the PC is running at 100 megahertz, then only 2,057 clock cycles are
`
`available between decoding of each macroblock. This is an inadequate number of clock
`
`Page 12 of 258
`
`

`
`3
`
`cycles to decode a given macroblock given the complexity of the decoding function
`
`under the MPEG 2 standard.
`
`As a result, chip sets have been developed that employ a dedicated
`
`microcontroller, a MPEG 2 decompression chip, and a large amount (e.g., 2 megabytes)
`
`5 of memory, such as DRAM. Such chip sets can be expensive, particularly since they
`
`require 2 megabytes ofDRAM. Thus, it would be desirable to employ the main memory
`
`of the computer, which typically has over 8 megabytes ofDRAM.
`
`Some applications exist that share the main memory. For example, the
`
`symmetrical multiprocessor environment (SMP) by Intel employs two or more identical
`
`10
`
`processors that each access the same block of main memory. However, each of the
`
`microprocessors employs a memory management unit (MMU) that has an identical .
`
`memory mapping table. Neither microprocessor can permanently allocate a portion of
`
`the main memory. Instead, as soon as one of the microprocessors no longer employs a
`
`portion of the memory, and the address of that memory is removed from its memory
`
`15 map, then the other microprocessor is free to use that portion of memory. Additionally,
`
`the SMP environment requires a specific operating system.
`
`Another known method of sharing main memory IS employed with
`
`graphics accelerators in personal computers. Previously, graphics or video accelerator
`
`cards included on-board memory chips. However, under the Video Electronics
`
`20 Standards Association (VESA), a VESA unified memory architecture (VUMA) standard
`
`has been developed. Under this standard, video accelerators can share main memory
`
`with the computer to thereby eliminate the need for on-board memory for the graphics
`
`accelerator. During boot-up of the computer system employing the video accelerator,
`
`the video accelerator will cause the basic input/output instructions (BIOS) of the
`
`25
`
`computer to reserve a large portion of contiguous memory in the main memory, and
`
`prohibit the operating system or other applications from accessing or employing that
`
`memory.
`
`However, typical operating systems such as Windows 95®, manufactured
`
`by Microsoft Corporation, do not permit large blocks of memory to be permanently
`
`30
`
`allocated for a given application or operation after booting up the computer. Instead,
`
`Windows 95 dynamically allocates memory to an application based on the need of that
`
`Page 13 of 258
`
`

`
`4
`
`application. As soon as the application no longer uses the memory, Windows 95
`
`allocates that memory to another application. Moreover, MPEG 2 decoding requires 2
`
`megabytes of contiguous memory. Windows 95 allocates small blocks of memory
`
`(typically "pages" of 4 kilobytes each) that are scattered throughout the main memory.
`
`5
`
`Summary of the Invention
`
`One solution the inventor has developed would be to initialize the
`
`computer during the boot-up process to reserve a 2 megabyte portion of contiguous
`
`memory, as is performed with video accelerators under the YUMA standard. Such an
`
`10
`
`allocation of memory, however, is awkward, and therefore undesirable by users.
`
`Additionally, such a solution would prohibit "on-the-fly" display of video information on.
`
`the computer. Instead, the computer must be rebooted whenever the computer wishes
`
`to use the 2 megabyte portion for other applications.
`
`The present invention solves problems inherent in the prior art and in the
`
`15
`
`inventor's above solution, and provides additional advantages, by employing a memory
`
`management system that operates with the computer and its operating system (e.g.,
`
`Windows 95) to request and employ approximately 500 4-kilobyte pages of the main
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`memory, some of which are in noncontiguous blocks of pages, to construct a single
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`contiguous 2-megabyte block of memory. The system retains the multiple pages of
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`20 memory, and their page descriptors, so as to lock down these portions of memory and
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`prohibit the operating system or other applications from using them. The memory
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`management system can be employed on a single chip having a direct memory access
`
`(DMA) engine, a microcontroller, a small block of memory (optional), and a video
`
`decoder circuit (e.g., an MPEG 2 decoder circuit).
`
`25
`
`The microcontroller, performing a Windows 95 memory allocation
`
`application, requests the page descriptors for each block of 4-kilobyte pages. Each of
`
`the page descriptors is then stored in the form of a lookup table in the on-chip memory
`
`to form a contiguous block of memory. As a result, the video decoder circuit can
`
`perform operations on what appears to be a 2-megabyte continuous block of main
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`30 memory, where the microcontroller employs the lookup table to translate one of the
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`2-megabyte contiguous addresses to its appropriate page in the main memory. As soon
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`Page 14 of 258
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`5
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`as the video decoding operations are complete, the microcontroller releases the multiple
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`pages of memory back to the computer.
`
`Broadly stated, the present invention embodies a control circuit for use in
`
`a computer system. The computer system is controlled by an operating system and has a
`
`5 main memory. An electronic device is coupled to the processor and the main memory
`
`and is configured to request continuous use of several portions of the main memory
`
`from the operating system. The memory portions can have noncontiguous addresses.
`
`The control circuit is also configured to translate the noncontiguous addresses to
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`contiguous addresses of a block of memory, wherein the control circuit permits access
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`10
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`to the portions of the main memory as the block of memory based on the contiguous
`
`addresses.
`
`Broadly stated,
`
`the present
`
`invention also embodies a memory'
`
`management method for use with the computer system. The memory management
`
`method includes the steps of: (a) requesting continuous use of several portions of the
`
`15 main memory from the operating system, the portions of the main memory having
`
`noncontiguous addresses; (b) receiving requests for access to a block of memory, the
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`block of memory having contiguous addresses; and (c) translating the contiguous
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`addresses to the noncontiguous addresses.
`
`Overall, the present invention is applicable to any application requiring a
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`20
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`large block of contiguous memory, not necessarily video decoding. Other features and
`
`associated advantages of the present invention will become apparent from studying the
`
`following detailed description, together with the accompanying drawings.
`
`25
`
`~·····
`BriefDescription ofthe ~ings
`7
`Figure 1 is a block diagram of a computer system having an MPEG 2
`decoder under the prese · ~o~;.····'
`
`~nven~~"
`Figure 2 ispl'd"6k diagram ofthe MPEG 2 decoder ofFigure 1.
`
`Figure 3 1s a blq,ck diagram of software elements employed by the
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`computer system ofFigure ..
`
`30
`
`Figure 4 is a flowchart of a routine performed by the MPEG 2 decoder of
`
`Figure 1.
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`Page 15 of 258
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`6
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`Detailed Description of the Presently Preferred Embodiment
`
`Referring to Figure 1, a computer system 100 under the present invention
`
`includes a computer 102, such as a conventional personal computer (PC). The
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`5
`
`computer 102 includes a central processing unit (CPU) 104, which can be an X86 based
`
`microprocessor. The CPU 104 communicates with a large block of main memory 106
`
`through a memory controller 108. As will be understood below, the main memory 106
`
`should include at least approximately 4 megabytes of memory (typically random access
`
`memory (RAM)).
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`10
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`A visual display device, such as a CRT 110, displays output produced by
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`the computer 102. A digital video disk (DVD) compact disk-read only memory
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`(CD-ROM) player 112, coupled to the computer 102, plays back video images to the'
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`computer from a DVD CD-ROM disk 113, which can be displayed on the CRT 110.
`
`The DVD CD-ROM disk 113 is a super-density disk that can hold up to 18 gigabytes of
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`15
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`audio, video and other types of data (e.g., menus in various languages, sub-pictures,
`
`graphics, etc.). Specifically, the DVD CD-ROM player 112 retrieves video images that
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`have been compressed under known video compression techniques such as the MPEG 2
`
`technique.
`
`An MPEG 2 decoder 114, coupled to the computer 102, decodes the
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`20
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`compressed video images from the DVD CD-ROM player 112 to reconstruct the
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`original, uncompressed video images so that they can be displayed on the CRT 11 0.
`
`The DVD CD-ROM player 112 can also provide compressed audio sequences which the
`
`MPEG 2 decoder 114 decodes using known audio decompression techniques (e.g.,
`
`Dolby AC-3 ). The computer system 100 of Figure 1 can also contain other peripherals
`
`25
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`and elements, not shown, such as a hard disk drive, tape drive, input devices such as a
`
`keyboard or mouse, etc.
`
`Referring to Figure 2, the MPEG 2 decoder 114 is shown in greater
`
`detail. A microcontroller 120 having a memory management unit 122 (MMU) operates
`
`under a routine described below to decode audio and video from the DVD CD-ROM
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`30
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`player 112. A direct memory access (DMA) engine 124 coupled between the
`
`microcontroller 120 and the computer 102 allows the microcontroller to directly access
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`Page 16 of 258
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`7
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`the main memory 106, without employing the CPU 104. The DMA engine 124 can
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`form part of a video module interface (VMI). The DMA engine 124 and VMiinterfaces
`
`are conventional, and are not described in detail herein for purposes ofbrevity and so as
`
`not to obscure the detailed description of the present invention.
`
`5
`
`A video decoding circuit 126, coupled to the microcontroller 120,
`
`decodes or decompresses the video images stored on the DVD CD-ROM disk 113 in
`
`the DVD CD-ROM player 112. Preferably, the video decoding circuit 126 employs
`
`conventional MPEG 2 decoding techniques. Alternatively, or in addition, the video
`
`decoding circuit 126 can decode video images compressed under the MPEG 1, JPEG,
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`10 H.261, or other known video compression techniques.
`
`In general, the MPEG
`
`compression standard is described in SGS-Thomson Microelectronics, Technical Note,
`
`MPEG Video Overview, April 1992.
`
`An audio decoding circuit 128 similarly decodes audio compressed on
`
`the DVD CD-ROM disk 113 in the DVD CD-ROM player 112. The audio decoding
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`15
`
`circuit 128 preferably employs known audio decoding techniques, such as the Dolby
`
`AC-3 technique. The video decoding circuit 126 and audio decoding circuit 128 are of
`
`conventional construction, and are not described in detail herein for purposes of brevity
`
`and so as not to obscure the detailed description ofthe present invention.
`
`An optional memory 129, coupled to the microcontroller 120, provides
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`20
`
`storage
`
`for a
`
`lookup
`
`table or memory map,
`
`as described below.
`
`The
`
`microcontroller 120, DMA engine 124, video decoding circuit 126, audio decoding
`
`circuit 128, and memory 129 can be monolithically integrated as a single chip 130 for
`
`use with or in the computer system 100.
`
`Referring to Figure 3, the computer 102 preferably operates under the
`
`25
`
`conventional Windows 95 operating system 152. A user interface 154, forming a
`
`high-level part of the Windows 95 operating system 152, provides an interface to a user
`
`of the computer system 100. The Windows 95 operating system 152 provides services
`
`for the user interface 154 and "hooks" for all drivers to permit operation therewith.
`
`Execution process of drivers and other application programs start from the user
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`30
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`interface 154. Upon request by such programs, a first menu appears to the user on the
`
`CRT 110, allowing the user to select menu items to initiate sequences of events
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`Page 17 of 258
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`8
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`performed by the application, such as initiating viewing of a movie stored on the DVD
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`CD-ROM disk 113.
`
`A DVD driver 156 employs the hooks of the operating system 152 and
`
`routes data from the DVD CD-ROM disk 113 to a DVD information file manager 158
`
`5
`
`and video objects manager 159. In general, there are two basic levels of data structures
`
`on the DVD CD-ROM disk 113, a volume information file which keeps track of the
`
`physical locations of lower level data structures, and video objects which contain data
`
`packets for all types of data. Physical locations of data on the DVD CD-ROM disk 113
`
`are provided in terms of sectors, each being 2048 bytes long. The DVD driver 156
`
`10
`
`essentially performs the task of reading data from the DVD CD-ROM disk 113. The·
`
`DVD information file manager 158 provides the DVD driver 156 with a physical disk
`
`location and a length of data. The DVD driver 156, in turn, transfers the requested data
`
`from the DVD CD-ROM disk 113 to a known location in the main memory 106, as
`
`described below.
`
`15
`
`The DVD information file manager 158 reads the volume information file
`
`from the DVD CD-ROM disk 113 to determine the physical locations of video titles,
`
`menu titles for each language, title attributes, etc. that are stored on the disk. In general,
`
`the DVD information file manager 158 controls the playback of video from the DVD
`
`CD-ROM disk 113 by requesting data therefrom through the DVD driver 156, and
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`20
`
`sending the data to the video objects manager 159 for display on the CRT 110. Once a
`
`user makes a selection through the user interface 154, the DVD information file
`
`manager 158 looks up the location of the appropriate video information from the
`
`volume information file. The DVD information file manager 158 continuously reads the
`
`video objects from the DVD CD-ROM disk 113 and sends the objects to the video
`
`25
`
`objects manager 159. The data transfer rate changes according to the bit rate needed for
`
`the display of the particular video images.
`
`In other words, the DVD information file
`
`manager 15 8 is an upper level traffic controller that recognizes the type of data that is
`
`read from the DVD CD-ROM disk 113. Based on the type of data, the DVD
`
`information file manager 158 either processes user input from the user interface 154, or
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`30
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`plays or pauses video and audio from the DVD CD-ROM disk 113.
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`Page 18 of 258
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`9
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`The video objects manager 159 is a lower level traffic controller
`
`responsible for the parsing of different packets of video, and time synchronization for
`
`video and audio "lip synching." Each video object contains video, audio, sub-picture
`
`data, and other data as appropriate. The video and audio packets contain MPEG 2
`
`5
`
`elementary video stream and system information, i.e., presentation time stamps,
`
`scrambling control, clock data, etc., as is known in the MPEG 2 standard. The video
`
`objects manager 159 parses the packets and provides appropriate synchronization. The
`
`video objects manager 159 routes the video packets to a video driver 160, and routes
`
`the audio packets to an audio driver 162. In sum, the video objects manager 159 is a
`
`10
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`system coordinator. As long as the video objects manager 159 obtains data from the
`
`DVD driver 156, it routes the data to the appropriate video and audio drivers 160
`
`and 162.
`
`The video driver 160 decodes the video under the MPEG 2 technique.
`
`Likewise the audio driver 162 decodes the audio packets under the Dolby AC-3
`
`15
`
`technique, or other techniques. The video driver 160 and audio driver 162 can be
`
`implemented as a combination of both hardware and software elements. The video
`
`driver 160 outputs video to the CRT 110, while the audio driver 162 outputs sound to a
`
`speaker (not shown).
`
`In operation, the DVD information file manager 158 retrieves menu data
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`20
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`from the DVD CD-ROM disk 113, through the DVD driver 156, to display a menu
`
`through the user interface 154 on the CRT 110. A user inputs a request, which is
`
`received by the DVD information file manager 158 that in response thereto, allocates a
`
`location and number of sectors on the DVD CD-ROM disk 113 and requests the
`
`appropriate information from the DVD driver 156. The DVD driver 156 then reads the
`
`25
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`appropriate information from the DVD CD-ROM disk 113 and transfers the video
`
`objects data, and/or other data, to the DVD information file manager 158.
`
`The video objects manager 159 parses the video objects into video,
`
`audio, sub-picture and othe~ data packets. The video objects manager 159 transfers the
`
`video and audio packets to the video and audio drivers 160 and 162, respectively, under
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`30
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`synchronism according to time stamps. The video driver 160 then employs known
`
`MPEG 2 decoding techniques to decode the video and display it on the CRT 110.
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`Page 19 of 258
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`10
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`Similarly, the audio driver 162 employs known Dolby AC-3 techniques to decode the
`
`audio packets and play them back over the speaker. The decoding of audio and video
`
`continues until a break occurs, or the user interrupts the process by a user command to
`
`the user interface 154.
`
`5
`
`Importantly, the MPEG 2 decoding technique, performed at least in part
`
`by the video driver 160, requires 2 megabytes of memory because of temporal
`
`compression employed by
`
`the technique to compress information and eliminate
`
`redundancy therein. The MPEG 2 encoding technique refers to previous and future
`
`pictures to encode a current picture. As a result, the MPEG 2 decoding technique must
`
`10
`
`refer to previous and future pictures to decode a current picture. Thus, the MPEG 2,
`
`technique must store at least two images (past and future) to generate a current image.
`
`While prior MPEG 2 decoding circuits employed dedicated memory, the present
`
`invention shares the main memory 108 with the computer I 02.
`
`Referring to Figure 4, a memory sharing routine 200 performed by the
`
`15 microcontroller 120 (Figure 2) operates with the Windows 95 operating system 152
`
`(Figure 3) to request a 2-megabyte portion of the main memory 106. The routine 200
`
`can form part of the DVD information file manager 158 (Figure 3). In step 202, the
`
`microcontroller 120 initiates the routine 200 as a Windows 95-based application.
`
`Therefore, the microcontroller 120 interacts with the Windows 95 operating system 152
`
`20
`
`as a new executable application. In step 104, the microcontroller 120 requests from the
`
`Windows 95 operating system 152, 2 megabytes ofthe main memory 106. As is known,
`
`X86 microprocessors deal with physical memory in pages, each page being 4 kilobytes
`
`in size. Under step 204, the microcontroller 120 makes a low level ring zero function
`
`call to the Windows 95 operating system 152 to request 2 megabytes (500 total pages)
`
`25
`
`of