United States Patent [19J
`Artieri
`
`[54) PICTURE PROCESSING SYSTEM
`
`(75]
`
`Inventor: Alain Arlieri, Meylan, France
`
`[73] Assignee: SGS-Thornson Microelectronics S.A.,
`Saint Genis Pouilly, France
`
`[21) Appl. No.: 247,996
`
`[22)
`
`Filed:
`
`May 24, 1994
`
`[30)
`
`Foreign Application Priority Data
`
`[FR)
`[FR]
`
`France ................................... 93 06612
`France ................................... 93 13293
`
`May 27, 1993
`Oct. 29, 1993
`Int. Cl.6
`................................ H04N 7/30; H04N 7132
`[51]
`l52] U.S. Ct . .............................................................. 3481416
`[58] Field of Search ..................................... 348/416, 699;
`382/56, 43; 375/245, 246, 253; H04N 7/30,
`7/32
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`111989 Fumilaka Sato ..................... 3581261.1
`4,800,441
`5,253,078 1011993 Balkanski eta! ....................... 3481416
`1/1995 Purcell et al. ............................ 382156
`5,379,356
`
`FOREIGN PATENT DOCUMENTS
`
`3545106
`
`6/1987 Gennany ........................ G06F 15/68
`
`OTHER PUBLICATIONS
`
`Digital Image Processing Applications, Los Angeles, CA,
`Jan. 17-20, 1989, 140-147, Yushcng. T. Tsai, "Real-time
`architecture for error-tolerant color picture compression-
`
`11111111111111111 11111 111111111111111 11111 11111 1111111111111111 111111111111
`US005579052A
`[It] Patent Number:
`[45) Date of Patent:
`
`5,579,052
`Nov. 26, 1996
`
`."IEEE Colloquim on Parallel Architectures for Image Pro(cid:173)
`cessing Applications, Digest No. 086, London, UK, Apr. 22,
`1991, M. N. Chong, et al., "Pipeline Functional Algorithms,
`Data Partitioning for Adaptive Transform Coding AJgo(cid:173)
`rithms.""A One Chip VLSI for Real Time Two-Dimensional
`Discrete Losine", Circuits & Systems, 1988 IEEE Internal
`Sypos, Artieri et al, pp. 701-704.
`"A Realtime Image Processing Chip Set", Solid State Cir(cid:173)
`cuits, 1989 36th Conference, IEEE.
`"Designing a High- Throughput VLC Decoder Pans 1- TI(cid:173)
`- Parallel Decoding Methods", Lin ct al, IEEE Trans. in
`Circuits & Systems for Video technology, vol. 2, No. 2, Jun.
`1992, pp. 187-206.
`
`Primary Examiner-Tommy P. Chin
`Assistant Examiner-Vu Le
`Auomey, Agent, or Fimt-David M. Driscoll; James H.
`Morris; Brett N. Domy
`
`[57]
`
`ABSTRACT
`
`A system that processes compressed data ani ving in packets
`corresponding to picture blocks, the packets being separated
`by headers containing decoding parameters of the packets. A
`memory bus is controlled by a memory controller to
`exchange data between the processing clements and a pic(cid:173)
`ture memory. A pipeline circuit contains a plurality of
`processing clements. A parameter bus provides packets to be
`processed to the pipeline circuit, as well as the decoding
`parameters to elements of the system. The parameter bus is
`controlled by a variable length decoder that receives the
`compressed data from the memory bus and that extracts the
`packets and the decoding parameters therefrom.
`
`13 Claims, 7 Drawing Sheets
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`U.S. Patent
`
`Nov. 26, 1996
`
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`U.S. Patent
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`Nov. 26, 1996
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`Sheet 6 of7
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`5,579,052
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`U.S. Patent
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`Nov. 26, 1996
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`

`
`5,579,052
`
`1
`PICTURE PROCESSING SYSTEM
`
`BACKGROUND OF THE INVENTiON
`
`25
`
`35
`
`l. Field of the Invention
`The present invention relates to picture processing sys(cid:173)
`tems and more particularly to a system for decoding pictures
`encoded in accordance with an MPEG standard.
`2. Discussion of the Related Art
`FIG. 1 represents the main clements of an MPEG decoder
`8. All MPEG decoders, especially for the MPEG-2 standard,
`generally include a variable length decoder (VLD) 10, a
`run-level decoder (RLD) 11, an inverse quantizer circuit
`) 12, an inverse discrete cosine transform circuit (DCJ 15
`(Q- 1
`t) 13, a half-pixel filler 14, and a memory 15. The encoded
`data are provided to the decoder via a bus COin and the
`decoded data are output via a bus VIDout. Between the input
`and the output, the data pass through processing circuits
`10-13 in the order indicated above, which is illustrated by 20
`arrows in dashed lines. The decoder output is provided by an
`adder 16 that sums the outputs of filter 14 and of the cosine
`transform circuit 13. The filter 14 needs a portion of a
`previously decoded picture stored in memory 15.
`FIG. 2A illustrates a decoding step of a portion of a
`currently reconstructed picture IMl. Picture decoding is
`carried out one macro-block at a time. A macro-block
`generally corresponds to one 16x l6-pixel picture block.
`FIG. 2B illustrates an exemplary format, noted 4:2:0, of 30
`a macro-block MB. The macro-block MB includes a lumi(cid:173)
`nance block formed by four 8x8-pixel blocksY1- Y4 and by
`one chrominancc block formed by two 8x8-pixel blocks U
`and V. An alternative format is the 4:2:2 format where the
`chrominance block includes two 8xl6-pixel blocks.
`In the current picture h\111 of AG. 2A, a current macro(cid:173)
`block MBc is being decoded, the macro-blocks that were
`previously decoded being represented by hatched lines.
`Generally, macro-block MBc is reconstructed by using a
`predictor macro-block MBp fetched in a previously decoded 40
`picture IMO. To find the predictor macro-block MBp, the
`data that serve to decode macro-block MBc provide a
`movement compensation vector V that defines the position
`of the predictor macro-block MBp with respect to the
`position P of macro-block MBc in the picture.
`The predictor macro-block MBp is fetched in the memory
`15 that stores the previously decoded picture IMO, and is
`provided to filter 14 while the cosine transform circuit 13
`processes data corresponding to the macro-block MBc.
`The decoding described above is a so-called "predicted"
`decoding. The decoded macro-block is also referred to as
`being of predicted type. ln accordance with MPEG stan(cid:173)
`dards, there arc three main types of decoding, referred to as
`"intra", "predicted", and "bidirectional".
`An intra macro-block directly corresponds to a picture
`block, that is, the intra macro-block is not combined with a
`predictor macro-block when it is output from the cosine
`transform circuit 13.
`A predictor macro-block, as described above, is combined
`with one macro-block of a previously decoded picture, and
`that comes, in the display order, before the currently recon(cid:173)
`structed picture.
`A bidirectional macro-block is combined with two pre(cid:173)
`dictor macro-blocks of two previously decoded pictures,
`respectively. These two pictures are respectively former
`(forward) and subsequent (backward) pictures, in the display
`
`2
`order, with respect to the currently reconstructed picture.
`Thus, encoded pictures arrive in an order different from the
`display order.
`In addition, each predicted or bidirectional macroblock is
`s of a progressive or an interlaced type. When the macro(cid:173)
`block is progressive, the DC11 circuit provides the lines of
`the macro-block in successive order. When the macro-block
`is interlaced, the DC11 circuit first provides the even lines
`of the macro-block, then the odd lines. In addition, the
`10 predictor macro-block that serves to decode a predicted or
`bidirectional macro-block is also of the progressive or
`interlaced-type. When the predictor macro-block is of the
`interlaced-type, it is partitioned into two half-macro-blocks;
`one half macro-block corresponds to even lines, and the
`other half macro-block corresponds to odd lines, each half
`macro-block being fetched at diiTcrcnt positions in a same
`previously decoded picture.
`A picture is also of the intra, predicted or bidirectional
`type. An intra picture contains only intra macro-blocks; a
`predicted picture contains intra or predicted macro-blocks;
`and a bidirectional picture contains intra, predicted or bidi(cid:173)
`rectional macro-blocks.
`To provide the various decoding parameters to the various
`circuits of the decoder, especially vectors V and the macro(cid:173)
`block types, the flow of encoded data includes headers.
`There are several types of headers:
`a picture sequence header that includes in particular two
`quantizer tables to provide to the inverse quantizer
`circuit 12 , one serving for the intra macro-blocks of the
`sequence, and the second serving for the predicted or
`bidirectional macro-blocks;
`a group of picture header, that does not include useful data
`for decoding;
`a picture header that includes the type (predicted, intra,
`bidirectional) of the picture and information on the use
`of the movement compensation vectors;
`a picture slice header including error correction informa(cid:173)
`tion; and
`a macro-block header including the macro-block's type, a
`quantizer scale to be provided to the inverse quantizer
`circuit 12, and the components of the movement com(cid:173)
`pensation vectors. Up to four vectors are provided
`when processing an interlaced bidirectional macro-
`block.
`·
`In addition, the high hierarchy headers (picture, group,
`sequence) can include private data serving, for example, for
`on-screen display. Some private data can also be used by
`components external to the decoder.
`The various processing circuits of an MPEG decoder are
`so frequently arranged in a pipeline architecture which can
`process high data flow rates but which is very complex and
`inflexible, that is, which is difficult to adapt to modifications
`of the standards and which is inadequate to exploit on-screen
`display and private data.
`The simplest and most inexpensive solution is to couple
`the various processing circuits to the memory through a
`common bus that is controlled by a multi-task processor.
`Patent application EP-A-0,503,956 (C-Cubc) describes
`such a system including a processor that conrrols transfers of
`60 data on the bus and three coprocessors that execute the
`processing steps corresponding to circuits 10-14. Each type
`of transfer to be achieved via the bus corresponds to a task
`carried out by the processor. All tasks are concurrent and are
`executed at processor interrupts generated by the coproces-
`65 sors. The coprocessors exchange the data to be processed
`and receive the instructions provided by the processor via
`the bus.
`
`45
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`ss
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`An object of the present invention is to provide a par(cid:173)
`ticularly fast picture decompression system with a relatively
`simple structure.
`Another object of the invention is to provide such a
`decompression system that can be easily connected in par(cid:173)
`allel with identical decompression systems in order to pro(cid:173)
`cess very high data flow rates.
`To achieve these objects, the invention provides a decoder
`of composite architecture, that is, some of the processing
`elements are connected together and to a picture memory
`through a first bus, and some other clements are connected
`in a pipeline architecture. These other elements are referred
`to hereinafter as a ''pipeline circuit". A second bus is
`provided to supply data to be processed to the first clement
`of the pipeline circuit as well as the required decoding
`parameters to the clements of the system.
`With this structure, the pipeline circuit processes data
`serially without it being necessary to exchange them with
`the memory through the first bus. In addition, the first bus is
`relieved of the transmission of decoding parameters, these
`parameters being transmitted by the second bus. Thus, the
`number of exchanges on the first bus corresponding to a
`given decoding step
`is substantially reduced, which
`increases the system's performance. The system has a high
`flexibility resulting from the usc of a bus system. Tllis
`flexibility is increased by an optimal choice of the elements
`to be included in the pipeline circuit.
`The present invention more particularly addresses a sys(cid:173)
`tem for processing compressed data arriving in packets
`corresponding to picture blocks, these packets being sepa(cid:173)
`rated by headers containing decoding parameters of the
`packets. The system includes a plurality of processing
`elements using said decoding parameters, and a memory bus
`controlled by a memory controller to exchange data between
`the processing elements at rates adapted to the processing
`rates of these elements, and to store in a picture memory data
`to be processed or re-used. The system includes a pipeline
`circuit containing a plurality of processing elements con(cid:173)
`nected to process packets serially, and a parameter bus to 45
`provide packets to be processed to the pipeline circuit, as
`well as the decoding parameters to elements of the system.
`The parameter bus is controlled by a master processing
`element that receives the compressed data from the memory
`bus and that extracts the packets and the decoding param- 50
`eters therefrom.
`According to an embodiment of the invention, each
`packet of compressed data is preceded by a block header,
`and the packets come in successive groups, each group of
`packets being preceded by a group header containing group 55
`decoding parameters as well as, possibly, private and on(cid:173)
`screen display information. The system further includes a
`processor bus controlled by a microprocessor to supply the
`group decoding parameters and the private and on-screen
`display information to the system elements requiring them; 60
`a buffer memory accessible by the processor bus, receiving
`the compressed data through tbe memory bus; and a group
`header detector cooperating with this buffer memory to
`generate interrupts of the microprocessor.
`According to an embodiment of the invention, a transfer 65
`of data between two elements connected to the memory bus
`corresponds to a specific task that is initiated or continued
`
`3
`This system is simple, but it is incapable of handling the
`high data flow rates needed.
`
`SUMMARY OF THE INVENTION
`
`(cid:51)(cid:68)(cid:74)(cid:72) (cid:20)(cid:19) (cid:82)(cid:73) (cid:21)(cid:19)
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`4
`when one of the two elements issues a ·request to provide or
`to receive data, all the possible tasks being concurrent tasks
`that are carried out by the memory conitroller according to a
`task priority management.
`According to an embodiment of the invention, the ele(cid:173)
`ments which exchange data with the picture memory are
`connected to the memory bus through respective write- or
`read-only buffer memories. A write-only buffer memory is
`emptied by the associated element and issues a request to
`receive data through the memory bus when its content
`reaches a lower limit. A read-only buffer memory is filled by
`the associated element and issues a request to provide data
`on the memory bus when its content reaches an upper limit.
`According to an embodiment of the invention, the system
`includes a variable length decoder (VLD) forming the
`master processing clement; a run-level decoder (RLD) form(cid:173)
`ing a first element of the pipeline circuit and receiving
`through the parameter bus the packets processed by the
`VLD; an inverse quantizer circuit forming a second element
`20 of the pipeline circuit and receiving quantizer scale coeffi(cid:173)
`cients through the parameter bus; an i overse cosine trans(cid:173)
`form circuit forming a third element of the pipeline circuit;
`the memory controller receiving movement compensation
`vectors through the parameter bus; a filter receiving block
`types through the parameter bus, this filter issuing distinct
`requests, according to the block types, to receive corre(cid:173)
`sponding data provided on the memory bus as a function of
`the vectors received by the memory controller; and an adder
`to provide on the memory bus the sum of the outputs of the
`30 filter and of the cosine transform circuit.
`According to an embodiment of the invention, the group
`header detector generates interruptions of the microproces(cid:173)
`sor when the associated buffer memory contains a picture
`sequence header or a picture header, the microprocessor
`being programmed to respond to these interruptions by
`reading, in the buffer memory associated with the group
`header detector, quantizcr tables that the microprocessor
`provides to the inverse quantizer circuit, information on the
`picture type and on the amplitude of the movement com(cid:173)
`pensation vectors tbat the microprocessor provides to the
`VLD, and information on the display configuration that the
`microprocessor provides to a display controller which
`receives the decoded data through the memory bus.
`According to an embodiment of the invention, the
`memory controller includes an instruction memory (inde(cid:173)
`pendent of the memory bus), in which are stored the
`program instructions corresponding respectively to transfer
`tasks on the memory bus; an instruction processing unit that
`is connected to the instruction memory in order to rccci vc
`therefrom successive instructions to be executed, and that is
`connected to act on the memory bus in response to these
`instructions; a plurality of instruction pointers associated
`respectively to possible tasks and each including the current
`instruction address to be executed of the associated task, one
`only of these pointers is enabled at a time to provide its
`content as an instruction address to the instruction memory;
`a priority decoder assigning a predetermined priority level to
`each request and enabling the instruction pointer associated
`with the active request having the highest priority level; and
`means for incrementing the content of the enabled instruc(cid:173)
`tion pointer and for reinitializing it at the address of the
`associated program start when its content reaches the end
`address of the associated program.
`According to an embodiment of the invention, each
`instruction includes a command field that is provided to the
`processing unit and a feature field provided to a prefix
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`decoder that includes means for authorizing the enabling of
`a new instruction pointer by the priority decoder if the
`feature field of the current instruction is at a first predeter(cid:173)
`mined value, and means for initializing the content of the
`enabled instruction pointer to the start address of the current s
`program if the feature field of the current instruction is at a
`second predetermined value.
`According to an embodiment of the invention, the prefix
`decoder includes means for inhibiting the incremcntation of
`the enabled instruction pointer if the feature field is at a third 10
`predetermined value, so that the current instruction is
`executed consecutively several times, the number of execu(cid:173)
`tions being determined by this third value.
`According to an embodiment of the invention, each
`instruction includes a command field that is provided to the 15
`instruction processing unit and an acknowledge field that is
`provided to means for, when the instruction is being
`executed, enabling at least one buffer memory connected to
`the memory bus.
`According to an embodiment of the invention, the pro- 20
`cessing unit includes a plurality of hard wired functions for
`the calculation of addresses, each function being selected by
`a field of a read or write instruction that is being executed.
`According to an embodiment of the invention, ~ith each
`hard wired function is associated an address reg1ster con-
`ncctcd to the memory bus; the hard wired function suitably
`modifies the content of its address register each Lime an
`instruction is executed in the processing unit.
`The present invention also addresses a system for pro(cid:173)
`cessing compressed data corresponding to pictures, includ-
`ing decoding means that provide decoded picture data to a
`picture memory, these means requiring, for decoding a
`current block of a picture being reconstructed, a predictor
`block of a previously decoded picture. In fact, the processing
`system includes a plurality of decoders associated with
`respective picture memories, each storing a specific slice of 3S
`corresponding blocks of a plurality of pictures, as well as at
`least one margin in which is liable to be a predictor block
`used for reconstructing a bloclc of the specific slice.
`According to an embodiment of the invention, each
`considered decoder includes means for storing in its picture 40
`memory, as a margin, a boundary area of at least one
`additional specific slice and for providing to at least one
`second decoder, as a margin, a boundary area of the specific
`slice associated with the considered decoder.
`According to an embodiment of the invention, each 45
`considered decoder includes a first buffer memory receiving
`picture blocks from the specific slice; at least one second
`buffer memory receiving picture blocks from an adjacent
`area of another specific slice; a terminal processing circuit
`providing the blocks of the specific slice to the first buffer 50
`memory of the considered decoder and to lhe second buffer
`memory or another decoder; and a memory controller to
`read the blocks in the first butTer memory and to write them
`in the picture memory at addresses corresponding to the
`specific slice, and to read the blocks in the second buffer
`memory and to write them at addresses corresponding to a
`margin.
`According to an embodiment of the invention, each
`second buffer memory is preceded by a barrier circuit in
`order to store in the second buffer memory only the data
`corresponding to the desired margin.
`According to an embodiment of the invention, the pic(cid:173)
`tures to be processed arc high definition television pictures
`that arc partitioned in horizontal slices of equal height.
`The foregoing and other objects, features, aspects and
`advantages of the invention will become apparent from the
`
`6
`following detailed description of the present invention
`which should be read in conjunction with the accompanying
`drawings.
`
`BRIEF DESCRIPTION OF ORA WINGS
`
`FIG. 1, above described, shows the main elements of an
`MPEG decompression system;
`FIG. 2A illustrates a decoding step of a macro-block;
`FIG. 28 represents an exemplary macro-block structure;
`FIG. 3 represents an embodiment of a decompression
`system architecture, or MPEG decoder, according to the
`invention;
`FIG. 4 is a timing diagram illustrating tlhe operation of the
`decompression system of FIG. 3;
`FIG. 5 represents an advantageous embodiment of a
`memory controller according to the invention;
`FIG. 6 represents another embodiment of a decompres(cid:173)
`sion system architecture according to the invention;
`FIG. 7 illustrates a high definition television picture that
`is to be processed by slices by a plurality of parallel
`decompression systems;
`FIG. 8 represents a plurality of decompression systems
`connected in parallel to process a high definition picture; and
`PIG. 9 partially represents an embodiment of an internal
`structure of a decoder according to the invention that allows
`an easy parallel connection.
`
`GENERAL ARCHITECfURE OF THE MPEG
`DECODER
`
`In FIG. 3, the clements already shown in FIG. 1 are
`designated with the same reference numerals.
`A bus, hereinafter memory bus MBUS, couples the pic-
`ture memory 15 to the compressed data input bus COin, to
`the input of the variable length decoder (VLD) 10, to the
`input of the half-pixel filter 14, and to the input of a display
`controller 18. Bus COin, decoder 10 and display controller
`18 arc connected to the memory bus MBUS through respec(cid:173)
`tive buffer memories (FIFOs) 20, 21, and 22. The half-pixel
`filter 14 includes two internal PIFOs that are connected to
`the memory bus MBUS. Exchanges on the memory bus
`MBUS are controlled by a memory controller (MCU) 24
`that serves to carry out, upon request of the FIFOs, transfer
`operations between these FIFOs and t.he picture memory. To
`achieve this purpose, the memory controller 24 receives a
`plurality of requests RQ and provides corresponding
`acknowledgements ACK. The memory controller 24 can be
`such as the one described in the above patent application
`EP-A-0,503,956. A more advantageous embodiment of this
`memory controller will be described hereinafter.
`According to the invention, the run-level decoder (RLD)
`11, the inverse quanlizer circuit (<T1) 12, and the inverse
`discrete cosine transform circuit (Ocr') 13 are connected
`according to a pipeline architecture, that is, these circuits
`11- 13 successively process data to decode, without these
`60 data temporarily transitling through a memory 15. The set of
`circuits 11- 13 is referred to as a pipeline circuit hereinafter.
`The output of the half-pixel filter 14 is summed to the output
`of the ocr' circuit 13 by an adder 16 that is coupled to the
`bus MB US through a FIFO 26 controlled by the memory
`65 controller 24. Hand-shake lines HSl and HS2 connect the
`adder 16 to the VLD circuit and to the ocr• circuit,
`respectively.
`
`55
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`not be used to calculate another picture. Thus, the recon(cid:173)
`struction of picture Pl requires picture 10, the reconstruction
`of pictures B2 and 83 requires pictures 10 and Pl. the
`reconstruction of picture P4 requires picture Pl. and the
`reconstruction of pictures B5 and B6 requires pictures P4
`and Pl.
`These pictures are displayed in the following order:
`
`10. 82, 83, PI, 85, P4, 86
`
`15
`
`since a predicted picture P is reconstructed from a former
`picture in the display order, and since a bidirectional picture
`B is reconstructed from two pictures, one former and the
`other subsequem in the display order.
`To determine the memory area IMl-L\13 which the
`memory controller 24 must access, four picture pointers RP,
`FP, BP, and DP are used, respectively indicating the loca(cid:173)
`tions of the currently reconstructed picture, of the former
`(forward) picture, of the subsequent (backward) picture, and
`20 of the currently displayed picture. The following table sums
`up the values of the picture pointers during the decoding of
`the above succession.
`
`10
`
`IMJ
`
`Decode
`Display
`
`RP
`FP
`BP
`DP
`
`PI
`10
`
`1M2
`IMI
`
`!Ml
`
`82
`B2
`
`1M3
`!Ml
`1M2
`1M3
`
`B3
`B3
`
`1M3
`IM I
`1M2
`1M3
`
`P4
`PI
`
`IM I
`1M2
`
`1M2
`
`85
`85
`
`1M3
`1M2
`!Ml
`1M3
`
`25
`
`30
`
`7
`According to an aspect of the invention, the VLD circuit
`10 controls a bus VLDBUS intended to provide to the RLD
`circuitll data to be processed by the pipeline circuit 11- 13,
`as well as parameters to the half-pixel filler 14, to the inverse
`quantizer circuit 12, to the display controller 18, and to the 5
`memory