Conference Materials
`------------------------------------------------------------· . . - - - - - - - - . ,
`Fairmont Hotel, San Jose
`October 10-11, 1995
`
`Sponsored by
`MICRODESIGN
`R E S 0 U R C E S
`
`Page 1 of 16
`
`ZTE Exhibit 1 034
`
`

`
`(
`'-,
`
`(
`'
`
`DAY ONE Tuesday, October 10
`
`AGENDA
`
`WElCOME Michael Slater
`
`KEYNOTE: SEMICONDUCTOR TECHNOLOGY AND THE GROWTH OF THE PC INDUSTRY
`Craig Barrell, Intel
`X86 MICROPROCESSORS Moderator: Michael Slater, MicroDesign Resources
`Shifting Sands in the x86 landscape
`Michael Slater
`P6: The Myths and Realities
`Robert Colwell, Intel
`BREAK: SPONSORED BY NEC ELECTRONICS
`AMD-K5 Performance and Microarchitecture Tradeoffs
`David Witt, AMD
`Optimizing the Ml for Windows 95
`Mark Bluhm, Cyrix
`'Overview of the Nx686 Processor
`Greg Favor; NexGen
`Q&A Panel
`All Speakers above
`LUNCH
`
`Market Trends for x86 Microprocessors
`Aaron Goldberg. Computer Intelligence InfoCorp
`PROCESSORS FOR MULTIMEDIA Moderator: Yang Yao, MicroDesign Resources
`Implementation Strategies for Multimedia
`YongYao
`Architecture of a Broadband Mediaprocessor
`John Moussouris, MicroUnity
`A VLIW and SIMD Vector Processor for PC Multimedia
`Stephen Purcell, Chromatic
`The TriMedia VLIW-Based PCI Multimedia Processor
`Gerrit Slavenburg, Philips Semiconductors
`BREAK: SPONSORED BY LSI LOGIC
`
`M.EA.S.T: A Highly Parallel, Scalable, Single-Chip DSP
`Gerald Pechaneh, lBM Microelectronics
`UltraSPARC's Instruction Set Extensions for Multimedia
`Marc Tremblay, Sun Microsystems
`A Multimedia 586 Processor for Consumer PCs
`Forrest Norrod, Cyrix
`Q&A Panel
`All speakers above
`MICROPROCESSOR REPORT AWARDS
`Nick Tredennick, Tredennick, Inc.
`RECEPTION/LITERATURE & DEMONSTRATION CENTER OPENING
`
`8:40
`
`9:20
`
`10:00
`
`12:00
`
`1:10
`
`1:30
`
`2:50
`
`3:10
`
`5:00
`
`5:30
`
`( }
`
`AFFINITY SESSIONS
`8:30PM-10:30PM
`Open Session on Cryptography
`Packaging Technology Directions
`
`Benchmarks & Workloads Roundtable
`The Issue of Branding Microprocessors
`
`Sponsored by
`..._ __ ___ ______ MICRODESIGN - - - - - - - - - - - - - - - '
`RESOURCES
`
`1995 Microprocessor Forum
`Page 2 of 16
`
`

`
`DAY TWO
`
`October 11
`
`AGENDA
`
`EMBEDDED PROCESSORS
`Moderator: James L Turley, MicroDesign Resources
`Ubiquitous Computers: The New Embedded Applications
`james L. Turley
`Bringing RISC Technology to Communications
`Robert O'Dell, Mowrola
`An Integrated i960 to Enhance Server and Network 1/0
`Elliot Garbus, Intel
`SH-DSP & SH-FPU: Optimized Communication & Consumer Microprocessors
`jim Slager, Hitachi
`StrongARM Reaches for Ever Higher Performance
`Rich Witek, Digital
`BREAK: SPONSORED BY FUJITSU MICROELECTRONICS
`A Scalable 64-bit RISC for Custom Designs
`Bob Caulk, LSI Logic
`A PowerPC Core for Cost-Sens itive Consumer Applications
`Kim O'Donnell, IBM
`A Next-Generation DSP Solution for Communications Applications & Beyond
`Roman Robles, Motorola
`Q&A Panel
`All speakers above
`
`LUNCH
`HIGH-PERFORMANCE RISC MICROPROCESSORS
`Moderator: Linley Gwennap, MicroDesign Resources
`RISC Processors: Generations
`Linley Gwennap
`PA-7300LC: A Highly Integrated System on a Chip
`Tom Meyer, Hewlett-Packard
`The Performance of PowerPC 603e and 604e Microprocessors
`Kaivalya Dixit, IBM
`Colorado 4 Extends 32-bit SPARC Performance
`Mitch Alsup, Ross Technology
`BREAK: SPONSORED BY MIPS TECHNOLOGIES
`UltraSPARC2: Advancing SPARC Performance
`Anant Agrawal, Sun Microsystems
`Alpha 21164A: Continued Performance Leadership
`Pete Bannon, Digital Semiconductor
`Q&A Panel
`All speakers above
`PANEL: FUTURE OF MICROPROCESSOR SYSTEM ARCHITECTURE
`Moderator: Michad Slater
`Dirk Meyer, Digital
`Lin Nease, Hewlett-Packard
`Don North, Apple
`
`Richard Oehler, IBM
`Fred Pollack, Intel
`George White, Corollary
`
`(
`
`)
`
`)
`
`\
`
`10:20
`
`12:00
`1:10
`
`2:30
`
`..
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`4:10
`
`• • . ~-!· .! .
`
`.. , ...
`
`5:00
`5:10
`
`WRAP-UP Michael Slater
`CONFERENCE ADJOURNED
`
`Sponsored by
`MICRODESIGN
`-------------------------------------------------------------~
`RESOURCES
`2
`
`~---------------------------------------------------------
`1995 Microprocessor Forum
`Page 3 of 16
`
`

`
`e speaker biographies
`
`r·
`
`Michael Slater, moderator
`Founder and President of MicroDesign Resources, Michael
`Slater serves as the Editorial Director and Publisher of
`Microprocessor Report and Director of the Microprocessor
`Forum. He is internationally recognized as a leading authority
`on microprocessor technology and system trends. Michael has
`lectured at Stanford University, Santa Clara University, and
`National Technological University. He has presented hundreds
`of seminars and consults regularly for companies including
`IBM, Apple, Sun, Intel, Motorola, AMD, Amdahl, Digital, and
`Tektronix. He is a columnist for Electronic Engineering Times,
`Nikkei Electronics Asia, and Computer Shopper, and he has writ(cid:173)
`ten for many computer publications.
`Linley Gwennap, moderator
`is Editor-in-Chief of Microprocessor Report and Director of
`Product Development for MicroDesign Resources. He joined
`MDR in 1992 after eight years at Hewlett-Packard working on
`RISC systems. His positions at HP included Product Manager
`for the HP PA7100 microprocessor, Program Manager for the
`HP9000 model815, and System Designer for the HP9000 model
`870. He currently consults on microprocessor developments and
`strategies for leading processor and system vendors.
`James Turley, moderator
`Senior Analyst and Senior Editor of Microprocessor Report, spe(cid:173)
`cializing in high-performance embedded microprocessors, Jim
`joined MDR in 1994 after devoting more than a dozen years to
`design engineering, engineering management, product market(cid:173)
`ing, and program management. He has designed embedded
`processors into a variety of products and developed both hard(cid:173)
`ware and software for leading companies around Silicon Valley
`and in Europe. He has also conducted numerous seminars and
`training courses.
`Yong Yao, moderator
`Director of the Technology Roadmap Service and Senior
`Analyst for PC technology for Microprocessor Report, is the most
`recent addition to the MicroDesign Resources staff of analysts.
`Prior to joining MDR, Yong was with Vitesse Semiconductor,
`where he was the director of product planning as well as the
`designer of the multiprocessor V-Bus.
`Craig Barrett, keynote speaker
`is Executive Vice President and Chief Operating Officer of Intel
`Corporation, having corporate-wide responsibility for internal
`operations of the company. He joined Intel in 1974 and served
`in various technical and business management positions. In
`1984 Dr. Barrett was named a Vice President, and he became
`General Manager of the Components Technology and
`Manufacturing Group in 1985. Dr. Barrett was named a Senior
`Vice President in 1987 and became comanager of the
`Microcomputer Components Group in 1989. He was promoted
`to the post of Executive Vice President in 1990. Dr. Barrett was
`elected to the Board of Directors in 1992 and was named Chief
`Operating Officer in January 1993.
`
`Anant Agrawal is Vice President of Engineering for Sun's
`SPARC Technology Business. He has been involved in the
`design and development of the SPARC microprocessors at Sun
`since 1984.
`Mitch Alsup is ROSS Technology's Chief Architect for its
`SPARC CPU product line. Mitch joined ROSS in 1991 from
`Motorola, where he was the Architect of Motorola's 88000.
`Peter Bannon is a Consulting Engineer with Digital
`Semiconductor, Pete has participated in the design or verifica(cid:173)
`tion of several microprocessor chips and was a member of the
`Alpha 21164 architecture team.
`Mark Bluhm is the Chief Architect of Cyrix's M1 as well as director
`of engineering responsible for all future superscalar processors. As one
`of Cyrix's initial design engineers, Mark helped define and design sev(cid:173)
`eral generations of wholly original x86 processors and math coproces(cid:173)
`sors.
`Bob Caulk has spent the last six years at LSI Logic leading
`architecture definition and product development for LSI's MIPS
`ruse processor family of embedded cores and derivative
`products.
`Robert Colwell manages the P6 architecture organization at
`Intel. Bob joined Intel in 1990 as a Senior Architect on the P6
`project, and became manager of the architecture group two
`years later. Prior to Intel he was a CPU architect at Multiflow
`Computer.
`Kalvalya Dixit is IBM's Director of Perfomance. Previous to
`joining IBM, he was Engineering Program Manager at SUN
`Microsystems.
`Gregory Favor is NexGen's Director of 686 Processor
`Development. Previous to his appointment to the Director
`position he was the Chief Processor Architect.
`Elliot Garbus is Strategic Development Manager in Intel's
`Semiconductor Products Group. Elliot has participated in the
`definition of the three generations of 80960 microprocessor
`products. He is currently working on products to enhance the
`1/0 performance of servers.
`Aaron Goldberg is Executive Vice President of Computer
`Intelligence InfoCorp. Prior to joining InfoCorp in 1992, Aaron
`was Senior Vice President of the Desktop Computing Group at
`International Data Corporation.
`Dirk Meyer is the Lead Architect of Digital's third-generation
`high-end Alpha microprocessor. Dirk was a co-microarchitect
`of Digital's first-generation Alpha 21064 microprocessor and an .
`original member of the .Alpha CPU team.
`Tom Meyer is currently a member of Hewlett-Packard's
`Systems Technology Division and Project Manager for the
`PA7300LC integrated memory and 1/0 controller. Previously he
`worked on the PA7100LC and the memory controller for sever(cid:173)
`al of the HP9000 Series computers:
`
`MICROPROCESS~
`. .
`-------------------~~---------------------------------------------------------------------~-~
`
`

`
`Jim Slager specializes in microprocessor and multimedia prod(cid:173)
`ucts, Jim is Director of Advanced Product Planning at Hitachi
`Micro Systems. He participated in the design of the 286, 386,
`and 486 at Intel and was involved in SPARC design at Sun
`Microsystems.
`Gerrit Slavenbelg Chief Scientist, TriMedia technology, for
`Philips Semiconductors, Gert is responsible for development of
`current and future TriMedia products.
`Nick Tredennlck is President of Tredennick, Inc. He created the
`logic design for the 68000 at Motorola and for the Micro/370
`microprocessor at IBM.
`Marc Tremblay, as a computer architect involved in the
`research and development of high-performance processors at
`Sun Microsystems Marc's main contributions have focused on
`the microarchitecture definition and performance evaluation
`for the 64-bit UltraSPARC Processor.
`George White, a cofounder and President of Corollary, George
`has pioneered a new category of computer, the PC-compatible
`multiprocessor system. He was instrumental in the develop(cid:173)
`ment of the NuBus and was the chairman of the IEEE commit(cid:173)
`tee that standardized the NuB us.
`Rich Witek, a principal designer of the Alpha architecture and
`co-architect of the first Alpha chip, Rich is currently the Chief
`Architect for the StrongARM microprocessor family at Digital.
`David Witt is a Product Development Manager at AMD, where
`he is in charge of the Argon/K7 processor development. David
`was in charge of the KS development effort at AMD, where he
`has been working for the past 11 years.
`
`•I speaker biographies
`
`John Moussomis is President and CEO ofMicroUnity Systems
`Engineering, which he founded in 1988. Prior to that John was
`Vice President ofVLSI Development at MIPS Computer Systems.
`Un Nease has been a System Architect for several of Hewlett(cid:173)
`Packard's UNIX server products, including the G-, H-, and 1-
`class midrange/low-end systems. He has been involved in the
`development of HP's commercial UNIX servers since the
`advent of that product line.
`Forrest Norrod is Program Manager and Principal Architect of
`the multimedia 586 CPU at Cyrix. Prior to joining Cyrix in
`1993, Forrest was with Hewlett-Packard, where he designed
`advanced 3D graphic systems.
`Don North has been associated with the Advanced Technology
`Group at Apple since its inception in 1985, and currently man(cid:173)
`ages a systems architecture research group. His current research
`interests include high-performance system interconnect issues
`and multiprocessor systems architecture.
`Richard Oehler is the Director of Systems Software in the
`Power Personal Systems Division at IBM. In over 20 years with
`IBM he has been involved in development of the 801, the first
`ruse machine, was lead architect for the the ruse System/6000,
`and is responsible for all dealings on PowerPC. In 1994 Rich
`became an IBM Fellow.
`Robert O'Dell has played a significant role in the definition of
`Motorola's integrated communications controller family of
`products. Robert is currently the Applications Manager for the
`Data Communications Operation in the High Performance
`Embedded Systems Division of Motorola's Semiconductor
`Products Sector.
`Kim O'Donnell, as Senior Engineering Manager for IBM, is
`responsible for the design and development of the IBM
`PowerPC 400 Series of Embedded Controllers.
`Gerald Pechanek, at IBM Microelectronics Mwave group, is
`involved in the research and development of parallel computer
`architectures for graphics-, video-, neural-, and signal-process(cid:173)
`ing multimedia applications.
`Fred Pollack is director of the group responsible for all Intel
`platform architecture and performance analysis. He also directs
`the planning for Intel's future microprocessors. Prior to this, he
`was the manager of the P6 architecture. In January of 1993 he
`was promoted to an Intel Fellow, one of nine in the company.
`Stephen Purcell is co-founder of Chromatic. He was previous(cid:173)
`ly a founder and Chief Architect at C-Cube Microsystems where
`he created the architecture for four generations of video
`CODECs, including the VideoRISC processor.
`Roman Robles is manager of Motorola's 24- and 32-bit DSP
`applications group. He has worked in Motorola's DSP applica(cid:173)
`tions group for the past five years, focusing primarily on
`Motorola's industry-standard 24-bit DSP56000 architecture and
`applications.
`
`)
`
`.1
`
`

`
`The TriMedia VLIW-Based
`PCI Multimedia Processor
`
`---------------------------------------------------------------------~ r--------------------------,
`Gerrit Slavenburg
`Philips Semiconductors
`
`Sponsored by
`MICRODESIGN
`R E S 0 U R C E S
`
`Page 6 of 16
`
`12
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`The Trimedia VLIW-based PCI
`Multimedia Processor System
`
`Gerrit Slavenburg - Philips Semiconductors
`
`c
`
`TM-1 : outside
`
`SO RAM
`
`TM-1
`
`CCIR 601/656
`YUV 4:2:2
`
`JTAG
`
`• multl•standard, as In "any"
`• VIdeo and Audio (de)compression
`• 3D graphics
`• Customer programmable, using
`standardC
`
`CCIR 601/656
`YUV 4 :2:2
`
`phone
`
`PCI bus
`
`Microprocessor Forum
`
`12-l
`
`October 10-11, 1995
`
`Page 7 of 16
`
`

`
`The Trimedia VLIW -Based PCI Multimedia Processor
`
`TM-1 configurations
`
`audio
`
`(dig) VCR
`TV monitor
`audio
`RGB image e;qugnces
`
`accellerator
`
`graphics
`card
`
`stand alone
`
`TV monitor
`
`PCI bus
`
`host CPU
`
`audio
`
`peri ph.
`
`peri ph.
`
`PCibus
`
`TM-1 · inside
`
`Serial
`dlg~ol audio
`
`4---i
`
`JTAG
`pC
`
`PC I local bus
`
`Microprocessor Forum
`
`12-2
`
`October 10-11, 1995
`
`Page 8 of 16
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`TM-1 Functional
`hardware
`
`Video DMA in:
`-:. CCIR601/656 YUV 4:2:2 input
`~ horizontal scaling by 1 :1 or 2:1
`Video DMA out:
`·> CCIR601/656 YUV 4:2:2 out
`·> horizontal scaling by 1:1 or 1:2
`·=· graphics overlay (alpha blending)
`Image co-processor
`,, memory-to-memory
`·=· memory to PCI windows, with YUV to RGB
`-> V resizing, H resizing
`VLD co-processor
`<· memory-to-memory de-tokenize
`·> MPEG-2, MPEG-1 slice/time
`
`hardware
`Audio DMA in/out:
`·> 8 or 16 bit
`·=· mono or stereo
`·> programmable 0 • 80 kHz sampling
`software
`multi-tasking in Con DSPCPU:
`·> compression (any standard)
`·:· decompression (any standard)
`•> 30 graphics
`~· system control
`·> PC API support
`using powerful custom multimedia
`operations
`
`(_
`
`.
`
`.. , J
`
`TM-1 Highway Arbitration
`
`·:· software assigns bandwidth to each master
`·:· every master is guaranteed:
`- minimum bandwidth as assigned
`- associated max. latency
`·:· all unused bandwidth is available:
`-
`to the DSPCPU/caches within 1 cycle
`-
`to any other master within a few cycles from request
`this is an essential function for audio/video
`
`Microprocessor Forum
`
`12-3
`
`October 10-11, 1995
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`Image Co-Processor capabilities
`
`live video windows
`.+ arbicr.uy H & V sCllling
`using quality filters
`+ can drive RGB or YUV
`graphics cards
`+ up to 50 MpixeVsec refresh
`
`AudioNideo synchronization
`
`VIdeo In:
`VIdeo Out :
`
`Audio In,
`Audio Out:
`
`camera/outside world Is pixel clock master
`programmable 10 MHz - 38 MHz, resolution 0.02 Hz
`(very low jitter synthesizer)
`
`programmable 256 or 384fa of 0 - 20 MHz, 0.02 Hz
`
`Synchronization Is achieved by software PLL's that vary the sampling
`frequencies/phase by minute amounts. This powerful method is universal
`and avoids application specific external hardware.
`
`Microprocessor Forum
`
`12-4
`
`October 10-11, 1995
`
`Page 10 of 16
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`TM-1 DSPCPU block diagram
`
`lnatruetlon r--~?±="~~'""'"'=~~--..:li!:"''""!'-:-'-"":-:.,.,.......T"'""--"--...~.,.,----,-...J....:::'---.
`Issue
`register
`
`(_
`
`TM-1 DSPCPU functional units
`
`Fnnd innl'lllJnit
`constant
`intel!er AU J
`lo:ul/.c;t.orP.
`DSPAUJ
`DSPMUL
`shiftP.r
`hm"".h
`int/float mul
`flollt A J .TJ
`float r.omnarP.
`float sortldiv
`
`Onantitv
`5
`5
`2
`2
`2
`2
`3
`2
`2
`1
`1
`
`T .afP.n~v
`1
`1
`3
`2
`3
`1
`:\
`3
`3
`1
`17
`
`RP.rnvP.rv Time
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`lti
`
`Microprocessor Forum
`
`12-5
`
`October 10-11, 1995
`
`Page 11 of 16
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`TM-1 instruction format
`
`• 5 operations Issued every clock cycle (1 o nSec}
`• Functional units are pipelined -each can start one operation per cycle
`• Issue slots are "guarded" for branch avoidance, delay slot utilization
`• Interruptable opcodes facilitate lightweight context switching
`• Instructions compressed in memory and !cache, decompressed on the fly
`
`IF R48
`
`iadd
`
`R49
`
`R99
`
`R121
`
`Trimedia programmer's model
`
`registers
`
`memory map
`
`232
`
`32
`
`..
`
`programmable base
`
`64
`
`programmable base
`
`0
`
`Microprocessor Forum
`
`12-6
`
`October 10-11, 1995
`
`Page 12 of 16
`
`\... ·
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`Trimedia operation examples
`
`Typical 32 bit RISC CPU operations
`·:· Integer, unsigned, logical, floating point (32 bit IEEE compatible)
`·:· Conditional branches
`·:- Loads/stores with address modes
`Typical 8, 16 and 32 bit DSP operations
`·:· Saturation arithmetic (add, multiply-add, ... )
`Branch-avoiding operations
`·:· Min, max
`·:· Select one of two operands depending on a third
`(implemented as branch-free three-operation sequence)
`35 Multimedia-enhancing operations
`(motion estimation)
`.;. me8(abcd,efgh)
`la-el + lb-fl + lc-gl + ld-hl
`(FIR filters)
`·:· fir16(ab,cd) Dual multiply-add- ac+bd
`!!!t!. b+f+1 c+s+1 d+h+tsubsampling filters)
`·:· quadavg(abcd,efgh)
`2 '2 '2 '
`2
`
`TM-1 DSPCPU key features
`
`·:• dual bytesex, determined by PCSW flag
`.;. byte addressed memory, natural alignment required
`·:· speculative loads & floating point supported
`·:· precise IEEE exceptions, even when using speculation
`·:· 5 ops/cycle, sustained
`·:· conditional (guarded) execution of each operation
`·:· compressed, byte aligned VLIW instructions
`.;. vectored interrupts, zero overhead enter/return
`- compiler inserts interruptable points
`-CPU can handle simple interrupts at> 100kHz with low loading
`·:· instruction & data (address/value) breakpoint hardware
`·:· level-1 boot from I2C resident serial xxROM
`
`Microprocessor Forum
`
`12-7
`
`October 10-11, 1995
`
`( __
`
`'<. ~ · ..
`
`L
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`Example TM-1 {simplified to 3/cycle)
`
`cycle
`101
`102
`103
`104
`105
`106
`107
`
`ld32 r12(4)-+r13
`#13---+rll
`iaddi r12,220-+r17
`ileq rll,r15-+rll
`rll:st32 r12(8) r14
`ld32x r17,r19 -+r16
`rll:st32 r12(12) r13
`bitinv rll-+r21
`r21:st32 r12(12) r17 r21:fir8 r101,r102-+r23
`r21:fir8 r103,r16-+r25
`r21:#1234-+r24
`firS r104,r10S-+r26 firS r106,r107-+r27
`
`me8 r101,r100-+r14
`#LABEL-+r18
`cjmpt rll,r18
`rll:me8 r99,r98-+r42
`rll:me8 r97,r96-+r43
`rll:me8 r95,r94-+r44
`iadd r42,r43-+r45
`
`107 me8 r93,r92-+r45 me8 r91,r90-+r46
`
`#OxffffOOO-+r18
`
`TM-1 system key stats
`
`• consumer electronics price level, ranging to sub $50
`• Early Access Program:
`- software development tools (now)
`- samples Q2 '96
`• application performance:
`- MPEG-2 main level, main profile, 15 Mbit/sec.
`Vldeo+Audio+System decoding
`- H.320 codec Vldeo+Audlo
`- H.324 codec Vldeo+Audio+software V.34 modem
`- any custom VIA algorithms with similar compute requirements
`+ typical4 W (@ 100 MHZ, 3.3 V)
`• 0.5u CMOS, 4L metal with shrink to 0.35u to follow
`• available in 240 pin EDQUAD or SuperBGA package
`
`Microprocessor Forum
`
`12-8
`
`October 10-11, 1995
`
`

`
`The Trimedia VLIW -Based PCI Multimedia Processor
`
`Software development
`
`'human assisted microcode compilation'
`
`·:· sophisticated compiler/debugger environment
`·•· compile, run, recompile for automatic fine grain
`parallelization
`·:· programmer feedback (where is time spent, where is
`parallelism limited)
`
`c
`
`L
`
`TM-1 Innovations
`
`·:> very high performance CPU on a chip at a consumer
`price point
`- enhanced VLIW architecture with conditional execution
`- VUW Instruction compression : sub RISC code size
`- multimedia operation set based on actual application ports
`- zero overhead interrupt handling
`- sophisticated compiler : profile driven program transformation and
`instruction scheduling
`·:· complete audio/video system + CPU on single chip
`- software controlled AudioNideo synchronization
`- DMA mastering 110 units
`- DMA mastering co-processors (image & VLD co-processor)
`·:· 100 MHz SDRAM interface, under worst-case conditions
`
`Microprocessor Forum
`
`12-9
`
`October 10-11, 1995
`
`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
`
`Trimedia
`
`A "Family" of software compatible media processors
`·:· continuous renewal of CPU cores
`·:· interfaces addressing different market segments (PC, settop, TV, .. )
`·:• mainline & derivative product strategy
`·:· a single architecture for all audio, video, graphics, communication, user(cid:173)
`interface and system control
`Superior flexibility and programmability
`·:· "Any" compression standard
`·:· All programming in Standard C
`·:• Applications/libraries available for Audio, Video, Graphics
`·:• SUN and PC hosted programming environment
`·=· Automatic fine-grain parallelization
`·:· Sophisticated source-level debugging of Device Under Test
`
`)
`
`Microprocessor Forum
`
`12-10
`
`October 10-11, 1995