PCI System
`Architecture
`
`Third Edition
`
`MINDSHARE, INC.
`
`TOM SHANLBY
`
`AND
`.
`DON ANDERSON
`
`A
`
`V7
`
`SEAVERWNO3
`
`Addison-Wesley Publishing Company
`
`Reading, Massachusetts 0 Menlo Park, California 0 New York
`
`Don Mills, Ontario 0 Wokingham, England 0 Amsterdam
`
`Bonn 0 Sydney 0 Singapore 0 Tokyo 0 Madrid - San Juan
`Paris - Seoul - Milan - Mexico City - Taipei
`
`‘
`Page1of235
`j—j. on-inn“
`
`ZTE EXHIBIT 1019
`
`ZTE EXHIBIT 1019
`
`

`
`Many of the designations used by manufacturers and sellers to distinguish their
`products are claimed as trademarks. Where those designations appear in this Hook,
`and Addison-Wesley was aware (it a trademark claim, the designations have been
`printed in
`capital letters or all capital letters.
`
`Theauthorsandpublislieratavetakencareiriprejiuatiorioitliisbooigbutuiakeno
`expressedarimpliedwanantyofanykindand assumenorspanaibilityfocrerrorsor
`oinisaions. No liability is assumed for incidental or consequential damages in
`cormectlnnwithorarisirtgoutoftlieuaeoftlielnformaticn orprograinaconialned
`herein.
`.
`
`Library of Congress Cataloging-in-Publication Data
`
`ISBN: 0-201-40993-3
`
`Copyright 0 1995 by Mindshare, Inc.
`
`All dghts reserved. No yart of this publication may be reproduced, stored in
`reuievalsyatem,or&uundtted,h1myfmmorbyanymeum,elecumfic,unchniml,
`photocopying, recording, or otherwise, without the prior writtm
`pennhsionofthe.
`publisher. Printed in the United States of America. Published simultaneously in
`Canada.
`.
`-
`
`Sponsoring Editor: Keith Wollman
`Project Managr: Eleanor McCarthy
`Production Coordinator: Dora 1.. Ryan
`Cover design: Barbara T. Atkinson
`Set in 10 point Palatino by Mindslme. Inc.
`
`1 23456789-MA-9998979695
`
`Firstprinting,February‘l995
`
`Addiaozrwesley books are available for bulk purchases by oorporatiom, institutions.
`and other organizations. For more information please contact the Corporate.
`Government, and Special Sales Department at (800) 238-9682.
`
`Page 2 of 235
`
`

`
`To Nancy and Sheryl, two very understanding ladies.
`
`Page 3 of 235
`
`.}V — , ...- ..
`
`

`
`Content:
`
`Contents
`
`one-‘Iu.IIv_ae.u_IIIIeuunIuIIs_IuuIo4nI_u_IIe.u:uoee_uens~no-_e-LoganIoeggutruss:-ooueuuguug-yam I
`
`About This Book
`The Mindshare Architecture Series ....................................................................... 1
`
`Organization of This Book ................................................................................. 2
`Who this Book is For .............................................. .......................................... 2
`
`PrerequisiteKnuwledge.................................................................................3
`
`Object Size Designations.........................................................................................L........3
`Documentation Conventions............................
`3
`Hex Notation ............................................................................................
`.......... ..3
`
`............................ ..3
`.......................................................................
`Binary
`Decimal Notation ........
`....
`............................................................
`.......
`...... ..-1
`
`Signal Name Representation .....................................................................................-1
`Identification of Bit Fields (logical groups of bits or signals) ......................
`.
`.
`We Want Your Feedback...................................................................................................4
`Bulletm Board........................................................................................................5
`‘
`'
`' ddress
`'
`5
`MaI1mgA
`....................................................................................................
`
`Part I: Introduction to the Local Bus Concept
`
`CHAPTER 1: The Problem
`OIOIICIIDIOIOIIII.OIIIIIOO%OIOO0hOCOOOOIIIO0OO60tl0IOIO03.0.9.Qoogjooogjoqpouoouoouuoouoogoonjooqgp 9
`
`9
`Graphics Interface Performance Requirements.................................................
`SCSI Performance Requirements ............................................................................ 10
`Network Adapter Performance Requirements.............................................;.....
`10
`)(-Bus DevicePerformanoe Constraints ................................................................... 10
`
`Expulsion Bus Transfer Rate Limitations ...................................mmmmmm ................ 13
`SA Expansion
`.....
`.....
`.........
`.............................
`................................. 13
`EISA Expansion
`....
`..........................................................................................13
`Micro Channel Architecture Expansion Bus.............................................................. 13
`
`Teleconferencing Performance Requirements ....... ............................................ 14
`
`CHAPTER 2: Solutions, VESA and PCI
`Graphics Accelerators: Before Local Bus ........................................................................ 19
`Local Bus Coueept........................................................................................... 20
`Direct-Connect Approach.................................................................................. 20
`Bufiered Approach...........
`.......................................
`......................................... fl
`Workstation Approach .....................
`.................................................
`............. 24
`
`
`
`I I I I I I I
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`I I I I I I I
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`I
`I
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`I I
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`I
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`I I
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`Page 4 of 235
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`G V
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`L
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`IOOI!OQIQICIOIIQQIIIQCIIIIlIlI!OItIUllIOOIO-IDOIIIO-ltdIIOXIOCOOVOIOIOOOIOIfiOllIOOIQIOOIO90Il
`
`Logic Cost .............................................,...............................
`Performance........................................................................
`
`.........................
`...............
`.........
`
`Longevity ................................................................................. ... ..................
`Teleconferendng Support......
`..........................................................................
`nnnnnn15::uuuuuuuuuuuuuuu070nnnnnnnnnnu:nnnnnnnnnnnnnnnnnnnnnnnnnnon;aaaaaaup-‘nnnnu_nnnnnnu_u '
`Add-in Connectors...........................................................................................
`
`Auto-Configuration......................................................................................
`Revision 2.0 V1. Specification ..........................................................................
`PC! Bus Solution.........................................................................................................
`Marke! Niche for PCI and VESA VL........................................................................
`PCI Device ....................................................................................................
`
`Specifications Book is Based on ......................................................................
`Obtaining PCI Bus Speci£ication(s) ......................................................................
`
`Part II:'Revision 2.1 Essentials
`
`
`CHAPTER 3: Intro to PCI Bus Operation
`Burst 'nanafer...........................................................................................
`Initiator, Target and Agents......................................................................................
`Single vs. Multi-Function PC! Device:..................................................................
`nu-ouunnuauenun-nun:nnuuootu-coooonluu-I
`PC! Bus C'.1ock..................................................
`Address Phase ...................§...............................................
`
`.................................................................
`Claiming the Transaction...........
`Data Phaets) ...................................................
`Tnnsution Duration...............................................................................................
`
`Transaction Completion and Return of Bus In Idle
`0
`-1nun-Iluu-uonoluucuonuuoouuMluooeuu-uuuoun-nu-nu uooocnuu--unouuoo-on-soc
`
`
`CHAPTER 4; Intro to Reflected-Wave Switching
`Each Trace 15 a Transmission Line ........................................;................................
`
`Old Method: Incident-Wave Switching“.........................................................
`PC] Method: Reflected-Wave Switching
`..............
`PC! Timing Characteristics
`.......................
`Introduction .............................................................................................. ..
`
`...............................................
`CI..KSig\al ..................;..........................
`Outputflmlng.................................................................................................
`mingnnnnnnnnnnouuuuunountnu uuuuuuuuuuuuuuuuuuunuuuuuuuunuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuno
`RS'l‘#/RBQ64#'I!ming .................................................................................
`onuoouunInnanoonuuocnnuouooutunanoulluocuoooohov-uoooooooool
`
`
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`Page 5 of 235
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`
`
`—
`
`7 Contents
`
`
`
`CHAPTER 5: The Functional Signal Groups
`Introduction .....................................................................................
`
`........ 53
`
`.
`
`System Signals .................................................................................................. 56
`.-.-Pcxc:1oc1¢signaL(cLK)..................e.............................,......................5e-~_._
`CLKRUN#Signal .....................................................................................................57
`General .............................................................................................. .;..................57
`meet Signal (RS'l'#) .....
`......
`................................................................................ 58
`Addresslbata
`58
`
`........................ 62
`Preventing Excessive Ciurent Drain-......................................
`'fi:ansaction Control Signals ..............................................
`..................
`.............63
`Arbitration Signals
`64
`...............
`Interrupt Request Signals ..........................................
`......................... 65
`mo: sinkOOOIDOIIIDOOOIIOCIIIIIIIIIIIIOIlllllliltlllilDOOQUOIIQIOOOOIIOCUIIIIIIIIIIDIICIIIIIIDlllviulltrflllulh
`Data Parity Error........................................................................................................ .. 65
`System Error ............................................................................................................ 66
`Cache Support (Snoop Result) Signals ..................................................................... ..67
`64-bit Extension Signals ................................................................................. 68
`Resource Locking............................................................................................. 69
`]'l'AGIBoundary Scan Signals .....................................................,..................... 70
`CD000!nonIIWenuonus-eneuoeo-ounsonnnu:no-onus-Inanuoouonus-oaoounuuouccccII71
`onnqpuonsunnnnnnnnnnnnnngauzennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnuunnneo 71
`Signal Types ...........................
`...............................
`...........
`..............................71
`Central Resource Functions ...................................
`...........................................72
`OthllociiICOIOCIIIIIIIIOIQIIIOOIIOOIOOIOOUOCOOMIIIIIOIIDIIIIVIIIUOIOOIIIIOOIIDOIIIMIIIIOOICOOIOIOOCUICIOII 73
`
`B ° O0 IIIIIIIIIIIIIIIIIIIIUIIIIUCIIIIIIVIOVUIUVOUIIIIIIIIIVIOIIOIUIQIIIII 0"llllllllllllllllllllllllIll!!!IIIIIIII II B
`Tuning Subtractive Decoder....................................................................................... 74
`Reading Timing Diagrams.........................................................
`........... 75
`
`
`CHAPTER 6: PCI Bus Arbitration
`Arbiter .....................
`.......................................................................
`
`.........79
`Arbitration Algorithm ...............................................................................
`so
`Example Arbiter wiflt
`B2.
`..............
`Master Wishes To Perform More Than One Transaction,...........
`-
`COIIIIIIIIIIIIIIOIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIICCIIIIIIIIIIIIIII00.. 32
`
`B“ P §II IIIIIOIOUVDQQDOIOCllIOIOOCOIOOIOIOIIIIODIOIIOIOOOIOOOIOIIOICOI‘IIOI‘IIIUD!00031000000000ICCOOOOIICOIOOIOCIIIIIIIIIIon 82
`RequestlGrant Timing.....................................................
`.......................................... 84
`Example of Arbitration Between Two Masters .....................
`......................
`85
`Bus Access Latency ....
`....
`........................
`......
`................. 89
`Master Latency Timer: Prevents Master From Monopolizing Bus .......................... 91
`Location and Purpose of Master Latency 'I‘imer................................................ 91
`
`
`
`.
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`_-
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`u - A.
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`6-
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`Page 6 of 235_
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`PCI Sgtem Architecture
`
`How LT Works .....................
`..........................
`.......
`...................................... 91
`Is Implementation of LI‘ Register Mandatory?................................................. 92
`Can LT Value Be Hardwired (mead-only)? .........................’.........................;...... 92
`How Does Configuration Software Determine Tlmalioe To
`Be Allocated To Master? .................................................................................. 92
`Treatment of Memory Write and Invalidate Command................................... 92
`Limit on Masters Latency ................................................................................. 93
`Preventing Target From Monopolizing
`93
`General ....................................................................................................... .. 93
`
`Target Latency on First Data Phase ................................................................ 95
`Options for Achieving Maximum 16 Clock Latency ........................................ .. 95
`Different Master Attempts Access To Device With
`Previously-Latched Request.............................................................................. 97
`Special Cycle Monitoringwhile Processing Request .................
`................. 97
`Delayed Request and Delayed Completion
`........................................... 97
`Handling Multiple Data Phases ..................................................................... 97
`Master or Target Abort Handling.....
`.........
`................................ .............. 97
`Commands That Can Use Delayed Transactions .............................................. 98
`Delayed Read
`.................................................................................. 98
`Request Queuing and Ordering
`98
`Locking, Delayed Transactions end Posted Writes ...................................... 103
`Fast Back-to-Back Tra.naactiona...................................................................,.................. 103
`Decision to Implement Fast Bnck—to-Back Capability
`106
`Scenario One: Master Guarantees Lack of Contention ......................
`............... .. 106
`How Collision Avoided Onsignala Driven By Master..................
`.............. 106
`How Collbion Avoided On Signals Drivm By‘l'arget................................... 107
`How Targets Recognize New Transaction Has Begun.................................... 108
`Fast Back-to-Back and Master Abort ...............................
`.........
`....
`........... 108
`
`110
`Scenario Two: Targets Guarantee Lack of Contention...................................
`111
`State of REQ# and GNTU During RST#.....................
`Pullups On RBQI From Add-In Connectors .................................................................. 112
`Broken Maa!er...................................................................................;........................-...
`
`....
`
`CHAPTER 7: The Commands
`Qnunenlouoonunnueulununnu-onnuuulnnauueauououonuulInuvnuuuuoouunnunuannu Iotlltduochilh
`
`"
`
` OIOOOOOOOOOOOOQCOOOOOOIOOOOCOQOCOIOCOOZOOOOOQIOOIDOIIIOOOOOIIIIICDIIOOOOODIOIAOII
`Introduction.....................................................................................................114
`
`llllllllllllllIIIIIOllllllllllllllllllDUOIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII oil
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence ........................... 115
`PCI Interrupt Acknowledge Transaction
`................................................
`......... 116
`IInonno-Iooooocooeuanqnuouunuloulu-nunuulouunannounce:Iunlnoouolulvouuuuuon
`
`viii
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`Page 7 of 235
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`WM
`121
`...............
`.....
`....................................................
`Special Cycle
`121
`Single-Data Phase Special Cycle
`Multiple Data PhaseSpecialCyI:leTransaction......................................."1122
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`Reading Memory....................................
`........................................................ .. 125
`
`
`
`.............................. 125
`Memory Read Line Command...................;...................
`Memory Read Multiple Command................................................................... 125
`Writing Memory............................................................................................... 126
`Memory Write Command ......................................................................... 126
`Memory Write and Invalidate Command....................................................... 126
`Problem ......................................................................
`.......................... .. 126
`
`Description of Memory Write and invalidate Command .......................... 127
`More Information On Memory Transfers ................................................................. 127
`Configuration Read and Write-Commands .................................................................... 128
`Duel-Address Cycle................................................................................................ 128
`Reserved Bus Commands .........................-.......................................................
`
`CHAPTER 8: The Read and Write Transfers
`some Basic Rule ............................................................................................................... 129
`
`Parity............................................................................................-......................................130
`Read Transaction...........................................
`.................................................... 130
`
`.............................................130
`Description............................................
`Treatment of Byte Enables During Read or Write........................................... 134
`BybeEnsbleSettingsMayVaryfromDatsPhasetoData Phase...................
`134
`DataPhasewith No ByteBnablesAsserted ........................................................135
`Target with Limited Byte Enable Support..................................................
`136
`Rule for Sampling of Byte Enables .........................................
`.................
`136
`Ignore Byte Enables During Line Read........................................................... 136
`Preietehing ..................................................................................................... 137
`Performance DuringRend'!'ransactions ................................................................ 137
`Tiafiacfionnmoaonouuuonwtwuouauuo-«nunssucuaoocuuuoouaouussnuIIonususuuououuno-onunoa
`
`..................... 139
`Dacription.......................................................................................
`Performance During Write Transactions .................................................................-. 144
`sssss nunuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu.--
`General ................
`......................................................................................... .. 146
`
`..................................................................................145
`Combining..............
`Byte Merging...............................................................................................147
`
`
`
`in
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`Page 8 of 235
`_ -2.2 .2}
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`.—
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`

`
` —
`
`PCI Szstem Architecture
`
`....... ..- 147
`Collapsing .......................................................................................
`Cache Line Merging......................................................................................... 147
`Addressing Sequence During Memory Burst
`............................. 148
`
`Linear and Cacheline Wrap Addressing..........
`....................................... 148
`‘ Target Response to ReservedSetting on AD[1:0]....................
`.............................. 150
`Do Not Mergeilh-ooessor I/O Writ into Single Bunt.Z.'....I......2;.:.;.;.....;...;......;;.:.a..z..150-
`PCI IIO
`150
`General.......................................
`150
`.....................................................................
`Situation Resulting in Target-Abort.. .......................................................................... 151
`I/O Address Management ................
`.................................................................. 153
`When 110 Target Doean't Support Mull!-Data Phase 'l'ranaactions............'................ 153
`AddraaIData Stepping .............................................................................-...................... 151
`Advantages: Diminished Current Drain and Crosstalk......................................... 154
`Why Targets Don't Latch Address During Stepping Process ............................. 155
`Data Stepping ...........
`...................................
`............................................
`155
`How Device Indicates Ability to Use Stepping ............
`................................ 155
`Designer May Step Address, Data, PAR (and PAR64) and IDSEI......................... 156
`Continuous and Discrete Stepping ........................................................................ 156
`Disadvantages of Stepping.............................................................................. 157
`Preemption While Stepping in Progress............................................................... 157
`Broken Master ...................
`..........................................................................
`158
`
`............................................................................ 159
`Stepping Example ....................
`When Not to Use Stepping.............................................................._...................... 161
`Who Must Support Stepping’? ......
`...................................................................... 161
` m l
`IIIOXDXIIIZOIIICOIOCDODIIOICIIOIIIIIDCOIIOCIIIIOOOIIIIIIUCIIIOCIIIIIIIIIIIIUID-IIICIIAII
`
`
`CHAPTER 9: Premature Transaction Termination
`Introduction..................................................................................................................163
`Master-Initiated Termination ........................................................................................... 163
`
`164
`Master-Preempted.............................................................................................
`Preemption During Timeslice....
`......
`............................................................ 164
`'I‘imesliee Expiration Followed by Poeunption.................................................. 165
`Master Abort: Target Doesn't Claim ‘Transaction ..................................................... 167
`Introduction
`...........................................
`.................................................. 167
`Master Abort on Single Data Phase ‘Transaction ................................................ 167
`Master Abort on Multi—Data Phase 'I}ansaction......................................
`159
`Action Taken byMasterinResponse to Master Abort .................................... ..171
`General .......................................................
`................................................. 171
`Special Cycle and Configuration Access ................
`.................................. 171
`Target-Initiated
`171
`STOP! Signal ............................................................
`................................................ 171
`
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`Page 9 of 235
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`'
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`Dlscormects...........................
`.....
`..........................................................172
`Description....................................................................................................... 172
`Reasons Target Issues Disconnect...................................................................... 173
`Target Slow to Complete Data Phase.........
`.........................................
`173
`Memory Target Doesn't Understand Addressing Sequence ...................... 173
`'TransferCrcsses Over Target’s Address'B'onnd3uy..L.'.......'..'..........l.......... 173
`BurstMemoryTransferCrosaesCad\eLineBoundary.........................."174
`Type “A” Disconnect: Initiator Not Ready When Target Says STOP ............... 174
`Type "B" Disconnect: Initiator Ready When Target Says 3101’ ....................... 175
`Retry (Type C) Disconnect .........................................................
`........
`178
`Description........................................................................................................ 178
`Reasons Target Issues Retry ...................................................................... 179
`Memory Target Doesn't Understand Addressing Sequence
`................ 179
`Target Very Slow to Completefirst Data Phase..................
`............... 179
`Snoop Hit on Modified Cache Line............
`.....................
`..................... 179
`Resource Busy.........................
`.........................
`......................
`............... 180
`Memory Target Ioc1ned.........................................1............................... 180
`Retrylixamples............................................................................
`..............180
`Host Bridge Retry
`............................
`.................................... 182
`Target Abort ..........................
`...........................
`..........................
`........ .. 182
`Description....................
`....................
`...................................... .. 182
`Reasons Target Issues Target Abort ..............
`..................................... 183
`Br-oken'I'arget.............................................................................~......183
`1/0 Addressing Error ......................................................................... 183
`Address Phase Parity Error .................................................................... 183
`Master's Response to Target Abcrt.....................................................
`............. 183
`Target Abort Example.............
`........................................................
`183
`How Soon Does Initiator Attempt to Re-Establish Transfer After
`Retry or Disc<mnect?.......................................................
`.............................. 185
`Target-Initiated Termination Summary ..............
`.................
`.......................... 185
`
`
`CHAPTER 10: Error Detection and Handling
`Introduction to PCI Parity........................................................................... 187
`Palm: Signal......................................................................................................................189
`Data Parity .........-............................
`..........s........................................1s9
`Data Parity Generation and Checking on
`d...........................................
`........ 189
`Introduction ....................................................................................................
`189
`
`190
`.......................
`Example Burst Read .........................................................
`Data Parity Generation and Checking out Write..................................................... 193
`Introduction ............................................................................................. 193
`
`Example Burstwrite .................................................................................... 193
`
`
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`xi
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`Page 10 of 235
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`PCI System Architecture
`
`Data Parity Reporting ................................................................................................ 196
`General ............................................................................................................... 196
`
`........ ..-.......... 196
`..............................................
`Parity Error During Read ...........
`Parity Error During Write .......................................
`...................... 197
`Data Parity Error Recovery ...............
`..........
`..........................
`...........
`......... 198
`Special C5": DI-fa Parity
`....'.;........7...'.......;:.:.....'......:;.:.. 199 ‘
`Devices Excluded from PERI!!! Requirement............................................................ 199
`Chipsels ...........
`.......................................................
`............................ 200
`Devices That Don't Deal with 05/Application Program or Data ................ 200
`Simn-nan4o¢O0vOlvOlOO¢0lOl0MIG!IDCIIiildlhooououooaooouI-a-onounolntuo-IonIncnnpnno-uIolnttlullvouuinvbonuoovfioti
`Address Parity...................................................................................
`............. 202
`Address Parity Generation and Checking............................................
`Address Parity Error Reporting“.......................................................................... 202
`System Errors....................................................................................................
`.........205
`' General ...........
`.........................
`....................
`................................................ 205
`Address Phase Parity Error....................................................................................... 205
`Data Parity Error During Special Cycle .........................
`........................................ 205
`Target AbortDetection........................................................................................205
`Other Possible Causes of System Error.....
`...........
`..................................... .. 205
`Devices Excluded from SERRI Requirement ................................................ 205
`
`
`CHAPTER 11: Interrupt-Related Issues
`
`‘
`
`KI
`PCI
`
`IIDOIIOIIIICIIDICIOIIOIIIIIIIIIIIIIIIIIOIIIIllIO0IIOIOICCOIIIIIOOIDIIIIIOOQOOAICIOIOIIIEIICIIM
`IIIIIIIIIIIIIIIIIOOOIIBIIIIIIIIIIIIUIIIOOUIICVIIVIOIIDIIIIIIIVIOIOIIIIIICCICIIIIIOIIII
`
`Connection of IN'l’:¢ line: To System Board 'I'racer..................’............................... 209
` pt
`I IOOIIOCIIOIOCDODIIIOOIIIIIO‘IInotI0lDIt¢OOoQ¢¢d4OOlD0OoOO0IIIIIIIII!OIIII‘OOCICIOOOOOOOIIIIIIQIIIICIlillluulll
`..........
`.......................................................................................... .. 210
`Platform ”I<nows" Interrupt Trace Layout ..................
`................
`...................... 216
`Well-Designed Platform Has Programmable Interrupt Router............................... 216
`Interrupt Routing Information ................................................................................ 216
`PCI Interrupts Are Shaxeeble ..........................................................217
`"Hooking" the Interrupt ................................................................................................... 217
`Interrupt
`..................
`..................218
`Gateral ....
`.......................................................................................................... 218
`
`............................. 219
`Step One: Initialize All Entries In Table To Null Value ............
`Step Two: Initialize All Entria For Embedded Devices ........................................ 219
`Step '11:uee: Hook Entries For Embedded Device BIOS Routines ......................... 219
`Step Four: Perform PCI Device Scan ...................................................................... 220
`Step Five: Perform Expansion Bus ROM Scan................................
`..................... 221
`Step Six: Load Operating System................................
`........................................... 221
`A Linked-l.iat Has Been Built for Each Interrupt Level ........................................... 222
`
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`Page 11 of 235
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`Contents
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