UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
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`ASUSTEK COMPUTER, INC. and ASUS COMPUTER INTERNATIONAL,
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`Petitioners
`
`v.
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`AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.,
`
`Patent Owner
`
`
`
`Case: IPR2016-00646
`
`U.S. Patent No. 5,870,087
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`
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`PATENT OWNER’S EXHIBIT NO. 2003
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`DECLARATION OF SCOTT ACTON, PH.D. UNDER 37 C.F.R. § 1.68
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`TABLE OF CONTENTS
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`SCOPE OF THE DECLARATION ................................................................ 4 
`I. 
`EXPERT QUALIFICATIONS AND BACKGROUND ................................. 5 
`II. 
`III.  MATERIALS REVIEWED ............................................................................ 9 
`IV.  SUMMARY OF OPINIONS ......................................................................... 10 
`V.  UNDERSTANDING OF LEGAL PRINCIPLES ......................................... 10 
`A.  Anticipation ......................................................................................... 11 
`B. 
`Obviousness ......................................................................................... 11 
`C. 
`Claim Construction .............................................................................. 13 
`VI.  PERSON OF ORDINARY SKILL IN THE ART ........................................ 13 
`VII.  OVERVIEW OF THE ʼ087 PATENT .......................................................... 15 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 18 
`IX.  ANTICIPATION ANALYSIS ...................................................................... 21 
`A. 
`Count 2 ................................................................................................ 21 
`1. 
`Independent Claims 1, 10, and 16 ............................................. 21 
`2. 
`Dependent Claim 7 ................................................................... 28 
`3. 
`Dependent Claim 11 ................................................................. 30 
`4. 
`Conclusion on Count 2 .............................................................. 31 
`X.  OBVIOUSNESS ANALYSIS ....................................................................... 32 
`A.  Motivation to Combine ....................................................................... 32 
`B. 
`Count 3 ................................................................................................ 33 
`1. 
`Independent Claims 1, 10, and 16 ............................................. 33 
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`C. 
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`2. 
`Dependent Claim 7 ................................................................... 39 
`Dependent Claim 8 ................................................................... 40 
`3. 
`Dependent Claim 11 ................................................................. 43 
`4. 
`Conclusion on Count 3 .............................................................. 45 
`5. 
`Count 5 ................................................................................................ 46 
`1. 
`Dependent Claim 7 ................................................................... 47 
`2. 
`Dependent Claim 8 ................................................................... 48 
`3. 
`Conclusion on Count 5 .............................................................. 50 
`Count 6 ................................................................................................ 51 
`1. 
`Dependent Claim 7 ................................................................... 52 
`2. 
`Dependent Claim 8 ................................................................... 53 
`3. 
`Conclusion on Count 6 .............................................................. 55 
`Conclusion on Obviousness ................................................................ 56 
`E. 
`XI.  CONCLUSION .............................................................................................. 56 
`
`D. 
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`I, Scott Acton, being over the age of 18 and competent to make the statements
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`herein, hereby declare the following:
`
`I.
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`SCOPE OF THE DECLARATION
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`1.
`
`I have been retained on behalf of Patent Owner Avago Technologies
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`General IP (Singapore) Pte. Ltd. (“Patent Owner”) as an expert consultant to
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`analyze and provide my opinions on the validity of U.S. Patent No. 5,870,087 (the
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`“ʼ087 Patent”), and such other topics as addressed in this report.
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`2. As part of this work, I have been requested by counsel for Patent
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`Owner to study the challenged claims of the ʼ087 Patent and compare them with
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`the grounds identified by Petitioners ASUSTeK Computer, Inc. and ASUS
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`Computer International (collectively, “Petitioners”) and instituted by the Patent
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`Trial and Appeal Board.
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`3.
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`I have prepared this declaration summarizing certain of my opinions
`
`regarding this subject matter and its relevance to the validity of the ʼ087 Patent.
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`4.
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`If called upon to do so, I am prepared to testify as an expert witness in
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`this regard.
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`5.
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`This declaration is based on information currently available to me. To
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`the extent that additional information becomes available, I reserve the right to
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`continue my investigation and study, which may include a review of documents
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`and information that may be produced, as well as testimony from depositions that
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`have not yet been taken.
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`II. EXPERT QUALIFICATIONS AND BACKGROUND
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`6.
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`I am qualified by education and experience to testify as an expert in
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`the field of signal processing, including signal, image, and video processing.
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`Attached as Attachment A is a copy of my curriculum vitae detailing my
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`experience and educational background. Additionally, I provide the following
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`overview of my background as it pertains to my qualifications for providing expert
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`testimony in this matter.
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`7.
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`I am a Professor at the University of Virginia in the Electrical and
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`Computer Engineering Department. I have been at the University of Virginia since
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`2000. I am currently the Director of the Virginia Image and Video Analysis
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`(VIVA) laboratory. My area of expertise is signal, image, and video processing. I
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`have taught signal processing and image and video processing at the graduate level
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`for over twenty years. My experience in the signal processing research area dates
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`back to 1988, when I joined the Laboratory for Vision Systems (now called the
`
`Laboratory for Image and Video Engineering) at the University of Texas at Austin.
`
`I hold M.S. and Ph.D. degrees from the University of Texas at Austin in Electrical
`
`and Computer Engineering. The concentration area of my graduate work was
`
`image and video processing. I hold a B.S. degree from Virginia Tech in Electrical
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`Engineering. I spent a year of postdoctoral study with the Center for Space
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`Research in Austin, Texas.
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`8.
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`I am currently the Editor-in-Chief of IEEE Transactions on Image
`
`Processing. This journal is the top journal for multidimensional signal processing
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`in the world. The journal has an impact factor above 3.7, receives approximately
`
`2,000 submissions per year, and accepts roughly a quarter of these submissions.
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`As Editor-in-Chief, I manage a dozen Senior Area Editors and approximately
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`seventy-five Associate Editors.
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`9.
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`For my work in signal, image, and video processing, I was named an
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`IEEE Fellow. The distinction of Fellow in the IEEE is capped at a maximum of
`
`one Fellow for every 1,000 members.
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`10.
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`I have over 275 publications in the area of image and video
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`processing. A complete list of my publications, including all publications I have
`
`authored in the previous ten years, is set forth in Attachment A.
`
`11.
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`I have industry experience with AT&T, the Mitre Corporation, and
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`Motorola, Inc. I have academic experience as a research assistant at the University
`
`of Texas at Austin, as a professor with Oklahoma State University, and as a
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`professor at the University of Virginia. In 2007-2008, I spent an academic
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`sabbatical at the University of New Mexico.
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`12. As both a consultant and as someone who has taught many courses in
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`this area through the years, I am intimately familiar with the issues and technology
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`relating to image and video processing. I have personally been involved with the
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`design and development of several signal processing systems while working at the
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`Laboratory for Image and Video Engineering, directing the Oklahoma Imaging
`
`Laboratory, and directing the Virginia Image and Video Analysis laboratory. My
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`software systems have been deployed in industry and in government. I am
`
`qualified to testify as an expert on matters related to the ’087 Patent.
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`13. For my study and testimony in this case, I am being compensated at a
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`rate of $350 per hour plus reimbursement for usual business expenses, which is my
`
`standard and customary practice. My compensation is not dependent on the
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`outcome of this matter.
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`14. During the previous four years, I have testified as an expert at trial or
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`by deposition in the following cases:
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` In re Certain Elec. Imaging Devices (Flashpoint Tech., Inc. v.
`
`HTC Am., Inc. et al.)
`
`No. 337-TA-726 (ITC)
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`Retained by King and Spalding on behalf of Respondents Nokia
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`Corp. and Nokia, Inc.
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`Retained by Perkins Coie on behalf of Respondents HTC Am., Inc.
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`and HTC Corp.
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`Retained by Greenberg Traurig on behalf of Respondents LG
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`Elecs. MobileComm U.S.A., Inc.; LG Elecs. U.S.A., Inc.; and LG
`
`Elecs., Inc.
`
` In re Certain Elec. Imaging Devices ( Flashpoint Tech., Inc. v.
`
`FutureWei Techs., Inc. d/b/a Huawei Techs. (USA) et al.)
`
`No. 337-TA-850 (ITC)
`
`Retained by Perkins Coie on behalf of Respondents HTC Am.,
`
`Inc.; HTC Corp.; Pantech Co., Ltd.; and Pantech Wireless, Inc.
`
` In re Certain Audiovisual Components & Prods. Containing the
`
`Same (Agere Sys., Inc. v. Funai Corp., Inc. et al.)
`
`No. 337-TA-837 (ITC)
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`Retained by Kilpatrick, Townsend & Stockton on behalf of
`
`Complainants Agere Sys., Inc. and LSI Corp.
`
` MedioStream Inc. v. Microsoft Corp. et al.
`
`No. 2:08-cv-00369-CE (E.D. Tex.)
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`Retained by Covington and Burling on behalf of Defendant
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`Microsoft Corp.
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` Avago Technologies General IP (Singapore) PTE Ltd. v. ASUSTeK
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`Computer, Inc. et al.
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`No. 3:15-cv-04525-EMC (N.D. Cal.)
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`Retained by Kilpatrick, Townsend & Stockton on behalf of
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`Plaintiff Avago Technologies General IP (Singapore) PTE Ltd.
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`III. MATERIALS REVIEWED
`
`15.
`
`In forming my opinions, I reviewed the following materials:
`
` Petition for Inter Partes Review of U.S. Patent No. 5,870,087
`
`Under 35 U.S.C. § 312 and 37 C.F.R. § 42.104 (Paper 3) and the
`
`exhibits thereto (Exs. 1001 to 1013);
`
` Patent Owner’s Preliminary Response Under 37 C.F.R. § 42.107 to
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087 and
`
`the exhibits thereto (Exs. 2001 to 2002);
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` Decision on Institution of Inter Partes Review of U.S. Patent No.
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`5,870,087 Under 37 C.F.R. § 42.108;
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` Deposition Transcript of Richard Kramer dated November 21,
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`2016 (Ex. 2004);
`
` Chia-Hsing Lin et al., Low Power Design for MPEG-2 Video
`
`Decoder, 42 IEEE Transactions on Consumer Electronics 513
`
`(1996) (Ex. 2005);
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` Sung-Chul Han et al., An ASIC Implementation of the MPEG-2
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`Audio Decoder, 42 IEEE Transactions on Consumer Electronics
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`540 (1996) (Ex. 2006); and
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` Deposition of Scott Acton, Ph.D. dated September 14, 2016 in
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`Avago Technologies General IP (Singapore) PTE Ltd. v. ASUSTeK
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`Computer, Inc., No. 3:15-cv-04525-EMC (N.D. Cal.).
`
`16.
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`I intend to continue to review materials that may inform my opinions
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`expressed in this Declaration. I reserve the right to amend or supplement this
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`Declaration and to rely on additional materials and testimony brought to my
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`attention during the course of this proceeding.
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`IV. SUMMARY OF OPINIONS
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`17. Based on the materials that I have reviewed, the analyses I have
`
`performed, the positions I have summarized within this declaration, and my
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`personal experience, I have formed at least the opinions listed below.
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`18. Petitioners have not shown by a preponderance of the evidence that
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`any challenged claim of the ʼ087 Patent is invalid based on anticipation or
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`obviousness. I detail the support for my conclusion in the following paragraphs.
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`V. UNDERSTANDING OF LEGAL PRINCIPLES
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`19. The paragraphs in this section represent my understanding of the
`
`applicable legal standards. Such understanding is premised entirely on direction
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`provided by Patent Owner’s counsel, and does not reflect any independent
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`assessment by me of the relevant legal standards.
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`A. Anticipation
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`20.
`
`I understand that a claim is anticipated only if each and every element
`
`as set forth in the claim is found, either expressly or inherently described, in a
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`single prior art reference. I understand that the identical invention must be shown
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`in as complete detail as is contained in the claim. I understand that unless a
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`reference discloses within the four corners of the document not only all of the
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`limitations claimed but also all of the limitations arranged or combined in the same
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`way as recited in the claim, it cannot be said to prove prior invention of the thing
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`claimed and, thus, cannot anticipate under 35 U.S.C. § 102.
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`21.
`
`I understand that in an inter partes review, a claim of unpatentability
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`based on alleged anticipation must be proved by a preponderance of the evidence.
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`B. Obviousness
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`22.
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`I understand that a patent claim is invalid for obviousness only if the
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`invention described in the claim would have been obvious to a person of ordinary
`
`skill in the art at the time the invention was made. I understand that the
`
`fundamental question in an obviousness analysis is whether the claimed invention
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`would have been obvious to a person of ordinary skill in the art, taking into
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`account (1) the scope and content of the prior art, (2) the differences between
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`the prior art and the claimed invention, (3) the level of ordinary skill in the
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`art, and (4) any objective considerations of non-obviousness, including
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`commercial success of products or processes using the invention, long felt need for
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`the invention, failure of others to make the invention, industry acceptance of the
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`invention, and copying of the invention by others.
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`23.
`
`I further understand that multiple references can be combined with
`
`one another, or with the knowledge of a person of ordinary skill in the art, to
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`render a claim obvious. However, obviousness is not established simply because
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`all of the elements of a patent claim can be found in the prior art. There must be
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`a reason that would have prompted a person of ordinary skill in the relevant field
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`to combine the elements in the way the claimed new invention does.
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`24.
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`In addition, I understand that obviousness of a patent cannot properly
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`be established through hindsight, and that elements from different prior art
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`references, or different embodiments of a single prior art reference, cannot be
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`selected to create the claimed invention using the invention itself as a roadmap.
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`The claimed invention as a whole must be compared to the prior art as a whole,
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`and courts must avoid aggregating pieces of prior art through hindsight, which
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`would not have been combined absent the inventor’s insight.
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`25.
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`I understand that in an inter partes review, a claim of unpatentability
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`based on alleged obviousness must be proved by a preponderance of the evidence.
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`C. Claim Construction
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`26.
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`I understand that, in inter partes review, claims of an expired patent
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`are given their ordinary and customary meanings, as would be understood by a
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`person of ordinary skill in the art at the time of the invention, having taken into
`
`consideration the language of the claims, the specification, and the prosecution
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`history of record. I understand that claims should always be read in light of the
`
`specification and teachings in the underlying patent.
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`VI. PERSON OF ORDINARY SKILL IN THE ART
`
`27.
`
`I understand that certain issues in the inter partes review involve the
`
`concept of a “person of ordinary skill in the art.” I also understand that the
`
`following appears in the U.S. Patent and Trademark Office Manual of Patent
`
`Examining Procedure at Section 2141.00:
`
`The person of ordinary skill in the art is a hypothetical person who is
`presumed to have known the relevant art at the time of the invention.
`Factors that may be considered in determining the level of ordinary
`skill in the art may include: (1) “type of problems encountered in the
`art;” (2) “prior art solutions to those problems;” (3) “rapidity with
`which innovations are made;” (4) “sophistication of the technology;”
`and (5) “educational level of active workers in the field.” In re
`GPAC, 57 F.3d 1573, 1579 (Fed. Cir. 1995). “In a given case, every
`factor may not be present, and one or more factors may predominate.”
`
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`Id. See also Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc.,
`807 F.2d 955, 962 (Fed. Cir. 1983).
`
`28.
`
`In my opinion, a person of ordinary skill in the relevant art at the time
`
`of the invention of the ’087 Patent would be someone with a bachelor’s degree in
`
`electrical engineering, computer engineering, computer science, or equivalent, and
`
`at least two years of industry experience or graduate studies in developing
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`image/video processing software/hardware systems.
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`29.
`
`I make this declaration as someone who actually possessed at least the
`
`knowledge of a person of ordinary skill in the art at the time the application that
`
`led to the ’087 Patent was filed.
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`30.
`
`I disagree with Petitioner’s expert Mr. Kramer’s definition of a person
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`of ordinary skill in the art, Ex. 1003 at ¶ 19, to the extent that it does not require
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`any experience related to the development of video decoders or other image/video
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`processing software/hardware systems. However, my opinions would not change
`
`if the person of ordinary skill in the art only had at least two years of industry
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`experience or graduate studies in developing processor systems involving memory
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`architectures but did not have any specific experience related to video decoders or
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`other image/video processing systems.
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`VII. OVERVIEW OF THE ʼ087 PATENT
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`31.
`
`I understand that the ’087 Patent was filed on November 13, 1996 and
`
`that the ’087 Patent issued on February 9, 1999.
`
`32.
`
`I have reviewed the specification and file history of the ’087 Patent.
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`33. The ’087 Patent discloses and claims structures, functions, and
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`methodologies for decoding an encoded multimedia data stream. Specifically, the
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`’087 Patent describes novel video decoder systems and methods for performing
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`video decoding that efficiently utilize memory.
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`34. Video decoder systems include several components such as a channel
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`receiver that receives an encoded multimedia data stream, transport logic coupled
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`to the channel receiver that demultiplexes the multimedia data stream into separate
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`audio and video data streams, a video decoder, a system controller that controls
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`operations within the video decoder system, and memory.
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`35. Similarly, methods for performing video decoding include steps such
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`as receiving an encoded multimedia data stream, demultiplexing the encoded
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`multimedia data streams, decoding the encoded multimedia data streams,
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`controlling operations within the decoder system, and accessing and storing data in
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`memory. A more detailed description of the Moving Picture Expert Group
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`(“MPEG”) compression standards in existence at the time of the ’087 Patent is
`
`provided at column 2, line 21 through column 4, line 27 of the ’087 Patent. This
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`discussion includes a summary of some of the steps needed to decode an MPEG
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`encoded stream.
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`36. The video decoder systems and methods for performing video
`
`decoding disclosed in the ’087 Patent improve video (MPEG) decoding by
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`utilizing what is alternately referred to in the ’087 Patent as “unified memory,”
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`“single memory,” or “single unified memory.” For simplicity, I refer to the
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`memory structure of the ’087 Patent in this Report as “unified memory.”
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`37. The ’087 Patent discloses that the unified memory may be comprised
`
`of one or more memory chips. For example, Figure 3 of the ’087 Patent, which is
`
`reproduced below, depicts a 16Mbit SDRAM (item 212) that is consistent with a
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`memory configuration of four ranks (i.e., chips).
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`38. Similarly, Figure 4 of the ’087 Patent, reproduced below, depicts
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`frame store memory 212 in a manner consistent with a memory having more than
`
`one memory chip or bank.
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`
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`39. Although, as is shown in Figures 3 and 4, more than one memory chip
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`may be utilized, the multiple memory chips function as a unit. The unified
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`memory structure described in the ’087 Patent thus allows for a reduction in the
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`total memory needed for the video decoder system and simplifies system design.
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`40.
`
`Indeed, the ’087 Patent discloses that prior MPEG decoder systems
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`“have generally used a frame store memory for the MPEG decoder motion
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`compensation logic which stores the reference frames or anchor frames as well as
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`the frame being reconstructed.” See Ex. 1001 at 4:29-32. Additionally, these
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`decoder systems “have also generally included a separate memory for the transport
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`and system controller functions” because size limitations prevented the memories
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`from being combined. See id. at 4:33-36. Additional memory adds additional cost
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`to the system. Thus, in addition to reducing total memory needed for the decoder
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`system and simplifying system design, the memory structure described in the ’087
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`Patent reduces the cost of the video decoder system.
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`VIII. CLAIM CONSTRUCTION
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`41.
`
`It is my opinion that, should the Board construe the claim term
`
`“memory” / “first unified memory,” the ordinary and customary meaning of that
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`term, as would be understood by a person of ordinary skill in the art having taken
`
`into consideration the intrinsic evidence, is “memory functioning as a unit.”
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`42. With my understanding of claim construction principles, I have read
`
`the specification and prosecution history of the ’087 Patent in view of Petitioners’
`
`proposed construction of “memory” / “first unified memory,” i.e., “a single
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`memory for use by transport, decode, and system controller functions.” Based on
`
`my review of the patent specification and its prosecution history, it is my opinion
`
`that Petitioners’ proposed construction is incorrect.
`
`43. The specification of the ’087 Patent uses the terms “memory,” “single
`
`memory,” and “unified memory” interchangeably. These terms are used
`
`throughout the specification to indicate that the memory of the video decoder
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`system (including MPEG decoder systems) functions as a unit. There is no
`
`indication that the memory is limited to a single structure. Indeed, the figures of
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`the ’087 Patent counsel otherwise. For example, in Figure 3, shown below, the 16
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`Mbit SDRAM identified by reference number 212 is comprised of four memory
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`chips coupled together to make a unified whole.
`
`
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`If the memory were limited to a single memory chip, memory 212 would have
`
`been depicted with a single chip.
`
`44. That the memory is not limited to one memory chip is further
`
`confirmed by Figure 4, reproduced below, which depicts Frame-store Memory 212
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`as being composed of two memory chips.
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`These memory chips function as a unit and form a unified memory. Again, in my
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`opinion, if the memory of the ’087 Patent was limited to a single memory chip, the
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`Frame-store Memory 212 in Figure 4 would have been depicted with one memory
`
`chip, rather than the two shown in Figure 4.
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`45. Nothing the prosecution history of the ’087 Patent leads me to a
`
`different conclusion. Throughout the application process, the patentee’s
`
`correspondence with the U.S. Patent and Trademark Office with respect to the
`
`memory was consistent with how the memory was referenced in the specification.
`
`The patentee did not ascribe a specific definition to the term “memory” / “first
`
`unified memory” that would impart to those terms a meaning different from the
`
`plain and ordinary meaning—“memory functioning as a unit.”
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`46. Petitioners’ proposed construction would import limitations from the
`
`specification into the claims. It is true that the specification of the ’087 Patent
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`discusses the use of a Samsung KM416S1120AT-12 SDRAM in the preferred
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`embodiment. Nothing in either the specification or the prosecution history of the
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`’087 Patent, however, indicates that the patentee was limiting his invention to this
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`embodiment or to a memory comprised of a single memory chip.
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`47. Accordingly, for purposes of this declaration, I have used the ordinary
`
`and customary meaning of “memory” / “first unified memory” as would be
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`understood by one of ordinary skill in the art in the context of the ’087 Patent’s
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`disclosure—i.e., “memory functioning as a unit.”
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`IX. ANTICIPATION ANALYSIS
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`A. Count 2
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`48.
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`I have reviewed Fujii (Ex. 1005). I understand Fujii, and it is my
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`opinion that Fujii does not anticipate any of the challenged claims.
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`1.
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`Independent Claims 1, 10, and 16
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`49.
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`Independent claim 1 of the ’087 Patent includes the feature “wherein
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`the transport logic is operable to access the memory to store and retrieve data
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`during demultiplexing operations.” Independent claim 10 includes the feature
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`“where said demultiplexing one or more multimedia data streams from the encoded
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`stream operates using a first unified memory.” And independent claim 16 of the
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`’087 Patent recites “wherein the transport logic is operable to access the memory to
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`store and retrieve data during demultiplexing operations. Mr. Kramer discusses
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`these three features together and asserts that Fujii Figure 14 discloses that the
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`transport logic stores and retrieves data from the RAM during demultiplexing
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`operations. Ex. 1003 at ¶ 92-94. I disagree.
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`50. Mr. Kramer identifies the program packet filter 15 and interface unit
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`14 of Fujii Figure 11 (Fujii’s “second embodiment,” Ex. 1005 at 5:32-33), and the
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`channel demultiplexer 202 of Fujii Figure 17 (Fujii’s “fourth embodiment,”
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`Ex. 1005 at 5: 44-46), as the “transport logic” disclosed by Fujii. Ex. 1003 at ¶ 88.
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`Mr. Kramer identifies RAM 7 of Figure 11 and RAM 203 of Figure 17 as the
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`“single memory” in Fujii’s second and fourth embodiments, respectively. Id. Mr.
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`Kramer then opines that program packet filter 15 retrieves “PID data” from RAM 7
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`via microprocessor 12, and that “[t]he same analysis holds true for the Figure 17
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`embodiment.” Id. at ¶ 94.
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`51. The portion of Fujii cited by Mr. Kramer for the proposition that the
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`transport logic retrieves data from the RAM during demultiplexing operations
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`actually states otherwise. Specifically, Fujii states that in the second embodiment,
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`the microprocessor 12 reads PID data “from the program map table in RAM 12
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`[sic] and sets it to register 123,” and the “PID data is then supplied from the output
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`port to the PID filter 152.” Ex. 1005 at 10:1-5. In other words, as described in the
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`specification and clearly depicted in Figure 14 of Fujii, the PID filter 152 within
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`program packet filter 15 receives information from register 123 within
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`microprocessor 12, not from the alleged “single memory” RAM 7. Had the Fujii
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`author meant that the PID data came to PID filter 152 from the RAM over the bus,
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`it would be expected the author would have said so directly. Similarly, Fujii states
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`that in the fourth embodiment, “PID interface unit 219 [within channel
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`demultiplexer 202] receives the PID information from the microcomputer 204,”
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`Ex. 1005 at 12:40-42, not from the alleged “single memory” RAM 203.
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`52.
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`I have read Mr. Kramer’s deposition transcript. During his
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`deposition, Mr. Kramer implied that the statement in Fujii’s specification that “PID
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`data may be supplied via the data bus,” Ex. 1005 at 10:5-6, discloses that PID data
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`may be supplied directly over the data bus from RAM 7 to program packet filter
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`15. However, when read in context, that statement makes no such disclosure. The
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`entire relevant passage from Fujii’s specification reads as follows:
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`The microprocessor 12 reads the PID data corresponding to the user
`selected program #k from the program map table in RAM [7] and sets
`it to the register 123. The PID data is then supplied from the output
`port to the PID filter 152. This PID data may be supplied via the data
`bus.
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`Ex. 1005 at 10:1-6. This passage discusses the transfer of PID data from register
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`123 in microprocessor 12 to PID filter 152 in program packet filter 15, and the
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`statement that “PID data may be supplied via the data bus” is made in that context.
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`The passage does not disclose the transfer of PID data directly from RAM 7 to
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`program packet filter 15 over the data bus.
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`53. Moreover, Fujii’s specification teaches that PID data is received by
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`program packet filter 15 (second embodiment) and channel demultiplexer 202
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`(fourth embodiment) not during demultiplexing as required by ’087 Patent claims
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`1, 10, and 16, but rather before any demultiplexing of video and audio elements
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`occurs. To meet the ’087 Patent limitations requiring “the transport logic is
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`operable to access the memory to . . . retrieve data during demultiplexing
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`operations” (independent claims 1 and 16) and “where said demultiplexing . . .
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`operates using a first unified memory” (independent claim 10), the transport logic
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`would need to access memory to retrieve data during the process of separating the
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`multiplexed encoded stream into one or more individual streams. The PID data in
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`Fujii, however, is received by Petitioners’ identified “transport logic” before the
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`process of separating the multiplexed encoded stream into individual audio and
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`video streams begins.
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`54. Specifically, in Fujii’s second embodiment, a user selects a program
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`#k via user interface unit 13, which instructs the microprocessor 12 to supply PID
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`data used to derive packets of that program. See Ex. 1005 at 1:26-29 (“[A]
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`plurality of broadcast programs can be transmitted in a multiplex manner over a
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`single transmission channel.”); id. at 2:38-41 (“In response to an instruction
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`entered by a user via a user interface unit 13, the microprocessor 12 supplies PID
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`which is used for deriving the TS packet of a program . . . .”); id. at 9:12-14; id. at
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`10:1-4 (“The microprocessor 12 reads the PID data corresponding to the user
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`selected program #k from the program map table in RAM [7] and sets it to the
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`register 123.”). The first filtering step performed by program packet filter 15 is to
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`filter out packets of programs other than the program #k selected by the user. Ex.
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`1005 at Fig. 12; 5:34-35, 9:19-23 (“FIGS. 12A and 12B are diagrams used for
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`illustrating discrimination between packets of programs.” (emphasis added);
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`“FIGS. 12A and 12B illustrate a filtering process to be executed by the program
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`packet filter 15. FIG. 12A shows inputted TS packets, and FIG. 12B shows