`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`____________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`
`
`ASUSTEK COMPUTER, INC. and ASUS COMPUTER INTERNATIONAL,
`
`Petitioners
`
`
`
`v.
`
`
`
`AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.,
`
`Patent Owner
`
`____________
`
`
`
`Case: IPR2016-00646
`
`U.S. Patent No. 5,870,087
`
`____________
`
`
`
`PETITIONERS’ REPLY BRIEF
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`US Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313-1450
`
`
`
`

`

`
`
`TABLE OF CONTENTS
`
`I.
`
`STATEMENT OF RELIEF REQUESTED ........................................................... 1
`
`II.
`
`INTRODUCTION ...................................................................................................... 1
`
`III. CLAIM CONSTRUCTION ....................................................................................... 2
`
`IV. FUJII ANTICIPATES CLAIMS 1, 7, 10, 11, AND 16 (COUNT 2) .................... 3
`
`a.
`
`b.
`
`c.
`
`Independent Claims 1, 10, and 16 ................................................................. 3
`
`Dependent Claim 7 ......................................................................................... 7
`
`Dependent Claim 11 ..................................................................................... 11
`
`V. FUJII IN COMBINATION WITH LAM RENDERS OBVIOUS
`CLAIMS 1, 5, 7-11, AND 16 (COUNT 3) ............................................................ 13
`
`a.
`
`b.
`
`c.
`
`Claims 1, 7, 10, 11, and 16 ............................................................................ 13
`
`Claims 5 and 9 ................................................................................................ 16
`
`Claim 8 ............................................................................................................ 17
`
`VI. FUJII IN COMBINATION WITH CLOUTIER OR WITH LAM
`AND CLOUTIER RENDERS OBVIOUS CLAIMS 7-9
`(COUNTS 5 AND 6) ............................................................................................... 22
`
`a.
`
`b.
`
`c.
`
`Claim 7 ............................................................................................................ 23
`
`Claim 8 ............................................................................................................ 24
`
`Claim 9 ............................................................................................................ 25
`
`VII. A POSITA WOULD BE MOTIVATED TO COMBINE FUJII
`AND LAM, FUJII AND CLOUTIER, AND FUJII, LAM, AND
`CLOUTIER ............................................................................................................... 25
`
`VIII. CONCLUSION .......................................................................................................... 26
`
`
`
`
`
`i
`
`

`

`
`
`
`CASES
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co.,
`464 F.3d 1356 (Fed. Cir. 2006) .......................................................................... 26
`
`KSR Int’l v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 25, 26
`
`In re Larson,
`340 F.2d 965 (CCPA 1965) ...................................................................... 2, 17, 18
`
`Ex Parte Seong-Sik Choi, et al.,
`App. 11/190,460, 2012 WL 4955428, at *2 (BPAI Oct. 12, 2012) ..................... 2
`
`
`
`
`
`ii
`
`

`

`
`
`LIST OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`U.S. Patent No. 5,870,087 (“the 087 patent”)
`
`Prosecution History of U.S. Patent No. 5,870,087
`
`Declaration of Richard Kramer (“Kramer Decl.”)
`
`U.S. Patent No. 5,960,464 (“Lam”)
`
`U.S. Patent No. 5,898,695 (“Fujii”)
`
`U.S. Patent No. 5,847,771 (“Cloutier”)
`
`ITU-T Recommendation H.222.0, approved July 10, 1995,
`
`available at http://www.itu.int/rec/T-REC-H.222.0-199507-S/en
`
`(“07/95 H.222.0”)
`
`1008
`
`Excerpts from Academic Press Dictionary of Science and
`
`Technology (Academic Press, Inc., 1992)
`
`1009
`
`Excerpts from Jack, Keith, Video Demystified, Second Edition,
`
`1996
`
`1010
`
`VESA Unified Memory Architecture (VUMA) Standard Hardware
`
`Specification, Version 1.0, March 8, 1996
`
`Datasheet for Samsung KM416S1120AT
`
`Excerpts from August 12, 2015 Joint Claim Construction
`
`1011
`
`1012
`
`iii
`
`

`

`
`
`Statement, Avago Technologies General IP (Singapore) PTE Ltd.
`
`v. ASUSTeK Computer, Inc. et al., Case No. 2:15-cv-00239, Dkt.
`
`46 (E.D. Tex., prior to transfer to N.D. Cal.)
`
`1013
`
`Excerpts from February 5, 2016 Joint Claim Construction and
`
`Prehearing Statement, Avago Technologies General IP
`
`(Singapore) PTE Ltd. v. ASUSTeK Computer, Inc. et al., Case No.
`
`3:15-cv-04525, Dkt. 170 (N.D. Cal., transferred from E.D. Tex.)
`
`1014
`
`Declaration of Michael J. Newton in Support of Motion for
`
`Admission Pro Hac Vice
`
`1015
`
`Deposition Transcript of Scott Acton dated January 30, 2017
`
`
`
`iv
`
`

`

`
`
`I.
`
`STATEMENT OF RELIEF REQUESTED
`
`Petitioners ASUSTeK Computer, Inc. and ASUS Computer International
`
`(collectively “Petitioners”) request cancellation of claims 1, 5, 7-11, and 16 in U.S.
`
`Patent No. 5,870,087 (“the 087 patent,” Ex. 1001), which are the subject of Counts
`
`2, 3, 5, and 6 of their Petition (Paper 3), for the reasons set forth in their Petition
`
`and below.
`
`II.
`
`INTRODUCTION
`
`The 087 patent describes and claims an MPEG decoder made up of
`
`conventional components that uses one memory rather than two. See, e.g., Ex.
`
`1001 at 4:14-28 (disclosing in the “MPEG BACKGROUND” section a “typical
`
`MPEG decoder” and prior art MPEG decoder systems that “typically include[]
`
`transport logic” and “generally include[] a system controller”); id. at 5:7-8 (“The
`
`present invention thus requires only a single memory.”). None of the challenged
`
`claims recite novel memory structures or memory management techniques, but
`
`rather rely on the simple concept of a single memory as their point of novelty.
`
`Similarly, certain dependent claims recite portions or buffers in the single memory,
`
`but Patent Owner’s expert acknowledges that these memory buffers were
`
`conventional and well known. See, e.g., Ex. 1015 at 99:11-14, 100:11-15, 104:3-5,
`
`106:6-20, 110:6-12. Patent Owner relies on the same abstract notion of combining
`
`these buffers into one location—the single memory—as the point of novelty. Paper
`
`- 1 -
`
`

`

`
`
`16 (Resp.) at 38. However, “the use of a one piece construction instead of a
`
`structure disclosed in [the prior art] would be merely a matter of obvious
`
`engineering choice.” In re Larson, 340 F.2d 965, 968 (CCPA 1965); see also Ex
`
`Parte Seong-Sik Choi, et al., App. 11/190,460, 2012 WL 4955428, at *2 (BPAI
`
`Oct. 12, 2012) (affirming rejection where “making separately attached parts
`
`integral was known, involves no more than a predictable variation, and creates
`
`securely attached parts while promoting efficiency”).
`
`Faced with the task of defending the use of one memory instead of two as a
`
`patentable distinction over the prior art, Patent Owner argues primarily that the
`
`various prior art references relied on in the Petition do not satisfy the limitations in
`
`the 087 patent relating to the use of memory during demultiplexing. As described
`
`in the Petition and below, however, these limitations are disclosed not only in Fujii
`
`alone, but also in the combinations of Fujii with Lam, Fujii with Cloutier, and Fujii
`
`with Lam and Cloutier. Patent Owner’s remaining arguments1 do not change this
`
`conclusion, and the challenged claims of the 087 patent are unpatentable as
`
`described in the Petition and herein.
`
`III. CLAIM CONSTRUCTION
`
`Patent Owner contends that the claim terms identified by Petitioners do not
`
`need to be construed. In the event the Board elects to construe the “memory”
`
`1 All other issues are deemed waived. See, e.g., Scheduling Order, Paper 12 at 3.
`
`- 2 -
`
`

`

`
`
`terms, the construction proposed by Patent Owner (“memory functioning as unit”)
`
`is based primarily on Patent Owner’s flawed understanding of the figures of the
`
`087 patent. The specification, however, provides ample support for the requirement
`
`of a single memory. See, e.g., Ex. 1001 at 5:7-10 (“The present invention thus
`
`requires only a single memory, and thus has reduced memory requirements
`
`compared to prior art designs”). Moreover, Patent Owner’s proposed construction
`
`creates more confusion than clarity, as demonstrated by Patent Owner’s expert Dr.
`
`Acton further construing the construction during deposition, and even then being
`
`unable to articulate a meaningful way to apply the construction to the 087 patent or
`
`the prior art. Ex. 1015 at 36:5-37:15 (requiring the “addressing mechanism” to
`
`determine if “functioning as a unit”); id. at 84:16-88:6. Therefore, the Board
`
`should adopt Petitioners’ proposed construction.
`
`IV. FUJII ANTICIPATES CLAIMS 1, 7, 10, 11, AND 16 (COUNT 2)
`
`a. Independent Claims 1, 10, and 16
`
`Patent Owner argues that Fujii is missing a single limitation in the
`
`independent claims, in particular that Fujii purportedly “fails to disclose that the
`
`transport logic retrieves data from a unified memory during demultiplexing
`
`operations.” Paper 16 (Resp.) at 17. In support of this contention, Patent Owner
`
`argues that (1) the transport logic retrieves PID data from the microprocessor
`
`rather than memory, (2) PID data is retrieved before, rather than during,
`
`- 3 -
`
`

`

`
`
`demultiplexing, and (3) PID data is “not the type of data” required by the claims.
`
`Id. at 18, 24. Patent Owner is incorrect on all counts.
`
`First, with respect to the transport logic retrieving data from the memory,
`
`Figure 14 of Fujii (second embodiment) discloses PID Filter 152 (in the transport
`
`logic) retrieving PID data from the RAM via a register in the microprocessor:
`
`
`The presence of a register to temporarily store the PID data retrieved from the
`
`Ex. 1005, Fig. 14.
`
`
`
`RAM on its way to the transport logic does not change the fact that the PID data
`
`- 4 -
`
`

`

`
`
`was retrieved from the RAM by the transport logic. As the Board correctly found,
`
`“the claim language does not require that the transport logic directly access the
`
`memory.” Paper 11 at 19 (emphasis in original). Nor does Patent Owner point to a
`
`disclosure in the 087 patent claims or specification that would require a direct
`
`connection. But even if a direct connection were required, the 087 patent discloses
`
`that “PID data may be supplied via the data bus.” Ex. 1005 at 10:5-6. As shown in
`
`Figure 14, the data bus connects the RAM to the transport logic. While Patent
`
`Owner argues that this phrase merely refers to the configuration depicted in Figure
`
`14, one of ordinary skill in the art would understand this language to disclose that a
`
`direct connection using the bus “may” be used in the alternative to the connection
`
`via the register. See, e.g., Ex. 2004 at 81:9-85:7; see also Ex. 1005 at Figs. 17-18
`
`(depicting bus for retrieval of PID data by the PID Data Interface 219 in Channel
`
`Demultiplexer 202 in the fourth embodiment).
`
`Second, with respect to when the PID data is retrieved, Patent Owner’s
`
`arguments that the PID data is retrieved by the transport logic before
`
`demultiplexing is incorrect. In an effort to create a temporal distinction, Patent
`
`Owner arbitrarily defines when the demultiplexing process begins. As Patent
`
`Owner’s expert Dr. Acton concedes, the PID data is used during demultiplexing of
`
`the streams. Ex. 1015 at 69:20-70:6, 72:1-18, 83:20-23. Indeed, the transport logic
`
`retrieves this data from the RAM for this very reason. Because demultiplexing in
`
`- 5 -
`
`

`

`
`
`Fujii requires the PID data, the PID data retrieval process is properly considered to
`
`occur during demultiplexing. This is further confirmed by Figure 7 of Fujii, which
`
`depicts “the algorithm of a packet demultiplexing process.” Ex. 1005 at 5:24-25;
`
`see also id. at Fig. 15.
`
`Ex. 1005, Fig. 7.
`
`
`
`
`
`As shown in Figure 7, this “demultiplexing process” includes both the
`
`retrieval of the PID from memory (S1) as well as separating into video and audio
`
`(S6 and S7). And as Dr. Acton concedes, the retrieved PID is used throughout the
`
`- 6 -
`
`

`

`
`
`demultiplexing process shown in Figure 7. Ex. 1015 at 69:20-70:6, 72:1-18.
`
`Third, with respect to whether PID data is “data,” Patent Owner is
`
`apparently making a claim construction argument despite not identifying any claim
`
`terms necessary for construction. See Paper 16 (Resp.) at 8-12. In essence, Patent
`
`Owner argues that “data” (when used in the context of the transport logic) does
`
`actually not mean “data,” but rather means “the data to be demultiplexed.” Paper
`
`16 (Resp.) at 24. The 087 patent does not support this overly narrow interpretation.
`
`For example, the independent claims require only that the “transport logic is
`
`operable to access the memory to store and retrieve data” (claim 1) and
`
`“demultiplexing … operates using a first unified memory” (claim 10). Nothing in
`
`the claims requires the “data” to take any particular form, only that it can be stored,
`
`retrieved, and used. PID data satisfies these requirements. Indeed, under Patent
`
`Owner’s proposal, the word “data” would have different meanings within the same
`
`claim, as claim 1 also requires the system controller to be “operable to access the
`
`memory to retrieve code and data during system control functions.” Therefore,
`
`Fujii anticipates independent claims 1, 10, and 11.
`
`b. Dependent Claim 7
`
`As described above and in the Petition, Fujii discloses all of the limitations
`
`of claim 1 from which claim 7 depends. Patent Owner further argues that claim 7 is
`
`not anticipated because Fujii purportedly does not disclose the RAM containing (1)
`
`- 7 -
`
`

`

`
`
`a “video frame portion for storing video frames” or (2) a “transport buffer portion
`
`for storing data used by the transport logic.” Paper 16 (Resp.) at 25. Fujii, however,
`
`discloses both of these elements.
`
`First, with respect to the video frame portion of memory, and contrary to
`
`Patent Owner’s assertions, Fujii does not teach away from including a video frame
`
`portion in the RAM. Although Figure 11 depicts video decode buffer 9 and RAM 7
`
`in separate boxes, the Figure 17 embodiment does not depict a video decode buffer
`
`separate from RAM 203:
`
`Ex. 1005, Fig. 17.
`
`
`
`And as Patent Owner’s expert Dr. Acton admits, one of skill in the art would
`
`understand that the MPEG decoder system depicted in Fujii Figure 17 would
`
`require storage of video frames, such as a video decode buffer:
`
`Q. I'm asking in the Figure 17 embodiment, is it your opinion that this
`
`embodiment would not have a video decode buffer?
`
`A. I don't think that's my opinion. If you read Paragraph 62, I'm
`
`- 8 -
`
`

`

`
`
`saying that it's not disclosed.
`
`Q. So you would expect this embodiment to have a video decode
`
`buffer somewhere. Correct?
`
`[Objection to form.]
`
`A: Incorrect. I would expect this embodiment to require the -- to
`
`have the need to utilize a video decode buffer. Yes.
`
`Ex. 1015 at 94:3-14 (emphasis added).
`
`One of skill in the art would therefore understand that the embodiment in
`
`Figure 17 contains a video frame portion in memory, and that the video frame
`
`portion of memory is located in the RAM. Ex. 1003 at ¶ 102. In addition, inclusion
`
`of a video frame portion in the RAM in Figure 17 is consistent with the other
`
`disclosure in Fujii. For example, the audio decode buffers and packet landing
`
`buffers depicted separately from the RAM in Figure 2 are depicted within the
`
`RAM in Figure 11. As the goal of Fujii is to consolidate the memory to “reduce the
`
`number of components and lower the cost of components,” Ex. 1005 at 3:63-64,
`
`and because the video frame portion is a required component of the system, Ex.
`
`1015 at 94:3-25, one of skill in the art would understand that the RAM in Figure 17
`
`contains a video frame portion for storing video frames, rather than deleting this
`
`necessary element entirely. Ex. 1003 at ¶ 102.
`
`Second, with respect to the transport buffer portion, Patent Owner argues
`
`- 9 -
`
`

`

`
`
`that the packet landing buffers in Fujii are not used by the transport logic because
`
`they store data output by the transport logic. As an initial matter, PID data satisfies
`
`the plain and ordinary meaning of “data,” and as described above and in the
`
`Petition, PID data is stored in the RAM and used by the transport logic. Thus,
`
`Fujii’s disclosure of PID data in the RAM constitutes a “transport buffer portion
`
`for storing data used by the transport logic.”
`
`In addition, Fujii’s packet landing buffer in the RAM also discloses a
`
`transport buffer portion. As with Patent Owner’s argument that PID data is not
`
`retrieved during demultiplexing, Patent Owner again attempts to create an arbitrary
`
`temporal distinction not reflected in the 087 patent claim language or specification.
`
`As explained in the Petition, Fujii discloses that the packet landing buffer in the
`
`RAM stores data used by the transport logic, namely the “PSI packet and TS
`
`packets relevant to the program #k.” Ex. 1005 at 9:23-25; Ex. 1003 at ¶ 93. To
`
`perform demultiplexing, the transport logic must use this data: “The program
`
`packet filter 15 derives from transmitted TS packets a PSI packet and a TS packet
`
`containing an element of the user selected program (program number #k), and
`
`supplies the filtered packets to the interface unit 14.” Ex. 1005 at 9:16-19
`
`(emphasis added). The transport logic sending the data to the buffer in the RAM
`
`further illustrates the use of the data and the buffer by the transport logic.
`
`That the data is used by the transport logic is further apparent in light of the
`
`- 10 -
`
`

`

`
`
`conventional apparatus in Fujii Figure 2, where “[i]t is … necessary to insert
`
`packet transport buffers 5 and 6 between the demultiplexer and decoders to convert
`
`the bit rates in accordance with the capacities of the decoder buffers, and thereafter
`
`to supply element data to the video decoder 8 and audio decoder 10.” Ex. 1005 at
`
`2:53-57. Fujii goes on to note that “the packet transport buffers [may be]
`
`implemented in the demultiplexer” in a conventional configuration, id. at 2:65-66,
`
`further demonstrating that the packet landing (or transport) buffer is used by the
`
`transport logic to store data as part of the demultiplexing process. Therefore, the
`
`packet landing buffer 71 in Figure 11 or the RAM in Figure 17 stores data used by
`
`the transport logic and constitutes a “transport buffer portion.”
`
`c. Dependent Claim 11
`
`Patent Owner makes the same arguments with respect to claim 11 that it
`
`made with respect to the independent claims, with the additional argument that PID
`
`data is not “multimedia data stream data.”
`
`As with the term “data” (when used by the transport logic), Patent Owner
`
`appears to be making a claim construction argument despite not providing a
`
`proposed construction in the “Claim Construction” section. Nevertheless, Patent
`
`Owner’s apparent construction of this term is inconsistent with the patent
`
`specification and the plain meaning of this phrase. For example, Patent Owner
`
`alleges that PID data cannot be “multimedia data stream data” because it “is not
`
`- 11 -
`
`

`

`
`
`‘multimedia’ nor is it a ‘stream.’” Paper 16 (Resp.) at 28. The claim term at issue,
`
`however, is “multimedia data stream data,” not “multimedia data stream.” Patent
`
`Owner’s argument attempts to improperly delete the final “data” from this phrase.
`
`Indeed, the claims themselves demonstrate that Patent Owner knew how to claim
`
`multimedia data streams, as the entire claim limitation refers to both “multimedia
`
`data streams” as well as “multimedia data stream data”: “wherein said
`
`demultiplexing one or more multimedia data streams from the encoded stream
`
`includes accessing multimedia data stream data from said first unified memory.”
`
`Ex. 1001 at 18:36-39 (emphasis added). Using a proper interpretation of this term,
`
`Fujii discloses “multimedia data stream data.” Fujii Figure 3A, for example,
`
`discloses PID data in a multimedia data stream:
`
`Ex. 1005, Fig. 3A.
`
`
`
`
`
`Alternatively, the packets in the packet landing buffer in RAM are
`
`- 12 -
`
`

`

`
`
`“multimedia data stream data” accessed during demultiplexing. See, e.g. Ex. 1005
`
`at 10:7-11 (“[A]s illustrated in FIG. 15, the algorithm of the data filtering from
`
`RAM 7 to the decoders includes only a filtering process for the elements of the
`
`program and PSI packet.”). In either case, Fujii anticipates claim 11.
`
`V.
`
`FUJII IN COMBINATION WITH LAM RENDERS OBVIOUS
`CLAIMS 1, 5, 7-11, AND 16 (COUNT 3)
`
`a. Claims 1, 7, 10, 11, and 16
`
`As discussed above, claims 1, 7, 10, 11, and 16 are anticipated by Fujii
`
`alone. Therefore, obviousness of these claims is presented in the alternative to the
`
`anticipation arguments based on Fujii alone.
`
`First, with respect to independent claims 1, 10, and 16, Patent Owner argues
`
`that Fujii and Lam both “fail[] to disclose that the transport logic retrieves data
`
`from a unified memory during demultiplexing operations, as required by each of
`
`the challenged claims.” Paper 16 (Resp.) at 32. As shown above, however, Fujii
`
`discloses these limitations. Patent Owner further argues that Lam in combination
`
`with Fujii does not render these limitations obvious because “[w]ithout any
`
`specific disclosure in Lam, one of skill in the art would not infer that Lam teaches
`
`or suggests the use of main memory 106 for this functionality.” Paper 16 (Resp.) at
`
`36. Patent Owner is incorrect. As an initial matter, Lam is clear that the goal of the
`
`invention is to reduce memory requirements by utilizing the main memory as part
`
`of the MPEG decoder system:
`
`- 13 -
`
`

`

`
`
`
`
`“The DVD driver 156, in turn, transfers the requested data from the
`
`DVD CD-ROM disk 113 to a known location in the main memory
`
`106, as described below.” Ex. 1004 at 5:41-44.
`
`
`
`“While prior MPEG 2 decoding circuits employed dedicated memory,
`
`the present invention shares the main memory 108 with the computer
`
`102.” Id. at 6:59-62.
`
`
`
`“The present invention avoids the need for additional memory to be
`
`used with the MPEG 2 decoder 114, but instead shares the main
`
`memory 106 with the computer system 100.” Id. at 9:3-5.
`
`In addition, despite Patent Owner’s attempts to infer additional undisclosed
`
`memories into Lam’s disclosure (i.e., a “dedicated buffer in hardware”), Paper 16
`
`(Resp.) at 36, Lam Figure 1 (“a block diagram of a computer system having an
`
`MPEG 2 decoder under the present invention”) and Figure 2 (“a block diagram of
`
`the MPEG 2 decoder of FIG. 1”) disclose only a single non-optional memory—
`
`main memory 106:
`
`- 14 -
`
`

`

`
`
`Ex. 1004, Fig. 1.
`
`
`
`Ex. 1004, Fig. 2.
`
`
`
`Given the disclosure in Fujii regarding the use of RAM for demultiplexing
`
`operations, it would have been obvious to modify Lam to incorporate the teachings
`
`of Fujii and use the main memory of Lam as a single memory which the transport
`
`logic is operable to access to store and retrieve data during demultiplexing
`
`operations. Ex. 1003 at ¶ 114.
`
`Second, with respect to dependent claim 7, Patent Owner’s arguments are
`
`- 15 -
`
`

`

`
`
`limited to those arguments relating to Fujii alone and the argument above that Lam
`
`does not “disclose any memory access by
`
`the
`
`transport
`
`logic during
`
`demultiplexing.” Paper 16 (Resp.) at 37-38. As discussed above, it would have
`
`been obvious to modify Lam to incorporate the teachings of Fujii with respect to
`
`the use of memory during demultiplexing, and therefore claim 7 is obvious in view
`
`of Fujii and Lam. See also Ex. 1003 at ¶ 118.
`
`Third, with respect to dependent claim 11, Patent Owner’s arguments are
`
`limited to those arguments relating to Fujii alone and the argument above that Lam
`
`does not “disclose[] the accessing or retrieval of any data from the unified memory
`
`during demultiplexing.” Paper 16 (Resp.) at 41-42. As discussed above, it would
`
`have been obvious to modify Lam to incorporate the teachings of Fujii with respect
`
`to the use of memory during demultiplexing, and therefore claim 11 is obvious in
`
`view of Fujii and Lam. See also Ex. 1003 at ¶ 114.
`
`b. Claims 5 and 9
`
`Other than arguments relating to motivation to combine and the claims from
`
`which these claims depend, Patent Owner makes no additional arguments that
`
`claims 5 and 9 are not obvious in view of the combination of Fujii and Lam. Patent
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`Owner’s arguments fail. As discussed in Section VII below, a person of ordinary
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`skill in the art would have been motivated to combine Fujii and Lam. Further, the
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`claims from which claims 5 and 9 depend are anticipated by Fujii alone (claims 1
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`and 7) or rendered obvious by Fujii and Lam (claims 1, 7, and 8).
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`c. Claim 8
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`Claim 8 depends from claim 7, which is anticipated by Fujii, or, in the
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`alternative, rendered obvious based on the combination of Fujii and Lam, both of
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`which are discussed above. Patent Owner argues that including the buffers recited
`
`in claim 8 in the single memory of Fujii or Lam would not be obvious.
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`As an initial matter, Patent Owner agrees with Petitioners’ expert Mr.
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`Kramer that “memory buffers were known in the art at the time.” Paper 16 (Resp.)
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`at 38. Patent Owner’s expert Dr. Acton likewise agrees. Ex. 1015 at See, e.g., Ex.
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`1015 at 99:11-14, 100:11-15, 104:3-5, 106:6-20, 110:6-12. Dr. Acton further
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`concedes that he is “uncomfortable saying … that there’s one definition that
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`corresponding with every [buffer] term throughout the art. Sometimes as engineers
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`we aren’t that consistent.” Id. at 108:25-109:7. Yet, despite the parties’ agreement
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`that buffers—including
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`the particular buffers recited
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`in claim 8—were
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`conventional structures common to prior art MPEG decoder systems, Patent Owner
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`nevertheless argues that claim 8 is distinguishable from the prior art because “one
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`of the novel aspects of the ’087 Patent, and claim 8 in particular, is the inclusion of
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`such buffers within a single unified memory.” Paper 16 (Resp.) at 38 (emphasis
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`added). The use of a single memory with these conventional buffers instead of
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`separate buffers, however, “would be merely a matter of obvious engineering
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`choice,” Larson, 340 F.2d at 968, and therefore claim 8 is obvious in view of Fujii
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`alone, Lam alone, or Fujii in combination with Lam.
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`To the extent including the conventional buffers of claim 8 within a single
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`memory is not obvious on the face of Fujii or Lam alone, the combination of Fujii
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`and Lam renders these buffers obvious. With respect to Lam, Patent Owner argues
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`that “there may be other dedicated memory buffers that are separate from main
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`memory 106.” Paper 16 (Resp.) at 39 (emphasis added). Patent Owner thus ignores
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`the only disclosure of video decoding memory in Lam—the main memory—and
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`asks the Board to infer that the phrases “conventional construction” and
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`“application-specific integrated circuit (ASIC)” require the use of “a video decode
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`buffer on-chip.” Id. at 39. Lam, however, teaches away from dedicated memory:
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`“While prior MPEG 2 decoding circuits employed dedicated memory, the present
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`invention shares the main memory 108 with the computer 102.” Ex. 1004 at 6:59-
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`62 (emphasis added).
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`But even if on-chip memory were present in Lam, it would not diminish the
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`obviousness of combining other known memory buffers into a single memory. For
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`example, Figure 4 of the 087 patent “illustrat[es] the MPEG decoder logic in the
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`system of FIG. 3,” which “illustrat[es] an MPEG decoder system … according to
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`the present invention.” Ex. 1001 at 5:55-61. According to Fujii, “the operation of
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`MPEG decoders is well known in the art,” id. at 11:45-48, and the “motion
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`compensation block 310 includes a local memory or on-chip memory 116 [sic]
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`which stores the retrieved reference block.” Id. at 12:52-54 (emphasis added).
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`Ex. 1001, Fig. 4.
`
`
`
`If Figure 4 truly reflects the “present invention” of the 087 patent, the use of
`
`a separate on-chip memory has no effect on the presence of multiple buffers in the
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`single memory, much less the specific buffers recited in claim 8. Indeed, according
`
`to Patent Owner’s expert Dr. Acton, the on-chip memory in the motion
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`compensation block of the 087 patent has a similar objective to the on-chip
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`memory in the prior art Lin paper (Ex. 2005), which Dr. Acton relies on in support
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`of his opinion. Paper 16 (Resp.) at 39-40; Ex. 1015 at 120:3-121:4. Thus, even if
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`the use of on-chip memory could be inferred from Lam’s passing reference to
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`“conventional configuration” and “ASIC”—despite Lam’s repeated emphasis on
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`the use of the main memory for video decoding (see, e.g., Ex. 1004 at 9:3-5)—the
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`Lin paper demonstrates that on-chip memory, even if it were present in Lam, does
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`not counteract the obviousness of including other conventional buffers in a single
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`memory.
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`In addition, despite Patent Owner’s expert Dr. Acton acknowledging that the
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`purported novelty is “not the innovation of the buffer,” Ex. 1015 at 110:11, Patent
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`Owner’s Response is replete with arguments that the prior art does not invalidate
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`claim 8 because it purportedly does not disclose conventional and well known
`
`buffers. Even if this were true, Patent Owner cannot acknowledge that buffers were
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`well known in the art while at the same time argue that those conventional buffers
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`distinguish the prior art. Nevertheless, the combination of Fujii and Lam renders
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`these buffers obvious as described in the Petition.
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`For example, with respect to the “video decode buffer portion,” as discussed
`
`with respect to claim 7 of Fujii above, Fujii Figure 17 discloses a single memory
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`that would be understood to include a video decode buffer portion for storing
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`decoded video data: the RAM. Lam, moreover, discloses the use of main memory
`
`for video decoding. Thus, the “video decode buffer portion for storing decoded
`
`video data” is further obvious in light of the combination of Fujii and Lam. Ex.
`
`1003 at ¶ 120.
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`Patent Owner also argues that the “audio sync buffer” in Fujii does not
`
`render obvious the “video display sync buffer” in claim 8. Paper 16 (Resp.) at 40.
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`The buffers, however, perform the same function. According to Fujii, “a delay
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`buffer … is provided in RAM 7 to realize synchronized outputs” due to the total
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`delay time between video and audio. Ex. 1005 at 8:9-16. While the 087 patent
`
`provides no further description of the “video display sync buffer” than its name in
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`a list (see, e.g., Ex. 1001 at 15:38), Dr. Acton admits that video display sync
`
`buffers and audio display sync buffers basically serve the same purpose, with the
`
`difference being whether the audio decoder is faster than the video decoder. Ex.
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`1015 at 99:15-100:15 (“So in the case of a video sync buffer, we’re holding frames
`
`that are produced before the audio is ready.”). This distinction is trivial,
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`particularly in view of Dr. Acton’s admission that “engineers … aren’t that
`
`consistent” and that there may not be “one definition that’s corresponding to every
`
`term throughout the art.” Id. at 108:25-109:7. The combination of Fujii and Lam
`
`therefore renders this buffer obvious. Ex. 1003 at ¶ 121.
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`Finally, Patent Owner argues that the “on-screen display buffer” is not
`
`obvious. Paper 16 (Resp.) at 40. Once again, Dr. Acton acknowledges that this
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`buffer was not invented by the 087 patent and is not described in the specification.
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`Ex. 1015 at 102:4-22, 104:3-5. An on-screen display processor, moreover, is
`
`expressly identified in Fujii Figure 17. The inclusion of this conventional buffer in
`
`the single memory is therefore obvious in view of Fujii and Lam. Ex. 1003 at
`
`¶ 122.
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`VI. FUJII IN COMBINATION WITH CLOUTIER OR WITH LAM
`AND CLOUTIER RENDERS OBVIOUS CLAIMS 7-9 (COUNTS 5
`AND 6)
`
`Claims 7, 8, and 9 relate to the use of specific memory portions or buffers in
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`the single memory of the 087 patent. As Patent Owner’s expert Dr. Acton
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`acknowledges, any purported novelty of the 087 patent is “not the innovation of
`
`the buffer.” Ex. 1015 at 110:10-11. Indeed, if buffers such as these were not known
`
`in the art, one reading the 087 patent would have no understanding of these buffers
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`at all, as the entire disclosure relating to the buffers in the claims is simply a list of
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`names without any accompanying detail or description:
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`FIG. 9 illustrate