UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`ASUSTEK COMPUTER, INC. and ASUS COMPUTER INTERNATIONAL,
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`Petitioners
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`v.
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`AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.,
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`Patent Owner
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`____________
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`
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`Case: IPR2016-00646
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`U.S. Patent No. 5,870,087
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`____________
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`PETITIONER’S EXHIBIT NO. 1003
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`DECLARATION OF RICHARD KRAMER UNDER 37 C.F.R. § 1.68
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`ASUS Exhibit 1003 - Page 1
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`Table of Contents
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`I. Qualifications and Professional Experience ........................................................ 5
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`II. Relevant Legal Standards ..................................................................................11
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`III. Background of the 087 Patent ...........................................................................13
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`i. The MPEG Standard and MPEG Transport, Decode and System
`Controller Functions Were Well Known to Those of Skill in the Art ........ 18
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`ii. The MPEG Standard and MPEG Transport, Decode and System
`Controller Functions Are Admitted Prior Art ............................................. 21
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`IV. Claim Construction ............................................................................................24
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`i. “memory” / “first unified memory” ...................................................... 25
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`ii. “demultiplexing one or more multimedia data streams” /
`“demultiplexes one or more multimedia data streams” .............................. 28
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`V. The Prior Art ......................................................................................................29
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`i. Lam ........................................................................................................ 29
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`ii. Fujii ........................................................................................................ 30
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`iii. Cloutier .................................................................................................. 31
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`VI. The Challenged Claims......................................................................................32
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`VII. Anticipation Analysis ..................................................................................37
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`i. Count 1: Lam Anticipates Claims 1, 5, 10, 11, and 16 ........................ 37
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`ii. Count 2: Fujii Anticipates Claims 1, 7, 10, 11, and 16 ........................ 52
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`VIII. Obviousness Analysis ..................................................................................69
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`i. Motivation to Combine ......................................................................... 69
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`ii. Count 3: Fujii in View of Lam Renders Obvious Claims 1, 5,
`7-11, and 16 ................................................................................................. 70
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`ASUS Exhibit 1003 - Page 2
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`iii. Count 4: Lam in View of Cloutier Renders Obvious Claims 7,
`8, and 980
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`iv. Count 5: Fujii in View of Cloutier Renders Obvious Claims 7,
`8, and 988
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`v. Count 6: Fujii in View of Lam in Further View of Cloutier
`Renders Obvious Claims 7, 8, and 9 ........................................................... 93
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`IX. Summary Chart ..................................................................................................98
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`X. Conclusion .......................................................................................................105
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`ASUS Exhibit 1003 - Page 3
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`I, Richard Kramer, declare:
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`1.
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`I am making this declaration at the request of ASUSTeK Computer,
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`Inc. and ASUS Computer International in the matter of the Inter Partes Review of
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`U.S. Patent No. 5,870,087 (“the 087 Patent”) to Chau.
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`2.
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`I am being compensated for my work in this matter. My compensation
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`in no way depends upon the outcome of this proceeding.
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`3.
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`In the preparation of this declaration, I have studied:
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`a.
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`The 087 Patent, Ex. 1001;
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`b.
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`The prosecution history of the 087 Patent, Ex. 1002;
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`c.
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`U.S. Patent No. 5,960,474 (“Lam”), Ex. 1004
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`d.
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`U.S. Patent No. 5,898,695 (“Fujii”), Ex. 1005
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`e.
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`U.S. Patent No. 5,847,771 (“Cloutier”), Ex. 1006
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`4.
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`In forming the opinions expressed below, I have considered:
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`a.
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`The documents listed above,
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`b.
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`The relevant legal standards, including the standard for
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`obviousness provided in KSR International Co. v. Teleflex, Inc., 550 U.S.
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`398 (2007),
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`c.
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`The relevant state of the art at the time of the invention,
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`including Exhibits 1007-1011, and
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`d. My knowledge and experience based upon my work in this
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`ASUS Exhibit 1003 - Page 4
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`area, as described below.
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`I.
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`Qualifications and Professional Experience
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`5. My qualifications are set forth in my curriculum vitae, a copy of
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`which is attached as Exhibit A to this declaration. As set forth in my curriculum
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`vitae:
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`6.
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`I received a Bachelor’s of Science degree in Electrical Engineering
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`from the University of Toledo in 1984. I have over 30 years of experience
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`successfully developing and launching commercially-implemented software and
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`hardware products and systems, including 19 years in the video industry
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`developing commercially successful products related to subscriber television
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`systems, IP networking, cable and satellite TV systems and equipment, cable TV
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`set-top boxes, remote controls, video networking, software, and other technologies
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`relevant to the subject matter of the 087 Patent. The cable TV video, video
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`surveillance and IP network video products and systems that I have developed
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`have been successfully launched under respected brands such as General Electric
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`and Scientific-Atlanta (now Cisco). My experience also included the development
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`of new technologies within pioneering high-tech start-up companies like Ivex
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`Corporation (acquired in 2001 by Axcess, Inc.), where we developed one of the
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`first IP network Video Streaming Appliances (called the “VSA”) for the video
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`surveillance industry. I hold two patents.
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`ASUS Exhibit 1003 - Page 5
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`7.
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`In 1987 I joined Schlumberger Industries, Electricity Management
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`North America.
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`8.
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`From 1987 until 1989, I was an Electronic Design Engineer at
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`Schlumberger. As an Electronic Design Engineer, I designed circuitry for a
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`product called the Quantum™, including an application specific integrated circuit
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`(“ASIC”) for the Quantum™ for memory management of the device. I also
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`designed the main processor and the memory circuits. The ASIC that I designed
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`allowed the memory to be partitioned for various functions within the operating
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`system and data storage system, and the memory was battery backed RAM
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`(Random Access Memory). To the processor, via the ASIC, the memory appeared
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`as a contiguous block of memory. The Quantum™ is a solid state electronic
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`electric meter with a dial-up modem that was primarily used in substation metering
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`and industrial applications. I also developed firmware for the Quantum™.
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`Additionally, I designed electronics for the Schlumberger Fulcrum™, a solid state
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`multifunction electronic electric meter including the main processor and memory
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`circuits. I worked on all aspects of the Schlumberger Fulcrum™, from core
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`metering to AMR (Automatic Meter Reading) electronics.
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`9.
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`In 1989, I was promoted to Senior Electronic Design Engineer at
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`Schlumberger. My duties as a Senior Electronic Design Engineer were similar to
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`those I had when I was an Electronic Design Engineer.
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`ASUS Exhibit 1003 - Page 6
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`10.
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`In 1990,
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`I was promoted again
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`to Hardware Manager at
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`Schlumberger. In that role, I began work in the Recorders and Translation Systems
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`Division. Because our systems were “Recorders” I had to be astute in memory
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`architecture as we designed new products. As Hardware Manager in the Recorders
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`and Translation Systems division, I led the development of data collection/memory
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`circuits and communication interfaces between electricity meters and a utility’s
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`central office, including battery powered handheld readers.
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`11.
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`In 1994, I was promoted to Engineering Manager, Residential and
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`Commercial Metering. As Engineering Manager, Residential and Commercial
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`Metering for Schlumberger, I oversaw product development of residential and
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`commercial solid state electronic electric meters for North America. I was
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`responsible for, among other things, the Schlumberger Vectron™ product, the
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`MT200/MTR200 Electronic Register product, and MACS™, a power line carrier
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`system. In this role, I led development of core metering technology, processor and
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`memory circuits, AMR interfaces, and firmware development.
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`12.
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`In early 1995, I became the engineering/technology leader for cable
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`TV set-top boxes in North America for Scientific-Atlanta, Inc. (prior to being
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`acquired by Cisco Systems, Inc.). I was responsible for all set-top devices for the
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`Advance Video Systems group. My group and the people that reported to me
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`developed and successfully launched Scientific-Atlanta’s first internally designed
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`ASUS Exhibit 1003 - Page 7
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`set-top (also called HCTs which means Home Communication Terminals). The
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`sales volumes of the products we developed exceeded 1 million units per year.
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`The position required me to be astute to each facet of the cable system technology
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`and the overall system. I was later promoted and served as the top technology
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`leader on the Strategic Planning Team for the “Advanced Video Systems”
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`Division. There I worked on the next generation advanced video products. In this
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`role, each of the functional technology areas including firmware, hardware, system
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`software and headend equipment reported to me in a dotted line matrix/cross-
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`functional organizational structure for the development of our next generation of
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`products. Our set-tops employed a wide spectrum of technology including the use
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`of ASICs (Application Specific Integrated Circuits), processors, memory systems,
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`decoders and decryption circuits. Because of our high volume of sales, cost
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`reduction was always a major effort including the elimination and reduction in
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`number of electronic components. As my CV indicates, I successfully led the
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`development team to reduce the cost of one of our main selling set-top boxes by
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`40%. As the top technology leader of the Strategic Planning Team for the
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`“Advanced Video Systems” Division I was immersed the latest system and
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`memory architectures and technologies as we developed our next generation
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`products.
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`13.
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`In 1998, I joined Home Wireless Networks, Inc, where I was
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`ASUS Exhibit 1003 - Page 8
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`promoted to Vice President of Engineering. At Home Wireless Networks, I led all
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`engineering in the development of leading-edge wireless products, including 900
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`MHz radio frequency (“RF”) circuits, antennas, and transceivers. Home Wireless
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`Networks’ products—which included the first integrated voice and low-cost IEEE
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`802.11 WiFi access point—were launched under the British Telecom and Telenor
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`brands in Europe and the BellSouth and MCI brands in the United States.
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`14. Seeing the need and opportunity in the video surveillance industry for
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`IP network video products, myself and a number of former Scientific-Atlanta
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`employees joined Ivex Corporation (“Ivex”), where I served as the Vice President
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`of Engineering starting in 2000 and led all technology development. At Ivex I led
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`the development of a video surveillance product called VSA (Video Streaming
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`Appliance), which allowed retail chains like Ace Hardware, The Finish Line, and
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`Eddie Bauer to remotely view their sites and facilities. I guided the development of
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`both the hardware platform and the required network solution to support the VSA
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`product. We called that software and network solution “ViewOps,” which included
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`both a hosted website over the Internet whereas “event” video and associated event
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`information was captured by a server, converted to a streaming video format, and
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`streamed via the hosted web-site viewing over the Internet. Such developments
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`were the subject of U.S. Patent 6,945,859 (“Simerly et al., filed October 8, 1999),
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`whereas the inventor reported directly to me.
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`ASUS Exhibit 1003 - Page 9
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`15.
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`In 2001, I joined and served as Vice President of Product
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`Development at Miraxis Corporation (a division of EMS Technologies, Inc., now
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`Honeywell, Inc.) developing IP network and digital video solutions in the satellite
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`TV industry. At Miraxis, we were focused on the design of an entirely new
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`DBS/DTH (Direct Broadcast Satellite/Direct to Home) television and multimedia
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`solution. Overall, Miraxis was responsible for the design of the satellite payload,
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`the associated ground based systems, and the CPE (Customer Premise Equipment).
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`As the Vice President of Product Development, I was responsible for all aspects of
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`the system solution; I was immersed in the leading-edge state of the industry. In
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`fact, we were one of only a handful of companies that received a newly allowed
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`Ka-Band satellite license. The new Ka-Band frequency spectrum opened
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`significant new opportunities for providing entertainment content to homes across
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`America.
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`16. From 2003 to 2007, I served as the Vice President-Engineering and
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`General Manager-Technology over the Video Systems Group (“VSG”) at General
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`Electric (“GE”). This role included the direct leadership of the development of
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`DVRs (Digital Video Recorders), advanced video systems, intelligent video
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`software, cameras, and client-server based video management systems.
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`17.
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`In summary, I have a deep familiarity with video decoders and
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`memory systems and the prevailing thoughts at the time of the 087 Patent
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`ASUS Exhibit 1003 - Page 10
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`invention and before.
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`18.
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`I am familiar with the knowledge and capabilities of one of ordinary
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`skill in the software/hardware engineering and, specifically, video and memory
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`system architectures based on: (1) my direct extensive experience in the industry;
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`and (2) my extensive experience with engineers practicing in the industry. In fact,
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`I directly managed and supervised such individuals thus allowing me to fully
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`appreciate the level of skill of individuals and the general state of the art. Unless
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`otherwise stated, my testimony below refers to the knowledge of one of ordinary
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`skill in the industry in November 1996, when the application which became the
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`087 Patent was filed.
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`19.
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`In my opinion, the level of ordinary skill in the art needed to have the
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`capability of understanding the scientific and engineering principles applicable to
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`the 087 Patent is (i) a B.S. degree in Electrical Engineering or equivalent training,
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`and (ii) approximately two to five years of direct experience in developing
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`processor systems involving memory architectures in order to appreciate what was
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`obvious and/or anticipated in the industry and what a person having ordinary skill
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`in the art would have thought at the time. Relevant industry experience could also
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`include experience with video decoders or other systems that shared memory with
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`a common processor.
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`II. Relevant Legal Standards
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`ASUS Exhibit 1003 - Page 11
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`20.
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`I have been asked to provide my opinions regarding whether the
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`claims 1, 5, 7-11, and 16 of the 087 Patent are anticipated or would have been
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`obvious to a person having ordinary skill in the art at the time of the alleged
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`invention, in light of the prior art. It is my understanding that, to anticipate a claim
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`under 35 U.S.C. § 102, a reference must teach every element of the claim. Further,
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`it is my understanding that a claimed invention is unpatentable under 35 U.S.C. §
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`103 if the differences between the invention and the prior art are such that the
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`subject matter as a whole would have been obvious at the time the invention was
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`made to a person having ordinary skill in the art to which the subject matter
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`pertains. I also understand that the obviousness analysis takes into account factual
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`inquiries including the level of ordinary skill in the art, the scope and content of the
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`prior art, and the differences between the prior art and the claimed subject matter.
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`21.
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`It is my understanding that the Supreme Court has recognized several
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`rationales for combining references or modifying a reference to show obviousness
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`of claimed subject matter. Some of these rationales include the following:
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`combining prior art elements according to known methods to yield predictable
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`results; simple substitution of one known element for another to obtain predictable
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`results; use of a known technique to improve a similar device (method, or product)
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`in the same way; applying a known technique to a known device (method, or
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`product) ready for improvement to yield predictable results; choosing from a finite
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`ASUS Exhibit 1003 - Page 12
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`number of identified, predictable solutions, with a reasonable expectation of
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`success; and some teaching, suggestion, or motivation in the prior art that would
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`have led one of ordinary skill to modify the prior art reference or to combine prior
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`art reference teachings to arrive at the claimed invention.
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`22.
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`It is my understanding that some claims can be interpreted as “means
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`plus function” claims under 35 U.S.C. § 112, paragraph 6. I understand that
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`“means plus function” claims require first, defining the particular function of the
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`limitation and second, identifying the corresponding structure for that function in
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`the specification. I also understand that structure disclosed in the specification is
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`corresponding structure only if the specification or prosecution history clearly links
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`or associates that structure to the function recited in the claim.
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`III. Background of the 087 Patent
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`23. The 087 Patent issued on February 9, 1999, from U.S. Patent
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`Application No. 748,269 filed on November 13, 1996, by Kwok Kit Chau.
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`24. The 087 Patent describes the alleged invention as a well-known
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`“computer system which performs video decoding” and includes “a video
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`decoder.” 087 Patent, 5:49-52, 17:2-3, Fig. 1. Video for decoding can be received
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`by the computer system from a broadcast signal or a standard Digital Video Disk
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`(DVD): “The media storage unit 62 preferably . . . includes . . . one or more
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`Digital Video Disk (DVD) storage units, or other media, for storing digital video to
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`ASUS Exhibit 1003 - Page 13
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`be decompressed and/or for storing the resultant decoded video data.” 087 Patent,
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`7:10-24. A block diagram of a computer system that performs MPEG decoding is
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`provided in Figure 2 of the 087 Patent, which shows the interconnection of system
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`components using a well-known “PCI (Peripheral Component Interconnect).” 087
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`Patent, 6:67-7:6, Fig. 2.
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`25. A block diagram illustrating the MPEG decoder system architecture
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`of the 087 Patent and the primary claim elements is provided in Figure 3 of the 087
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`Patent:
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`–14–
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`ASUS Exhibit 1003 - Page 14
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`087 Patent, Fig. 3 (annotated), 7:65-9:20.
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`Channel receiver 202
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`Transport logic 206
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`System controller 208
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`MPEG decoder 224
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`Memory 212
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`26. Claim 1 provides a basic overview of the 087 Patent:
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`1. An MPEG decoder system which includes a single
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`memory for use by transport, decode and system
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`controller functions, comprising:
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`a channel receiver for receiving and MPEG encoded
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`stream;
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`transport logic coupled to the channel receiver which
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`demultiplexes one or more multimedia data streams from
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`the encoded stream;
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`a system controller coupled to the transport logic which
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`controls operations within the MPEG decoder system;
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`ASUS Exhibit 1003 - Page 15
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`an MPEG decoder coupled to receive one or more
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`multimedia data streams output from the transport logic,
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`wherein the MPEG decoder operates to perform MPEG
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`decoding on the multimedia data streams; and
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`a memory coupled to the MPEG decoder, wherein the
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`memory is used by the MPEG decoder during MPEG
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`decoding operations, wherein the memory stores code
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`and data useable by the system controller which enables
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`the system controller to perform control functions within
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`the MPEG decoder system, wherein the memory is used
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`by the transport logic for demultiplexing operations;
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`wherein the MPEG decoder is operable to access the
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`memory during MPEG decoding operations;
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`wherein the transport logic is operable to access the
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`memory to store and retrieve data during demultiplexing
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`operations; and
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`wherein the system controller is operable to access the
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`memory to retrieve code and data during system control
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`functions.
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`27. Claim 10 essentially recites a method claim corresponding to the
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`features in system claim 1.
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`28. Claim 16 is substantially similar to claim 1, with the exception that
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`“MPEG decoder” has been replaced with “video decoder.” As MPEG decoding is
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`–16–
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`ASUS Exhibit 1003 - Page 16
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`a specific form video decoding, the MPEG decoder art discussed in this declaration
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`applies to both claims. Therefore, while the analysis in my declaration may refer
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`to “MPEG decoding” rather than “video decoding” for simplicity, it is my opinion
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`that the same analysis applies to both, and claim 16 is invalid for the same reasons
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`recited with respect to claim 1.
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`29. The sole point of purported novelty in the patent is the use of a single
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`memory for use by transport, decode, and system controller functions. Because of
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`the size of memory components in 1996, the patentee found it impossible “to
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`combine the memory required for the transport and system controller functions
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`with the memory required for the MPEG decoder logic due to the memory size
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`requirements.” 087 Patent, 4:55-58. According to the patentee, “[t]he present
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`invention thus requires only a single memory, and thus has reduced memory
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`requirements compared to prior art designs.” 087 Patent, 5:7-10. This single
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`memory is also referred to as a “unified memory” or “single unified memory” in
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`the specification. See, e.g., 087 Patent, Title (“MPEG Decoder System and
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`Method Having a Unified Memory for Transport Decode and System Controller
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`Functions”), 17:2-6 (“Therefore, the present invention . . . includes a single unified
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`memory . . . . This reduces the required amount of memory, thus simplifying
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`system design and reducing system cost.”).
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`30. However, none of the challenged claims of the 087 Patent require a
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`–17–
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`ASUS Exhibit 1003 - Page 17
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`novel form of memory, memory structure, or memory management method to
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`consolidate separate memories into a single memory, only that a single memory be
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`used by transport, decode and system controller functions.1 As discussed below,
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`these functions were well known to those of skill in the art at the time the 087
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`Patent was filed, and the idea of consolidating separate components into one is
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`obvious.
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`i. The MPEG Standard and MPEG Transport, Decode and
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`System Controller Functions Were Well Known to Those of
`
`Skill in the Art
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`31. Well before the filing of the 087 Patent, MPEG standards such as
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`MPEG-1 and later MPEG-2 were well known to those skilled in the art. For
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`
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`1 I note that the 087 Patent specification refers to the “desire[] to keep the memory
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`requirements below a particular size of memory, such as 16 Mb,” 087 Patent, 4:50-
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`52, and discusses the relationship between memory bandwidth and memory size,
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`087 Patent, 14:67-15:4 (“[A]s the memory size decreases . . . the required amount
`
`of memory and/or processing bandwidth increases.”); 087 Patent, 15:4-30. The
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`087 Patent specification also adds up various well known memory usages, 087
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`Patent, Fig. 6A, but none of these requirements appear in the challenged claims.
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`–18–
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`ASUS Exhibit 1003 - Page 18
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`example, the MPEG-2 standard published as “ISO/IEC2 13818 is [] incorporated
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`by reference” into the 087 Patent. 087 Patent, 1:9-10. The MPEG-2 standard ITU-
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`T3 Recommendation H.222.0 (containing identical text to ISO/IEC 13818-1, see
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`Foreword), approved July 10, 1995, (“07/95 H.222.0”) (Ex. 1007) plainly
`
`documented that the MPEG transport, decode, and system controller functions
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`were well known in 1995.
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`32. For example, shown below is Figure Intro. 2 from 07/95 H.222.0
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`(MPEG-2), entitled “Information Technology - Generic Coding of Moving
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`Pictures and Associated Audio Information: Systems” as just one example showing
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`the well known functions:
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`
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`2 ISO/IEC (International Standards Organization / International Electrotechnical
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`Commission)
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`3
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`ITU-T
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`(International Telecommunication Union Telecommunication
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`Standardization Sector)
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`–19–
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`ASUS Exhibit 1003 - Page 19
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`33. Figure Intro. 2 depicts one example of the well known MPEG
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`Transport function (see “Transport Stream containing…” and “Transport Stream
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`demultiplexer and decoder”), and the well known MPEG Decode function (see
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`“Video decoder”).
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`34.
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`In addition, MPEG decoder systems under the control of a system
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`controller were common place when the above-mentioned MPEG standard was
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`released, including for example, in cable TV set-top boxes and PC video decoder
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`systems.
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`35. The above-mentioned MPEG standard also talked about memory
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`“buffers,” which were well known and widely used by 1995. Although the use of
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`specific types of buffers in memory is included as a purported limitation in claims
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`7, 8, and 9 of the 087 Patent, there was nothing novel about the use of buffers
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`generally or with respect to MPEG decoding specifically at the time of the 087
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`Patent’s purported invention. For example, over a year prior to the 087 Patent’s
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`–20–
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`ASUS Exhibit 1003 - Page 20
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`

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`
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`filing date, the 07/95 H.222.0 MPEG-2 standard expressly noted that “[m]ultiplex-
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`wide operations include the coordination of data retrieval of the channel, the
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`adjustment of clocks, and the management of buffers.” 07/95 H.222.0, Section
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`Intro. 7 (emphasis added).
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`ii. The MPEG Standard and MPEG Transport, Decode and
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`System Controller Functions Are Admitted Prior Art
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`36. Although I do not rely on the disclosure in the specification of the 087
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`Patent as admitted prior art for purposes of the prior art analysis in my declaration,
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`the specification confirms that the MPEG standard and MPEG transport, decode,
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`and system controller functions were widely known to those of skill in the art when
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`the application for the 087 Patent was filed.
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`37. For example, the “MPEG Background” section of the 087 Patent
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`specification discloses that each of the primary non-memory elements in the
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`independent claims were known by those of skill in the art:
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` “When an MPEG decoder receives an encoded stream, the MPEG
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`decoder reverses the above operations.” ’087 Patent, 3:60-61 (emphasis
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`added).
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` “An MPEG decoder system also typically includes transport logic
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`which operates to demultiplex received data into a plurality of individual
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`multimedia streams.” 087 Patent, 4:22-24 (emphasis added).
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`–21–
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`ASUS Exhibit 1003 - Page 21
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`
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` “An MPEG decoder system also generally includes a system controller
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`which controls operations in the system and executes programs or
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`applets.” 087 Patent, 4:24-27 (emphasis added).
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` “The MPEG decoder accesses the reference frames or anchor frames
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`stored in the external memory in order to reconstruct temporally
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`compressed frames.” 087 Patent, 4:15-21 (emphasis added).
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`38. Similarly, while not admitting that prior art systems used a single
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`memory, the “MPEG Background” section of the 087 Patent admits that those of
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`skill in the art would know that memory is required to perform the transport,
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`system control, and MPEG decoder functions described above:
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` “Prior art MPEG video decoder systems have also generally included a
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`separate memory for the transport and system controller functions.”
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`087 Patent, 4:33-35 (emphasis added).
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` “A typical MPEG decoder includes motion compensation logic which
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`includes local or on-chip memory. . . . The MPEG decoder also
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`typically stores the frames being reconstructed in the external memory.”
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`087 Patent, 4:14-21 (emphasis added).
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`39.
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`In addition, the specification of the 087 Patent illustrates that the
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`memory portions and buffers recited in claims 7-9 (i.e., video frame portion,
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`system controller portion, transport buffer portion, video decode buffer portion,
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`–22–
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`ASUS Exhibit 1003 - Page 22
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`
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`video display sync buffer, on-screen display buffer, and audio buffers) are trivial
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`limitations known in the art. Other than the portions of memory that are discussed
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`in the “MPEG Background” with respect to the well known MPEG transport,
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`decode, and control functions, the 087 Patent provides no disclosure regarding the
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`function or operation of these memory portions or buffers. Instead, as shown
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`below, the only disclosure is a list of memory portions or buffers with memory
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`allocations based on the well known television standards NTSC and PAL:4
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` “FIG. 9 illustrates the memory partitions of the external memory 212 for
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`each of the NTSC and PAL encoding formats according to one
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`embodiment of the invention. FIG. 9 illustrates the number of bytes of
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`memory size allocated for different purposes in the unified memory 212,
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`including number of bits for video frames, the vbv buffer, the video
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`decode buffer, the video-display synch buffer, the audio buffer, the
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`audio-video latency buffer, the audio-display synch buffer, the transport
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`buffer, the jitter buffer, the PES header overhead memory, the OSD,
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`and the system controller code and data storage. It is noted that FIG.
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`9 illustrates the memory partition according to one embodiment of the
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`invention, and it is noted that the memory 212 may be allocated
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`differently, as desired.” 087 Patent, 15:32-45 (emphasis added), Fig. 9.
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`
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`4 NTSC (National Television System Committee); PAL (Phase Alternating Line)
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`–23–
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`ASUS Exhibit 1003 - Page 23
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`
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`40. The 087 Patent not only admits that the memory allocation is not
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`novel (“the memory 212 may be allocated differently, as desired,”), but also that
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`the types of memory portions are not novel, as they are provided for “different
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`purposes” that are not described in the specification (e.g., see Fig. 6A, Fig. 9,
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`13:60-61, 15:41 for limited recitation of “on-screen display” or “OSD”). Thus, if
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`these memory portions were not known to those of skill in the art, the dependent
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`claims would lack sufficient written description.
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`41. Therefore, the patentee’s own admissions confirm my opinion that
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`MPEG decoding systems (and video decoding systems generally), and the
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`corresponding functions of transport, system control, and MPEG decoding were
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`well known in the art at the time the application for the 087 Patent was filed. The
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`sole remaining element of purported novelty – the abstract concept of using a
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`single memory to perform these functions – was expressly disclosed or would have
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`been obvious to those of skill in the art in light of numerous prior art references
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`available at the time.
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`IV. Claim Construction
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`42.
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`It is my understanding that in order to properly evaluate the 087
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`Patent, the terms of the claims must first be interpreted. It is my understanding that
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`the claims are to be given their broadest reasonable interpretation in light of the
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`specification. It is my further understanding that claim terms are given their
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`–24–
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`ASUS Exhibit 1003 - Page 24
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`
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`ordinary and accustomed meaning as would be understood by one of ordinary skill
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`in the art, unless the inventor has set forth a special meaning for a term.
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`43.
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`In order to construe the following claim terms, I have reviewed the
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`entirety of the 087 Patent, as well as its prosecution history. Any claim term not
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`construed in the patent or discussed below should be given its ordinary and
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`customary meaning.
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`i. “memory” / “first unified memory”
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`44. The claim term “memory” is found in the body of claims 1, 5, 7-9,
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`and 16 of the 087 Patent, and “first unified memory” is found in the body of claims
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`10 and 11 of the 087 Patent.
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`45. As discussed above, the sole point