UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`RICOH AMERICAS CORP.,
`Petitioner,
`
`v.
`
`ROUND ROCK RESEARCH, LLC,
`Patent Owner.
`
`
`Case (to be assigned)
`Patent 6,455,935
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT 6,455,935
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §42.100 et seq.
`
`
`Filed on behalf of Petitioner:
`
`Takayuki Yasaku
`(pro hac vice motion to be filed)
`Yasaku Foreign Law Office
`Suite 1102, 1-6-12 Nishi-Shimbashi
`Minato-ku
`Tokyo, Japan 105-0003
`Tel/Fax:+81-3-6457-9700/9710
`
`
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`Theodore J. Mlynar (Reg. No. 40,096 )
`Eric J. Lobenfeld
`(pro hac vice motion to be filed)
`Ira J. Schaefer (Reg. No. 26,802)
`Gary Serbin (Reg. No. 43,912)
`Helen Y. Trac (Reg. No. 65,096)
`HOGAN LOVELLS US LLP
`875 Third Avenue
`New York, N.Y. 10022
`Tel/Fax: 212.918.3000/3100
`
`

`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`INTRODUCTION ........................................................................................ 1
`
`II. MANDATORY NOTICES ........................................................................... 2
`
`A.
`
`B.
`
`C.
`
`Real Parties-in-Interest ........................................................................ 2
`
`Related Matters ................................................................................... 2
`
`Counsel and Service Information ........................................................ 2
`
`III. NOTICE OF FEES PAID ............................................................................. 3
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING ................................. 3
`
`V.
`
`PRECISE RELIEF REQUESTED ................................................................ 3
`
`VI. RELEVANT INFORMATION CONCERNING THE ’935 PATENT .......... 4
`
`A.
`
`B.
`
`Background on the ’935 Patent ........................................................... 4
`
`Person of Ordinary Skill in the Art...................................................... 4
`
`VII. CLAIM CONSTRUCTION .......................................................................... 5
`
`VIII. DETAILED ANALYSIS OF GROUNDS FOR UNPATENTABILITY ....... 5
`
`A. Ground 1: Kunishima ......................................................................... 6
`
`1.
`
`2.
`
`3.
`
`Kunishima Anticipates Independent Claim 8 ............................ 6
`
`Kunishima Anticipates Claim 9 .............................................. 16
`
`Kunishima Anticipates Claim 10 ............................................ 16
`
`B.
`
`Ground 2: Fushida ........................................................................... 16
`
`1.
`
`2.
`
`3.
`
`Fushida Anticipates Independent Claim 8 ............................... 17
`
`Fushida Anticipates Claim 9 ................................................... 32
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`Fushida Anticipates Claim 10 ................................................. 32
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`C.
`
`Ground 3: Kunishima In Combination With Fushida ....................... 32
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`1.
`
`2.
`
`3.
`
`Kunishima In Combination With Fushida Renders
`Independent Claim 1 Obvious ................................................. 33
`
`Kunishima In Combination With Fushida Renders
`Claim 9 Obvious ..................................................................... 34
`
`Kunishima In Combination With Fushida Renders
`Claim 10 Obvious ................................................................... 34
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`IX. CONCLUSION .......................................................................................... 35
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`I.
`
`INTRODUCTION
`
`Petitioner Ricoh Americas Corp., (“Petitioner”) challenges Claims 8, 9, and
`
`10 of U.S. Patent No. 6,455,935 (the “’935 Patent”). The ’935 Patent generally
`
`relates to a semiconductor device with a contact comprising “a mixed metal
`
`silicide/nitride layer which has a sufficient thickness to provide low sheet
`
`resistance without excessively consuming the underlying substrate.” Ex. 1001
`
`(’935 Patent) at Abstract. Specifically, the ’935 Patent is directed to a
`
`conventional self-aligned silicide (a/k/a “salicide”) contact for a semiconductor
`
`device (e.g., a MOSFET) that extends minimally into a diffusion region (e.g.,
`
`source/drain) in the substrate. See Ex. 1001 at Figs. 2A and 2B, 4:61-6:15.
`
`The named inventors of the ’935 Patent did not, however, invent any of the
`
`concepts required by Claims 8, 9, or 10. Numerous prior art references disclosed
`
`the creation of a self-aligned silicide contact extending minimally into the shallow
`
`active area of a transistor, including: (1) Japanese Laid-Open Patent Publication
`
`H06-318563, “Semiconductor Device and Method for Producing Same” published
`
`November 15, 1994 (“Kunishima”), Ex. 1003; and (2) U.S. Patent No. 6,008,111
`
`(“Fushida”), Ex. 1005. A certified English-language translation of Kunishima is
`
`provided as Ex. 1004.
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`As detailed below, Claims 8, 9, and 10 of the ’935 Patent are anticipated by
`
`each of Kunishima and Fushida, or rendered obvious in view of a combination
`
`thereof.
`
`II. MANDATORY NOTICES
`
`A. Real Parties-in-Interest
`
`The real parties-in-interest in this proceeding are Petitioner, Ricoh Co., Ltd.,
`
`Ricoh Americas Holdings, Inc., Ricoh Imaging Co., Ltd., Ricoh Imaging Americas
`
`Corp., and Ricoh Electronics, Inc.
`
`B. Related Matters
`
`The ’935 Patent has been asserted in the following cases:
`
`Defendant
`Case No.
`C.A. No. 15-157 Ricoh Americas Corp., Ricoh Imaging
`Americas Corp., and Ricoh Electronics, Inc.
`C.A. No. 14-1456 SanDisk Corp.
`C.A. No. 14-1457 Canon Inc. et. Al
`C.A. No. 14-1458 JVC Kenwood Corp.
`C.A. No. 14-1491 Nintendo Co., Ltd. et. al.
`
`
`C. Counsel and Service Information
`
`Jurisdiction
`D. Del.
`
`D. Del.
`D. Del.
`D. Del.
`D. Del.
`
`Lead counsel is Theodore J. Mlynar (Reg. No. 40,096) and backup counsel
`
`are Ira. J. Schaefer (Reg. No. 26,802), Eric J. Lobenfeld (pro hac vice motion to be
`
`filed), Gary Serbin (Reg. No. 43,912), Takayuki Yasaku (pro hac vice motion to be
`
`filed), and Helen Y. Trac (Reg. No. 65,096). Service information for Petitioner in
`
`this matter is as follows:
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`Post and Hand Delivery
`
`Email
`
`Telephone / Facsimile
`
`III. NOTICE OF FEES PAID
`
`Hogan Lovells US LLP
`875 Third Avenue
`New York, N.Y. 10022
`ted.mlynar@hoganlovells.com
`ira.schaefer@hoganlovells.com
`eric.lobenfeld@hoganlovells.com
`gary.serbin@hoganlovells.com
`takayuki.yasaku@yasaku-law.com
`helen.trac@hoganlovells.com
`212.918.3000 / 212.918.3100
`
`Fees are submitted herewith. If any additional fees are due at any time
`
`during the proceeding, the undersigned authorizes the Office to charge such fees to
`
`Deposit Account No. 50-1349.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`
`Petitioner certifies that the ’935 Patent is available for inter partes review,
`
`that it is not barred or estopped from requesting this review, and that this Petition is
`
`being filed within one year after Petitioner was served with a complaint for
`
`infringement of the ’935 Patent.
`
`V.
`
`PRECISE RELIEF REQUESTED
`
`The relief requested is cancellation of the challenged claims, as follows:
`
`Ground
`
`1
`
`2
`
`3
`
`References
`
`Kunishima
`
`Fushida et al.
`
`Claims Basis
`
`8-10
`
`102
`
`8-10
`
`102
`
`Kunishima in combination with Fushida et al.
`
`8-10
`
`103
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`VI. RELEVANT INFORMATION CONCERNING THE ’935 PATENT
`
`A. Background on the ’935 Patent
`
`The ’935 Patent issued from U.S. Patent Appl. No. 09/658,780, filed on
`
`September 11, 2000. The ‘935 Patent is a continuation of U.S. Patent Appl. No.
`
`09/026,104, filed on February 19, 1998, and issued as U.S. Patent 6,147,405.
`
`In the first and only Office Action, the pending claims were rejected under
`
`35 U.S.C. § 102(e) as being anticipated by O’Brien et al., U.S. Pat. No. 5,888,903.
`
`Ex. 1002-50. In response, the Applicant argued that claim 38 of the application
`
`(issued claim 1) and its dependent claims were not anticipated by O’Brien, because
`
`O’Brien did not disclose the “metal silicide layer extending into the substrate
`
`below the upper surface of the substrate by an amount less than about 30% of the
`
`metal silicide thickness.” Ex. 1002-55 and 56. All pending claims were
`
`subsequently allowed. Ex. 1002-65.
`
`B.
`
`Person of Ordinary Skill in the Art
`
`A person of ordinary skill in the art (“POSITA”) in the field of the ’935
`
`Patent would have had a good working knowledge of semiconductor
`
`(microelectronic) devices and their methods of manufacture. The person would
`
`have gained this knowledge through an undergraduate Bachelor of Science degree
`
`in electrical engineering, applied physics, materials science, or a comparable field
`
`relating to semiconductor manufacturing and three years of related work
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`experience, or a Master of Science degree in one of those fields and two years of
`
`related work experience. Ex. 1010 at ¶¶9-11.
`
`VII. CLAIM CONSTRUCTION
`
`Claims must be given their broadest reasonable construction in light of the
`
`specification and prosecution history in this proceeding. 37 C.F.R. § 42.100(b);
`
`Microsoft Corp. v. Proxyconn, Inc., 789 F. 3d 1292, 1297-1298 (Fed. Cir. 2015).
`
`Petitioner’s position, explicitly or implicitly, regarding claim scope is not to be
`
`taken as a concession regarding the appropriate scope to be given to the terms
`
`below, or to any other claim terms, in a court or other adjudicative body having
`
`different claim interpretation standards. All claim terms are to be given their
`
`broadest reasonable interpretation.
`
`The challenged claims use terms, such as “self-aligned silicide contact” and
`
`“junction depth,” that have their ordinary meaning, as explained in the ’935 patent,
`
`and therefore do not require construction.
`
`VIII. DETAILED ANALYSIS OF GROUNDS FOR UNPATENTABILITY
`
`This section explains how the Kunishima and Fushida references each
`
`anticipate, and in combination render obvious, the challenged claims of the ’935
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`Patent.1 Additional support for those conclusions is set forth in the Declaration of
`
`Dr. Alexander D. Glew. (Ex. 1010).
`
`A. Ground 1: Kunishima
`
`Kunishima is Japanese Laid-Open Patent Publication H06-318563, entitled
`
`“Semiconductor Device and Method for Producing Same.” Kunishima was
`
`published in November 1994, and is prior art under 35 U.S.C. § 102(b).
`
`Kunishima discloses a self-aligned silicide contact which intrudes only 150
`
`Å into the 1000 Å deep diffusion layer of a transistor. See, generally, Ex. 1003 at
`
`Figs. 4(a)-4(c) and 5(a)-5(c); Ex. 1004-11 and 12; Ex. 1010 at ¶¶19-26.
`
`1. Kunishima Anticipates Independent Claim 8
`
`Claim 8[a]: A self-aligned silicide contact extending below a substrate surface
`into a shallow junction transistor active area,
`
`Kunishima discloses a self-aligned silicide contact extending below a
`
`substrate surface into a shallow junction transistor active area. Ex. 1010 at ¶¶19-22.
`
`Specifically, Kunishima refers to “salicide,” which the ’935 patent explains is a
`
`shorthand term for self-aligned silicide. Ex. 1001 at 1:48-49.
`
`
`1 Petitioner takes no position herein as to whether the challenged claims are
`
`invalid under 35 U.S.C. §§ 101 or 112, with the understanding that this is not the
`
`appropriate forum for such challenges. Petitioner reserves the right to present these
`
`and other challenges as to the ’935 Patent’s validity in other fora.
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`
`Claim 8[a]
`
`A self-aligned
`silicide contact
`extending
`below a
`substrate
`surface into a
`shallow
`junction
`transistor active
`area,
`
`Kunishima
`
`“[Goal] To provide a semiconductor device having an
`electrode wiring structure that has low contact resistance and
`high thermal stability on a shallow diffusion layer
`measuring 0.1 µm or less.
`[Configuration] There is an impurity diffusion layer 4 on a
`semiconductor substrate 1 having a (001) surface as a
`principal surface, and selective vapor phase epitaxy is used to
`form a monocrystalline refractory metal compound film 15
`of orthorhombic crystal on the entire surface of the impurity
`diffusion layer 4 or on a portion exposed by an opening in
`an insulation film.
`[Effects] The contact resistance of the silicide/Si interface
`can be reduced, and highly reliable junctions can be
`implemented.” Ex. 1004-2 to 3(emphasis added).
`
`“[Field of industrial applicability] The present invention
`relates to a semiconductor device having a metal compound
`film on a shallow impurity layer.” Ex. 1004-5 (emphasis
`added).
`
`“One conceivable method for solving the above-described
`problem is to metallize either a part of the impurity layer or
`the inside of the contact hole openings; for example, there is a
`method called salicide. This is shown in FIG. 6.
`[0003] This method comprises first forming an 800 nm
`field oxide film 2 by embedding onto an n-type Si substrate
`1. A 10 nm gate oxide film 31 is formed on an element
`formation region surrounded by the oxide film 2, and a 150
`nm doped polycrystalline layer 32 as a gate electrode is
`formed, and thereafter the foregoing is etched into a gate
`shape to provide a laminated film. Later, an insulation film 35
`is deposited to a thickness of 150 nm, and then etched
`anisotropically to form an insulation film 35 with a thickness
`of approximately 150 nm on sidewalls of the gate electrodes.
`Next, a known ion implantation method is used to form an
`impurity diffusion layer 4 on the substrate 1, and a
`titanium (Ti) film 13 is then deposited to a thickness of 40
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`
`Claim 8[a]
`
`Kunishima
`
`nm (FIG. 6(a)). This is heated over by lamp annealing to
`form a titanium disilicide (TiSi2) film 15 over the impurity
`diffusion layer 4 (FIG. 6(b)). Then, the unreacted Ti is
`removed by etching, and finally an insulation film 10 is
`provided and an opening is formed, and then an interconnect
`17 is formed (FIG. 6(c)).” Ex. 1004-5 (emphasis added).
`
`Ex. 1003 at Figs. 6(a)-6(c).
`
`“[0031] Next, another example of the present invention shall
`be described with reference to FIG. 4. First, an 800 nm field
`oxide film 2 is formed by thermal oxidation on an n-type Si
`
`
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`
`Claim 8[a]
`
`Kunishima
`
`+ ions are
`substrate 1 having (001) as a principal surface. BF2
`implanted at 5 x 1015 cm-2 with 35 eV in an element formation
`region surrounded by this oxide film 2, and a heat treatment is
`applied at 1000°C for 20 seconds in an N2 atmosphere thereby
`forming a shallow p+ diffusion layer 4 measuring
`approximately 0.1 µm. Next, a laminated film of a CVD-
`SiO2 film 101 and a BPSG film 102 is deposited at a thickness
`of 1. 0 µm over the entire surface as an interlayer insulation
`film, then a contact hole is provided on the diffusion layer
`(FIG. 4(a)). The substrate is washed with an aqueous solution
`of dilute hydrofluoric acid, and thereafter introduced into a
`vacuum device where the temperature is raised to 600°C. At
`this time, the pressure inside the chamber is held at 1 x 10-6
`Torr or below at all times. Thereafter, TiCl3(CH3) gas is
`introduced into the chamber. At this time, prior to reaching the
`Si substrate, the TiCl3(CH3) gas only reaches the film
`formation region after having passed through an Si heating
`element region that has been heated to 800°C. At this time, the
`pressure of the TiCl3(CH3) gas is 1 x 10-4 Torr. As a result, a
`TiSi2 film 15 measuring approximately 15 nm is selectively
`formed only at the portion where the diffusion layer is
`exposed inside the contact hole (FIG. 4(b)). Thereafter, a
`CVD-W film 11 is continuously grown by selective vapor
`phase epitaxy only on the TiSi2 surface in the contact hole, and
`the upper-layer electrode wiring is completed with a laminated
`film of a Ti film 113, a TiN film 111, and an Al-Si-Cu film 112
`(FIG. 4(c)).” Ex. 1004-11 (emphasis added).
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`
`Claim 8[a]
`
`Kunishima
`
`
`
`Ex. 1003 at Figs. 4(a)-4(c).
`
`“[0034] The first and second embodiments above have
`described steps for using TiCl4 and Si to form TiSi2. A
`third embodiment where a mixed gas of TiCl4 and SiH4 is
`used will [be] explained with reference to FIG. 5.
`[0035] In a similar manner to the second embodiment, a field
`oxide film 2, a shallow p+ diffusion layer 4, and a
`laminated film of a CVD-SiO2 film 101 and a BPSG film
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`
`Claim 8[a]
`
`Kunishima
`
`102 are formed on an n-type Si substrate 1 having (001) as
`the principal surface, and then a contact hole is provided
`over the diffusion layer (FIG. 5(a)). This substrate is washed
`with an aqueous solution of dilute hydrofluoric acid, and
`thereafter introduced into a vacuum device where the
`temperature is raised to 650°C. At this time, the pressure
`inside the chamber is held at 1 x 10-6 Torr or below at all
`times. Thereafter, TiCl4 gas and SiH4 gas are introduced into
`the chamber. At this time, the TiCl4 gas and the SiH4 gas are
`introduced to the chamber from separate ports, and prior to
`reaching the substrate, the TiCl4 gas passes through an Si
`heating element region that has been heated to 900°C or above
`before reaching the film formation region. At this time, the
`pressures of the TiCl4 gas and the SiH4 gas are 3 x 10-4 Torr
`and 1 x 10-3 Torr, respectively. As a result, an epitaxial TiSi2
`film 15 measuring approximately 0.7 µm is selectively
`embedded only at the portion where the diffusion layer is
`exposed inside the contact hole (FIG. 5(b)). At this time,
`the penetration depth of the TiSi2 film 15 into the Si
`substrate is approximately 15 nm. Thereafter, a laminated
`film of a Ti film 113, a TiN film 111, and an Al-Si-Cu film 112
`is formed, thus completing the upper-layer electrode wiring
`(FIG.5(c)).” Ex. 1004-12 (emphasis added).
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`Claim 8[a]
`
`Kunishima
`
`Ex. 1003 at Fig. 5(c).
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`Claim 8[b]: the active area having a junction depth of no more than about
`
`
`1,000 Å,
`
`In both the second and third examples of Kunishima, shallow p+ diffusion
`
`layer 4 is an active area having a junction depth of no more than about 1,000 Å (=
`
`100 nm = 0.1 µm). See Ex. 1010 at ¶24.
`
`Claim 8[b]
`
`the active area
`having a
`junction depth
`of no more than
`about 1,000 Å,
`
`Kunishima
`
`“[0031] Next, another example of the present invention shall
`be described with reference to FIG. 4. First, an 800 nm field
`oxide film 2 is formed by thermal oxidation on an n-type Si
`+ ions are
`substrate 1 having (001) as a principal surface. BF2
`implanted at 5 x 1015 cm-2 with 35 eV in an element formation
`region surrounded by this oxide film 2, and a heat treatment is
`applied at 1000°C for 20 seconds in an N2 atmosphere thereby
`forming a shallow p+ diffusion layer 4 measuring
`approximately 0.1 µm.” Ex. 1004-11 (emphasis added).
`
`
`
`Ex. 1003 at Fig. 4(a).
`
`“[0035] In a similar manner to the second embodiment, a field
`oxide film 2, a shallow p+ diffusion layer 4, and a laminated
`film of a CVD-SiO2 film 101 and a BPSG film 102 are formed
`on an n-type Si substrate 1 having (001) as the principal
`surface, and then a contact hole is provided over the diffusion
`layer (FIG. 5(a)).” Ex. 1004-12 (emphasis added).
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`
`Claim 8[b]
`
`Kunishima
`
`Ex. 1003 at Fig. 5(a).
`
`
`
`
`Claim 8[c]: the contact extending below the substrate surface into the active
`area by no more than about 30% of the junction depth.
`
`
`In both the second and third examples of Kunishima, the TiSi2 film 15 of the
`
`contact structure penetrates into the 1,000 Å (=100 nm) active area about 150 Å
`
`(=15 nm) or less. The TiSi2 film 15 thus extends below the substrate surface into
`
`the active area by no more than about 15% of the junction depth. See Ex. 1010 at
`
`¶¶25-26.
`
`Claim 8[c]
`
`the contact
`extending
`below the
`substrate
`surface into
`the active
`area by no
`more than
`about 30% of
`the junction
`depth.
`
`Kunishima
`
`“As a result, a TiSi2 film 15 measuring approximately 15 nm
`is selectively formed only at the portion where the diffusion
`layer is exposed inside the contact hole (FIG. 4(b)).
`Thereafter, a CVD-W film 11 is continuously grown by
`selective vapor phase epitaxy only on the TiSi2 surface in the
`contact hole, and the upper-layer electrode wiring is
`completed with a laminated film of a Ti film 113, a TiN film
`111, and an Al-Si-Cu film 112 (FIG. 4(c)).” Ex. 1004-11
`(emphasis added)
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`
`Claim 8[c]
`
`Kunishima
`
`
`
`Ex. 1003 at Fig. 4(c).
`
`“As a result, an epitaxial TiSi2 film 15 measuring
`approximately 0.7 µm is selectively embedded only at the
`portion where the diffusion layer is exposed inside the contact
`hole (FIG. 5(b)). At this time, the penetration depth of the
`TiSi2 film 15 into the Si substrate is approximately 15 nm.
`Thereafter, a laminated film of a Ti film 113, a TiN film 111, and
`an Al-Si-Cu film 112 is formed, thus completing the upper-layer
`electrode wiring (FIG.5(c)).” Ex. 1004-12 (emphasis added).
`
`Ex. 1003 at Fig. 5(c).
`
`
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`
`2. Kunishima Anticipates Claim 9
`
`Claim 9: The self-aligned silicide contact of claim 8, wherein the contact
`extends below the substrate surface into the active area by no more than about
`25% of the junction depth.
`
`See section VIII.A.1. Claim 8[c], supra.
`
`3. Kunishima Anticipates Claim 10
`
`Claim 10: The self-aligned silicide contact of claim 9, wherein the contact
`extends below the substrate surface into the active area by no more than about
`20% of the junction depth.
`
`See section VIII.A.1. Claim 8[c], supra.
`
`B. Ground 2: Fushida
`
`U.S. Patent No. 6,008,111 (“Fushida”), entitled “Method of Manufacturing
`
`Semiconductor Device,” was filed on March 13, 1997. Fushida is prior art under
`
`35 U.S.C. §102(e).
`
`Fushida discloses semiconductor manufacturing methods for producing self-
`
`aligned silicide (a/k/a salicide) contacts along with several “experiments”
`
`involving different thicknesses and depths of a cobalt silicide layer 14. Source and
`
`drain regions 9 and 10 which are 1000Å (= 100 nm) deep are created in silicon
`
`substrate 1. In Fushida’s “fourth experiment,” a Co silicide layer is created which
`
`extends only 182Å (= 18.2 nm) below the surface of the silicon substrate 1. See,
`
`generally, Ex. 1005 at 4:45-8:65 and Figs. 2(A)-2(J); Ex. 1010 at ¶¶31-37.
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`
`1.
`
`Fushida Anticipates Independent Claim 8
`
`Claim 8[a]: A self-aligned silicide contact extending below a substrate surface
`into a shallow junction transistor active area,
`
`Fushida discloses a self-aligned silicide contact extending below a substrate
`
`surface into a shallow junction transistor active area. Ex. 1010 at ¶¶31-33.
`
`Claim 8[a]
`
`A self-aligned
`silicide contact
`extending
`below a
`substrate
`surface into a
`shallow
`junction
`transistor active
`area,
`
`Fushida
`
`“Such a process that gate, source and drain regions are
`simultaneously formed as silicides to lower their resistances,
`i.e., a salicide (self-align silicide) process has become
`indispensable technology.” (Ex. 1005 at 1:24-27.) (emphasis
`added)
`
`“Next, ordinary manufacturing steps for the MOS
`transistor in which Co salicide is applied to surface layers
`of the gate, source, and drain electrodes will be explained.
`
`First, as shown in FIG. 1A, a surface of a region of a silicon
`substrate 101 isolated by a LOCOS oxide film 102 is
`thermally oxidized to thereby form a gate oxide film 103 of an
`about 50 Å thickness. In turn, a polysilicon film 104 of an
`about 1500 Å thickness is formed on an overall surface by the
`CVD method.
`
`Then, as shown in FIG. 1B, after any one of boron,
`phosphorous, and arsenic is ion-implanted into the polysilicon
`film 104, a gate electrode 105 is formed by patterning the
`polysilicon film 104. Thereafter, shallow impurity injection
`layers 106 are formed by ion-implanting phosphorous, for
`example.
`
`Next, a silicon oxide film of an about 1000 Å thickness is
`formed by the CVD method and then anisotropic etching is
`carried out until an upper surface of the gate electrode 105 is
`exposed. As shown in FIG. 1C, the silicon oxide films remain
`on both side surfaces of the gate electrode 105 to be utilized as
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`17
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`

`
`Claim 8[a]
`
`Fushida
`
`side walls 107.
`
`After this, and after deep impurity injection layers 108 are
`formed by ion-implanting phosphorous, the shallow impurity
`injection layers 106 and the deep impurity injection layers 108
`are activated by annealing process. As a result, the source
`layer (109) and the drain layer (110) are formed on both sides
`of the gate electrode 105 in the silicon substrate 101 as a LDD
`structure.
`
`Subsequently, after silicon oxide films (natural oxide films)
`formed on surfaces of the gate electrode 105, the source layer
`109 and the drain layer 110 are removed by buffered hydrogen
`fluoride, as shown in FIG. 1D, a cobalt film 111 of an about
`100 Å thickness and a titanium nitride film 112 of an about
`300 Å thickness are formed and then silicide formation is
`executed by RTA (rapid thermal annealing) process at 550° C.
`for 30 seconds to form cobalt silicide layers 113.
`
`Then, as shown in FIG. 1E, by removing the titanium nitride
`film 112 and the unreacted cobalt film 111 and executing RTA
`process at 850° C. for 30 seconds, cobalt silicide layers 113
`formed on the gate electrode 105, the source layer 109 and the
`drain layer 110 are made to have further low resistance.
`
`Such salicide technology is a basic manufacturing step.”
`(Id. at 1:51-2:14.) (emphasis added)
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`18
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`

`
`Claim 8[a]
`
`Fushida
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`19
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`

`
`Claim 8[a]
`
`Fushida
`
`Ex. 1005 at Figs. 1(a)-1(e).
`
`“The cobalt silicide layer is used for the source layer and the
`drain layer of the MOS transistor and the like to reduce their
`resistance.” (Id. at 3:14-16.)
`
`“FIGS. 2A to 2J are sectional views illustrating steps of
`manufacturing a semiconductor device according to an
`embodiment of the present invention.
`
`At first, as shown in FIG. 2A, a surface of a region of a
`silicon substrate 1 isolated by LOCOS oxide films 2 is
`thermally oxidized to thus form a gate oxide film 3 of about 5
`nm thickness. Subsequently, a polysilicon film 4 is formed on
`the gate oxide film 3 and the LOCOS oxide film 2 by the CVD
`method to have a thickness of about 150 nm.
`
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`20
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`

`
`Claim 8[a]
`
`Fushida
`
`Then, as shown in FIG. 2B, for example, arsenic is ion-
`implanted into the polysilicon film 4, then the gate oxide film
`3 and the polysilicon film 4 are patterned to a gate electrode 5
`by means of the polysilicon film 4. The gate electrode 5 is
`formed to cross the center area of a region isolated by LOCOS
`oxide films 2. After this, a shallow impurity implanted
`layer 6 is formed by ion-implanting arsenic into the silicon
`substrate 1 with the use of the gate electrode 5 as a mask.
`In this ion-implantation, a dosage is 3×1014 atm/cm2 and
`acceleration energy is 10 keV, for purposes of example.
`
`In turn, a silicon oxide film of about 100 nm thickness is
`formed on an overall surface by the CVD method. Then, the
`silicon oxide film is etched in the vertical direction by means
`of anisotropic etching until an upper surface of the gate
`electrode 5 is exposed, so that the silicon oxide film remains
`on both sides of the gate electrode 5 as side walls 7, as shown
`in FIG. 2C. The anisotropic etching is carried out by reactive
`ion etching (RIE).
`
`Then, arsenic is ion-implanted into the silicon substrate 1
`using the gate electrode 5 as a mask to form a deep
`impurity injection layer 8. In this ion-implantation, a dosage
`is 2×1015 atm/cm2 and acceleration energy is 40 keV, for
`example.
`
`Next, in terms of RTA process at 1000° C. for ten seconds,
`arsenic implanted in the gate electrode 5 is diffused and
`simultaneously arsenic implanted in the shallow impurity
`injection layer 6 and the deep impurity injection layer 8 is
`activated. As a result, as shown in FIG. 2D, a source layer 9
`and a drain layer 10 are formed on both sides of the gate
`electrode 5 in the silicon substrate 1 as an LDD structure. In
`this event, the source layer 9 and the drain layer 10 are
`formed to a depth about 100 nm from a surface of the
`silicon substrate 1 in regions which are not overlapped with
`the side walls 7.
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`

`
`Claim 8[a]
`
`Fushida
`
`
`Thereafter, as shown in FIG. 2E, germanium is ion-implanted
`into an overall surface including the source layer 9 and the
`drain layer 10 to thereby form an amorphous (non-
`crystalline) layer 11 on surfaces of the gate electrode 5, the
`source layer 9 and the drain layer 10. A dosage of this ion-
`implantation is set more than 8×1013 atm/cm2. A magnitude of
`acceleration energy of this ion-implantation is selected such
`that the amorphous layer 11 is formed shallow rather than at
`the bottom of the source layer 9 and the drain layer 10 and that
`the amorphous layer 11 should not disappear in first annealing
`for silicide formation executed later but disappear in second
`annealing for silicide formation executed further later.
`
`More particularly, though depending on a depth of the silicide
`layer to be formed later, a magnitude of acceleration energy is
`selected in a range of 20 to 40 keV in case the source layer 9
`and the drain layer 10 are 100 nm in depth.
`
`Next, natural oxide films (silicon oxide films) formed on
`surfaces of the gate electrode 5, the source layer 9 and the
`drain layer 10 are removed by buffered hydrogen fluoride
`(BHF). This BHF is a mixed solution in which hydrogen
`fluoride and water are mixed at a rate of 2:100. A time
`required for such removing is about 60 seconds.
`
`As shown in FIG. 2F, a cobalt (Co) film 12 of about 8 to 20
`nm thickness and a titanium nitride (TiN) film (cap layer) 13
`of about 30 nm thickness are formed by sputtering in sequence
`on an entire surface of the resultant structure.”
`(Id. at 4:45-5:48.) (emphasis added)
`
`“Succeedingly, the first annealing for silicide formation is
`carried out. In other words, as shown in FIG. 2G, if
`respective surfaces of the gate electrode 5, the source layer
`9 and the drain layer 10 are formed as silicides in terms of
`RTA at 400 to 450° C. for 30 seconds in nitrogen or argon
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`22
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`

`
`Claim 8[a]
`
`Fushida
`
`atmosphere, cobalt silicide layers 14 made of Co2 Si or CoSi
`are formed in upper surface regions of the amorphous
`layers 11. The cobalt silicide layers 14 are not formed if the
`RTA temperature is less than 400° C., but the RTA
`temperature in excess of 450° C. is not desired since regions
`beneath the amorphous layers 11 are recrystallized. According
`to this annealing, besides the cobalt silicide layers 14 are
`spread into upper surface regions of the amorphous layers
`11 to thus cause disappearance of such regions, bottom surface
`regions of the amorphous layers 11 are recrystallized.
`Therefore, the amorphous layers 11 can be prevented from
`disappearing in this stage by optimizing ion implantation
`energy of germanium described above to thus remain though
`they are very thin.
`
`Then, as shown in FIG. 2H, the titanium nitride film 13 is
`removed by immersing a resultant structure in a hydrogen
`peroxide/ammonia liquid mixture solution
`(H2 O2 :NH4 OH:H2 O=1:1:4) heated up to 70° C. for 180
`seconds, then the unreacted cobalt film 12 is removed by
`immersing a resultant structure in a sulfuric acid/hydrogen
`peroxide mixture solution (H2 SO4 :H2 O2 =3:1) for twenty
`minutes. In this case, the cobalt silicide layers 14 remain as
`they are.
`
`Next, the second annealing for silicide formation is carried
`out. In other words, as shown in FIG. 2I, the cobalt silicide
`layers 14 are heated in nitrogen or argon atmosphere within
`the temperature range of 600 to 900° C. Thereby, the cobalt
`silicide layers 14 are changed from Co2 Si or CoSi to
`CoSi2 to lower their resistance. In this case, if annealing
`temperature is less than 600° C., low resistance of the cobalt
`silicide layers 14 cannot be achieved since CoSi2 is hard to be
`generate. Conversely, if anneali