`Devoe et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,366,443 B1
`*Apr. 2, 2002
`
`US006366443B1
`
`(54) CERAMIC CHIP CAPACITOR OF
`
`4,819,128 A * 4/1989 Florian et al. ............ .. 361/321
`
`CONVENTIONAL VOLUME AND EXTERNAL
`
`FORM HAVING INCREASED CAPACITANCE
`
`
`
`fgglgsggggggsggggsggfggs RELIABLY CONNECTING T0
`
`POSITIONALLY-TOLERANT EXTERIOR
`PADS THROUGH MULTIPLE REDUNDANT
`VIAS
`
`4,864,465 A * 9/1989 Robbins . . . . . . . . .
`
`2 j:
`
`lsnglgson et a1
`
`. . . .. 361/320
`
`,
`
`,
`
`c0 . . . . . . . . . . . . . .
`
`. . . ..
`
`A 5,590,016 A * 12/1996 Fu]1sh1~r0 et al. .......... .. 361/313 Mason. .......... ..
`
`
`5,599,414 A * 2/1997 Roethlingshoefer ........ .. 156/89
`5,712,758 A * 1/1998 Amano e161. ......... .. 361/321.2
`5,757,611 A * 5/1998 Gurovich et al. ...... .. 361/321.4
`5,855,995 A * 1/1999 Haq et al. ................. .. 438/210
`
`(76) Inventors: Daniel Devoe, 1106 Barcelona, San
`Diego, CA (US) 92107; Alan D. Devoe,
`5715 Waverly Ave., La Jolla, CA (US)
`92037; Lambert [)evoe, 26213 Via
`Luis, Laguna Niguel, CA (Us) 92607
`
`* Cited by examiner
`
`Primary Exami't@r—Anth9ny Dinkins
`Assistant Examiner—Eric Thomas
`(74) Attorney, Agent, or Firm—Wood, Herron & Evans,
`L.L.P.
`
`Notice:
`
`*
`)
`
`(
`
`This patent issued on a continued pros
`ABSTRACT
`(57)
`ecution application ?led under 37 CFR
`A ceramic capacitor typically 10 mils to 340 mils square by
`1~53(d)> and is Subleq to the twenty Year
`Pawnt term Provlslons of 35 USC typically 4—20 mils thickness With areas of metalliZation, or
`154(21)(2)-
`pads, to Which electrical connections may be made on,
`_
`_
`_
`_
`typically, each of tWo opposite exterior surfaces, has embed
`Sub]eCt_tO any dlsclalmeri the term of thls
`ded at least one, and normally tWo or more, metalliZation
`Patent 15 extended or adlusted under 35
`planes at close, typically 0.5 mil, separation. Each interior
`U'S'C' 154(k)) byO days‘
`metalliZation plane connects through multiple redundant
`vias, as are preferably made by (ii) punching, (ii) drilling,
`(iii) laser drilling, or (iv) radiation patterning of a green
`ceramic sheet having a photosensitive binder, to an associ
`ated surface pad or trace. The vias are both numerous and
`redundant, typically being of 2 mil diameter on 10 mil
`centers in a pin grid array pattern over and through entire
`Ceramic layers of the Capacitor, permitting both (1) easy
`fabrication Without @Xacting alignment of registration
`betWeen layers, and (ii) loW Equivalent Series Resistance
`(ESR) in the ?nished capacitor. The composite structure so
`created exhibits increased capacitance over that Which
`Would alternatively exist should no electrically-connected
`interior metalliZation planes be present.
`
`(21) APPL NOJ 08/987,463
`-
`_
`Dec‘ 9’ 1997
`(22) Flled'
`(51) Int. Cl.7 .......................... .. H01G 4/06; H01G 4/20;
`H01G 4/005
`(52) US. Cl. ................... .. 361/313; 361/321.2; 361/303
`(58) Field Of Search ............................ .. 361/3011, 302,
`361/303, 3061, 3063, 307, 311, 312, 313,
`320 3211 3212 3213 3214 3215
`,
`,
`,
`,
`,
`References Cited
`U S PATENT DOCUMENTS
`
`(56)
`
`4,439,813 A * 3/1984 Dougherty et al. ....... .. 361/321
`
`28 Claims, 6 Drawing Sheets
`
`7361/
`
`K 77a [/40
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`//// ////]
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`US 6,366,443 B1
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`1
`CERAMIC CHIP CAPACITOR OF
`CONVENTIONAL VOLUME AND EXTERNAL
`FORM HAVING INCREASED CAPACITANCE
`FROM USE OF CLOSELY-SPACED
`INTERIOR CONDUCTIVE PLANES
`RELIABLY CONNECTING TO
`POSITIONALLY-TOLERANT EXTERIOR
`PADS THROUGH MULTIPLE REDUNDANT
`VIAS
`
`BACKGROUND OF THE INVENTION
`
`10
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`2
`said. “A number of our customers can’t place them at all.”
`To combat these complaints, some companies such as
`Murata Electronics North America Inc. are developing Ways
`of handling the components. The manufacturer has created
`a small plastic case With a ?ip top that can hold 50,000 to
`80,000 pieces. This box is slipped into a slot on the place
`ment equipment. In comparison, a typical tape-and-reel
`holds about 5,000 parts. Although Murata developed the
`bulk cassette technology, others noW offer it. For example,
`Kemet Will ship the 0603 and 0402 siZes of its capacitors
`that use the X7R and COG dielectrics in cassettes can hold
`15,000 units of 0603 chips and 50,000 units of 0402 chips.
`Another emerging solution is the use of capacitor arrays,
`in Which several components are encased in a single pack
`age. The present invention Will be seen to Well support
`capacitor arrays. With these arrays OEMs are able to avoid
`the placement issues surrounding very small chips. In
`addition, they save on-board real estate and component
`placement costs. Astandard array contains tWo to four chips.
`HoWever, use of these packages is still limited to specialiZed
`niche markets. One of the biggest draWbacks of this pack
`aging strategy is that all of the capacitors in the array have
`heretofore been required to be of same value. The present
`invention Will be seen to readily overcome this limitation.
`The fact that the Electronic Industries Association has not
`settled on a standard case siZe has also inhibited sales of
`arrayed capacitors. Heretofore the case siZe Was strongly,
`even in?exibly, linked to the capacitance value. Therefore
`standardiZation of case siZes Was, to some extent, a stan
`dardiZation of the capacitance values With Which, for a
`particular packaging technology, circuit designers could
`Work. The present invention Will be seen to sever this
`relationship, and present a greater opportunity than hereto
`fore of producing a ceramic capacitor of any desired value
`(Within limits) inside a standard case, or a reduced number
`of standard cases.
`A similar trend is occurring in the tantalum capacitor
`market. “We are seeing users of each case siZe [A, B, C, and
`D] going to the next-smallest case siZe to save real estate,
`While getting the same values,” said Willing S. King, mar
`keting manager for tantalum products at AVX. “In turn, We
`are using less material and passing that savings on to the
`customer.” There is about a 10% price difference betWeen
`case siZes, he estimated.
`Computer makers primarily use C and D case siZes, While
`telecommunications and cellular manufacturers, the tWo
`biggest markets for tantalum capacitors, prefer the A and B
`siZes. A standard A case measures about 1.6 mm, While a B
`case is 2 mm high. Despite some similarities, the ceramic
`and tantalum-capacitor businesses are, in fact, very different.
`In the ceramic marketplace, some of the primary focuses
`include advancing dielectric technologies and the advent of
`loW-inductance products. Tantalum manufacturers, on the
`other hand, are concentrating on loWering equivalent-series
`resistance (ESR) ratings and increasing C/V ratings.
`TWo popular dielectrics are the Y5V and X7R. Y5V is a
`general-purpose dielectric Without the tighter tolerances
`offered by the X7R. It offers an operating temperature range
`of (approximately) —30 degrees C to +85 degrees C, and is
`favored in cost-sensitive consumer applications. The X7R,
`Which is more temperature-stable, can handle from —55
`degrees C to +125 degrees C. HoWever, the dielectric
`coefficient K of the Y5V dielectric is approximately 15,000;
`the K of the X7R dielectric only about 4000. Accordingly,
`the advantage that a high-dielectric-constant dielectric offers
`for realiZing much higher capacitance in a single chip comes
`at the expense of temperature stability. There has therefore
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`1. Field of the Invention
`The present invention generally concerns “parallel plate”
`or “single layer” capacitors as are typically made by met
`alliZing tWo faces of a thin sheet of ceramic so as to make
`a ceramic capacitor.
`The present invention further concerns high-capacity
`ceramic capacitors having
`internal conductive planes
`connected by (ii) multiple redundant (preferably radiation
`patterned) vias to (iii) improved, alignment-insensitive and
`anti-Wicking, surface pads to Which electrical connection
`may be made.
`2. Description of the Prior Art
`2.1 State of the Art in Capacitor Technology Circa 1997, and
`Industry Impetus for Certain Improvements of All Types
`As reported by free-lance Writer Hailey Lynne McKeefry
`in the article “Capacitor Technology Marches Ahead”
`appearing in the February, 1994, issue of Electronic Buyer’s
`NeWs, capacitors Were then, and are noW, a mature compo
`nent in a mature market. Nonetheless to this maturity, U.S.
`manufacturers are striving mightily to improve both tanta
`lum and ceramic capacitors. “The fact that everything you
`buy performs better and costs less than What you bought last
`year is What keeps this industry going,” said Terry Weaver,
`president and chief operating officer at Kemet Electronics
`Corp., Greenville, SC. In this sentiment the inventors of the
`present invention concur.
`As With just about any electronic component, the motto of
`capacitor purchasers and manufacturers alike is “smaller is
`better.” Capacitor manufacturers are Working toWard cases
`With smaller footprints and loWer pro?les. For example, the
`Sprague division of Vishay Electronic Components of North
`America and Asia developed a molded surface-mount tan
`talum capacitor With a rating of 6.8 microfarads in an R-siZe
`45
`case. In September, 1997, Myrtle Beach, S.C.-based AVX
`Corp. announced a loW-pro?le V-siZe case for its tantalum
`surface-mount capacitors. The TPS-V series is designed to
`provide capacitance/voltage (C/V) ratings higher than 3,500
`and improved poWer dissipation. The V case measures less
`than 7 mm><6 mm, With a height of just 3.45 mm.
`In the marketplace for ceramic capacitors (to Which the
`present invention pertains), the 0805 case siZe remains
`popular although there is a signi?cant move to 0603s, and
`even increased interest in 0402s. “Designers are leap
`frogging the 0805 packages in favor of the 0603s in some
`designs,” said Kevin Rafferty, marketing manager for
`ceramic capacitors at Philips Electronic Components,
`Jupiter, Fla. Rafferty predicts that 0805s—With a 30% share
`of ceramic volume—Will continue to take the biggest share
`of the market, While 0603s Will claim 20% and 0402s 5%.
`The remaining 35% Will be divided among products in 1206
`and larger packages. In 1996, 0603 packages accounted for
`only 5% of the market share. “The 0805s are stable, While
`1206 packages are losing share,” he said.
`Part of What is holding the 0402s back is their diminutive
`siZe. “They are just too hard to handle,” Kemet’s Weaver
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`US 6,366,443 B1
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`3
`heretofore been a trade-off: improved dielectric performance
`With resultantly increased capacitance (for the same form
`factor) versus enhanced temperature sensitivity. The present
`invention Will again be seen to substantially obviate this
`concern, and to permit the production of ceramic capacitors
`of desirably high capacitance by use of only the dielectrics
`having loWer dielectric coef?cients.
`OEMS have commenced to replace the tantalum chips
`With the ceramic parts in some instances. “Higher capaci
`tance values and cost effectiveness make surface-mount
`ceramic capacitors an increasingly popular alternative to
`tantalum caps,” said Philips’ Rafferty. “Other advantages of
`ceramic chips include higher breakdoWn voltages, loWer
`ESR, higher insulation resistance, and better pulse response
`for frequencies greater than 100 kHZ. This means that the
`capacitance values can be 50% less than the equivalent
`tantalum caps.
`LoW inductance is also in demand for the PC market,
`particularly as faster and faster microprocessors arc
`designed into PCs. “There has been lots of interest in
`loW-inductance products since the speed of processors is
`increasing and voltages for processors are dropping to 2.2V”
`Vishay’s Gormally said. “Using higher-inductance parts can
`Wreak havoc With those circuits.” Vitramon has recently
`introduced a ceramic chip capacitor in the 0612 format With
`only one-third the inductance (0.3 nanohenry) of its standard
`counterpart.
`Lowered Equivalent Series Resistance, or ESR, is also
`desired. Tantalum capacitors in a C-case siZe are available in
`the range from 4 V to 50 V With a maXimum ESR at 25° C.
`of 250 milliohms to 1,600 milliohms. HoWever, OEMs
`continue to push for even loWer values. State of the art is
`around 80 milliohms to 100 milliohms. The present inven
`tion Will be seen to support very loW resistance electrical
`connection to the plates of a ceramic capacitor, thus deliv
`ering a desirably loW ESR.
`2.2 State of the Art in Ceramic Capacitor Technology Circa
`1997
`As demand for smaller, thinner, and lighter portable
`equipment, liquid crystal modules, and poWer supply mod
`ules groWs, smaller and thinner ceramic capacitors are in
`greater demand. Since neWer equipments tend to require
`(and provide) both higher performance and longer service
`life, the demand for ceramic capacitors, as opposed to
`tantalum or aluminum electrolytic capacitors, is greatly
`increasing.
`To meet the demand, the industry is Working, circa 1997,
`on increasing the capacitance, reducing the siZe, and
`improving the dielectric strength of ceramic capacitors. To
`manufacture a capacitor With a ceramic capacitance of 100
`micro F, high technology is required to create a thin-layer
`dielectric substance of 5x10‘6 meters or less, and to, in the
`case of multiple electrode ceramic capacitors, form capaci
`tors of 300 or more buried layers. To do so progress has been
`made in ?ne-graining ceramic material, particularly com
`posite perovskite type ceramic, so that it can be thin-layered.
`Recently achieved increases in capacitance have resulted
`in, for example, the commercialiZation by Murata Manufac
`turing Co., Ltd. (Japan) of its GRM 200 line of ceramic
`capacitors having up to 22 microfarads capacitance, With
`contemplated development of ceramic capacitors of up to
`100 microfarads capacitance.
`Applications of these improved, larger capacitance,
`ceramic capacitors include poWer supply modules, liquid
`crystal modules, and various portable equipments.
`The neW Murata Manufacturing Co., Ltd. GRM 200
`series of large-capacitance monolithic chip ceramic capaci
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`tors include: capacitance 10 microfarads/10V of siZe: 3.2x
`25x15 mm; capacitance 22 microfarads/10V of siZe: 3.2x
`25x20 mm; and capacitance 10 microfarads/25V.
`When small siZe is emphasiZed the siZes may be as small
`as 2.0><1.25><1.25 mm for the capacitance of 10 microfarads.
`When increased capacitance is emphasiZed 47 microfarads
`may be realiZed in a 3.2><2.5><1.5 mm siZe, 100 microfarad
`in a 4.5><3.2><2.5 mm siZe. Production of these neW capaci
`tors has reportedly been achieved by use of a thin-layer/
`multi-layer forming technology using improved materials.
`Currently, demand for even smaller liquid crystal
`modules, poWer supply modules, and portable equipment is
`greatly increasing. Demand for these neW capacitors is
`eXpected to eXpand With the need to doWnsiZe this type of
`equipment. Currently, the neW capacitors are used mainly
`for smoothing in the DC-DC converters of portable
`equipments, noise-?ltering in liquid crystal bias circuits, and
`smoothing/de-coupling in IC poWer supply lines of various
`equipments. The capacitors are being produced at levels
`from 20 to 50 million units per month as of 1996/97.
`2.3 General Construction and Theory of Single-layer
`Parallel-plate Ceramic Capacitors
`Existing “parallel plate” or “single layer chip” capaci
`tors are built With tWo parallel conductive plates separated
`by a single, insulating dielectric, layer that is typically made
`of ceramic. These single-layer parallel-plate ceramic capaci
`tors have a very useful form factor Which renders them
`suitable for automated assembly into microWave frequency
`circuits and similar applications. The normal form factor is
`a rectilinear parallelepiped body. Dimensions of the chip
`capacitors can be matched to the Width of the strip lines upon
`Which the capacitors are mounted and to Which the capaci
`tors electrically connect.
`In assembly the bottom face of the chip capacitor is
`typically soldered or conductive epoXy attached to a con
`ductive surface, or pad. The top face is typically ribbon, or
`Wire, bonded to another connection point.
`Most current chip capacitors are made by metalliZing tWo
`faces of a thin sheet of sintered ceramic typically having a
`thickness in the range of 4 mils (inches) to 10 mils (inches).
`The metalliZed sheet is then cut into small rectangular
`bodies by saWing or by abrasive cutting techniques. The
`siZes of the cut bodies range from, typically, 10 mils (inches)
`square to 50 mils (inches) square, although some applica
`tions use rectangular forms.
`While the form factor of these advices is desirable, the
`amount of capacitance that can be achieved and quality
`factor of the devices has frequently limited their usefulness.
`The simpli?ed equation for the capacitance of tWo parallel
`plates is C=kA/d; Where C is capacitance in farads, k is the
`dielectric constant of the insulating material betWeen the
`plates, A is the area of each of the opposed plates in square
`meters, and d is the distance betWeen the plates. Solution of
`this equation shoWs that a 20 mil square part (A) having a
`5 mils thickness (d) in material having a relative dielectric
`constant of 100 gives a capacitance of 8 picofarads.
`2.4 Adhesive Mounting of Single-layer Parallel-plate
`Ceramic Capacitors
`Conductive adhesive, and particularly conductive epoXy
`adhesive, may be used to strongly permanently bond single
`layer parallel-plate ceramic capacitors to a substrate. The
`capacitors are simultaneously
`adhesively attached, and
`(ii) electrically connected, to a substrate circuit by ?rst being
`placed in a puddle of liquid conductive epoXy, Which epoXy
`is then cured. It is intended that the conductive epoXy
`contact only the underside conductive surface of the capaci
`tor; electrical connection to the topside conductive surface
`being made by ribbon, or Wire, bonding.
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`000009
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`5
`Sometimes, however, the liquid epoxy Will Wick up the
`sides of the capacitor, especially if these sides are
`other
`than exactly perpendicular to the substrate, and/or (ii) too
`much epoxy is used. The conductive epoxy Wicked up the
`sides of a single-layer parallel-plate ceramic capacitors may
`?oW over onto, and electrically contact, the conductive
`topside surface of the capacitor, resulting in reduced resis
`tance or even a total shorting of the capacitor.
`Some manufacturers have previously gone to extraordi
`nary lengths to angle the edges of their capacitors in order
`to avoid this problem. Generally, hoWever, features that
`extend the body of the capacitor, and that thereby serve to
`isolate one or both of the conductive areas (plates) of its
`underside and topside surfaces, only serve to reduce the area
`of the plates for a given physical siZe, and thus adversely
`reduce the capacitance of a capacitor of any given siZe.
`2.5 Creation of Vias in Ceramic Capacitors and Other
`Ceramic Electrical Components
`The present invention Will be seen to concern improve
`ments in the creation of vias, or through holes—though
`Which vias electrical connection can be made by the depo
`sition of metal—in the ceramic electrical components hav
`ing ceramic-covered or ceramic-encapsulated electrically
`connectable parts. The improvements are applicable to
`ceramic capacitors containing electrically conductive plates,
`but are not limited to ceramic capacitors, being also useful
`in fabrication of pieZoelectric sensors and actuators, for
`example.
`The conventional means of making vias is discussed in
`US. Pat. No. 4,864,465 for a VIAD CHIP CAPACITOR
`AND METHOD FOR MAKING SAME to William L.
`Robbins. The Robbins patent concerns a tWo pole viad chip
`capacitor activatable from either of its sides. The capacitor
`has
`a plurality of ceramic layers in a stack, each and every
`layer having only tWo vias, a ?rst via in a ?rst region of each
`layer and a second via in a second region of each layer; (ii)
`a ?rst conductor in each of the ?rst vias; (iii) a second
`conductor in each of the second vias; (iv) a stack of ?rst
`capacitor plates being on ?rst alternate ceramic layers and
`each ?rst plate being in electrical contact With a ?rst
`conductor; (v) and a stack of second capacitor plates, the
`second plates being on second alternate ceramic layers that
`are interdigitated With the ?rst alternate ceramic layers and
`in electrical contact With a second conductor.
`The Robbins capacitor is a conventional-type ceramic
`chip capacitor solderable at both ends for use on printed
`circuit boards. The ceramic conventional volume and exter
`nal form of the ceramic chip capacitor of the present
`invention Will be seen, hoWever, to be of a different nature.
`Namely, the (nominal) “top” and “bottom” of the capacitor
`have extensive conductive planes, or pads. This permits the
`neW capacitor of the present invention to be machine located
`and soldered (typically) immediately adjacent integrated
`circuits in small packages—substantially unlike the Robbins
`capacitor.
`The vias of the Robbins capacitor, and of other ceramic
`capacitors, may be mechanically punched in the green
`ceramic sheets, or may be punched through the ceramic
`sheets by hydraulic jets, before sintering of the multi-layer
`ceramic capacitor. The punching technique, in particular,
`continues to Work Well for the creation of vias in the ceramic
`capacitors of the present invention and is, indeed, used at a
`much higher density than heretofore in order to create a
`greatly increased number of vias per unit area, and overall,
`than heretofore.
`HoWever, fabrication of the improved capacitors of the
`present invention Will also be seen to usefully employ a
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`method of creating vias, or through-holes, in the ceramic of
`electrical components having ceramic-covered or ceramic
`encapsulated electrically-connectable parts by use of one or
`more photosensitive ceramic binders. A number of issued
`United States patents concern ceramic compositions having
`photosensitive binders, an exemplary ?ve of Which patents
`are assigned to E. I. Du Pont de Nemours and Company
`(Wilmington, Del.).
`US. Pat. No. 4,613,560 to Dueber, et. al. for a PHOTO
`SENSITIVE CERAMIC COATING COMPOSITION
`assigned to E. I. Du Pont de Nemours and Company
`(Wilmington, DE) concerns a photosensitive ceramic coat
`ing composition Which is ?red in a substantially non
`oxidiZing atmosphere comprising an admixture of: (a) ?nely
`divided particles of ceramic solids having a particularly
`de?ned surface area-to-Weight ratio and particle siZe, and (b)
`?nely divided particles of an inorganic binder having a
`particularly de?ned surface area-to-Weight ratio and particle
`siZe, dispersed in an organic medium comprising (c) an
`organic polymeric binder and (d) a photoinitiation system,
`dissolved in (e) photohardenable monomer and
`an vola
`tile organic solvent.
`US. Pat. No. 4,912,019 to Nebe, et al. for a PHOTO
`SENSITIVE AQUEOUS DEVELOPABLE CERAMIC
`COATING COMPOSITION assigned to E. I. Du Pont de
`Nemours and Company (Wilmington, Del.) concerns a pho
`tosensitive ceramic coating composition Which is ?red in a
`substantially non-oxidiZing atmosphere comprising an
`admixture of: (a) ?nely divided particles of ceramic solids
`having a surface area-to-Weight ratio of no more than 10
`m2/g and at least 80 Weight percent of the particles having
`a siZe of 1—10 pm, and (b) ?nely divided particles of an
`inorganic binder having a glass transition temperature in the
`range from of 550° to 825° C., a surface area-to-Weight ratio
`of no more than 10 m2/g and at least 90 Weight percent of
`the particles having a siZe of 1—10pm, the Weight ratio of (b)
`to (a) being in a range from 0.6 to 2, dispersed in an organic
`medium comprising (c) an organic polymeric binder, and (d)
`a photoinitiation system, dissolved in (e) photohardenable
`monomer, and
`an organic medium. An improvement to
`this composition comprises an organic polymeric binder
`containing a copolymer or interpolymer of a C1—C1O alkyl
`acrylate, C1—C1O methacrylate, styrene, substituted styrene
`or combinations thereof and an ethylenically unsaturated
`carboxylic acid, Wherein a moiety in the binder derived from
`the unsaturated carboxylic acid comprises at least 15 Weight
`percent of the polymer and Wherein the binder has a molecu
`lar Weight not greater than 50,000 and Wherein the compo
`sition upon imageWise exposure to actinic radiation is devel
`opable in an aqueous solution containing 1 percent by
`Weight sodium carbonate.
`Similarly, US. Pat. No. 4,959,295 is for a PROCESS OF
`MAKING A PHOTOSENSITIVE SEMI-AQUEOUS
`DEVELOPABLE CERAMIC COATING COMPOSITION;
`US. Pat. No. 4,925,771 is for a PROCESS OF MAKING
`PHOTOSENSITIVE AQUEOUS DEVELOPABLE
`CERAMIC COATING COMPOSITION INCLUDING
`FREEZE DRYING THE CERAMIC SOLID PARTICLES;
`and US. Pat. No. 4,908,296 is for a PHOTOSENSITIVE
`SEMI-AQUEOUS DEVELOPABLE CERAMIC COAT
`ING COMPOSITION.
`
`SUMMARY OF THE INVENTION
`The present invention contemplates a ceramic capacitor of
`conventional volume and external form—meaning a paral
`lelepiped body having exterior pads to Which electrical
`connection is made—that is enhanced in its capacitance by
`
`000010
`
`
`
`US 6,366,443 B1
`
`7
`dint of including at least one interior metalliZation plane, and
`preferably one or more pairs of interior metalliZation planes,
`that arc parallel to capacitor surfaces Where exist pads and/or
`traces. Electrical connection betWeen these interior metalli
`Zation planes and the surface pads and/or traces (Which pads
`and traces need not be, and Which commonly are not,
`coextensive With the planes) is made though
`abundant (ii)
`redundant vias.
`In accordance With the physical laW that capacitance
`betWeen tWo conducting planes is inversely proportional to
`the distance of 10 separation, the capacitance betWeen these
`interior metalliZation planes—Which capacitance is seen at
`the exterior of the capacitor When these internal planes are
`electrically connected to the exterior pads—is greater than
`that capacitance Which Would alternatively be seen betWeen
`opposed exterior pads (Which have heretofore served as the
`electrodes) should no electrically-connected interior metal
`liZation plane(s) be present.
`The present invention further contemplates that each
`interior metalliZation plane Within a ceramic capacitor so
`constructed should be redundantly, and preferably massively
`redundantly, electrically connected to associated exterior
`pads by plural, and more preferably by multiple, vias. By
`this construction the enhanced-capacitance ceramic capaci
`tor may be reliably conventionally fabricated in huge arrays
`(typically many thousands of capacitors) on Workpiece
`“bars” regardless that any single one via, and some feW vias,
`may not be properly located. Additionally, the redundant
`vias make a loW-resistance electrical connection useful at
`high frequencies.
`Moreover, the many vias are preferably located in a dense
`uniform pattern; normally a regular pin grid array. Because
`both
`the interior metalliZation planes internal to the
`capacitor, and the (ii) exterior metalliZations in the forms of
`traces and pads, do not commonly occupy all the area of the
`capacitor, this makes that many vias “lead to noWhere”,
`connecting to metalliZation at only one end (a “missed via”)
`or at neither end (an “empty via”). These “missed” and/or
`“empty” vias are intentional: they permit fabrication of
`diverse capacitors
`by uniform processes in Which (ii)
`alignment is not critical. In the course of capacitor
`fabrication, those vias that actually connect to metalliZation
`(Which is typically more than 50%, but less than 100% of all
`vias) ?ll With metal. Those vias that do not serve to connect
`to metalliZation areas tend to close off, and heal, during
`annealing of the capacitor ceramic. The small regions Where
`these “vestigial” “empty” vias are present do not signi?
`cantly affect capacitor performance.
`The present invention still further contemplates a ceramic
`capacitor having amply numerous, and amply-large exterior
`pads so as to easily readily support positionally-tolerant
`electrical connection. In particular, the exterior pads, of
`Which there may commonly be but tWo located on opposed
`sides of the ceramic capacitor, are much, much larger than
`are the egress areas of (preferably multiple) vias that connect
`to interior metalliZation planes that are Within the capacitor.
`The exterior pads are, indeed, so large as to span betWeen
`multiple vias. Equivalently, it may be said that multiple vias
`connect each interior metalliZation plane to an associated
`external surface pad, and that the vias are thus “redundant”.
`The present invention still further contemplates that all
`the collective large-area exterior pads (or pad) on at least
`one, and preferably both, surfaces of the capacitor should be
`WithdraWn from the edges of the capacitor. It is thereby
`bene?cially promoted that (insulating) epoxy adhesive Will
`not Wick onto the conductive pads of the capacitor, poten
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`8
`tially interfering With electrical connection to these pads,
`during adhesive surface mounting of the capacitor.
`Still other niceties are present in the improved capacitors,
`particularly including
`parallelepiped ceramic bodies that
`are (by dint of the close interior metalliZation planes) of
`suf?cient siZe and thickness so as to substantially avoid
`fracture during routine handling (regardless that the capaci
`tance is much higher than even that Which Would normally
`be realiZed from a ceramic capacitor so excessively thin so
`as to typically be undesirably fragile), and (ii) rounded
`edges.
`Finally, the present invention contemplates improved
`methods of realiZing the abundant multiple vias; namely, the
`vias are either
`stamped as a grid array in the green
`ceramic sheets (from Which the ceramic capacitor is made),
`or else (ii) patterned With radiation, normally ultraviolet
`light, in a ceramic dielectric tape having a photosensitive
`binder. In the case of method (ii), unexposed areas of the
`tape are cost effectively Washed out With solvent, instead of
`being punched out, before sintering of the ceramic so as to
`easily and accurately create multitudinous holes.
`HoWsoever abundantly perforated, the perforated ceramic
`tape is used to make Wafers of arrayed ceramic capacitors
`the future vias are accurately precisely positionally located.
`Notably the ample, and amply-large pads, that are, as
`previously explained, positionally-tolerant of later external
`electrical connection are to some extent made possible by
`the precise location of the many vias. Namely, the vias
`typically serve to de?ne the boundaries of the pads, and the
`precise location of these vias permits the pads, even as they
`are preferably WithdraWn from the edges of the capacitor, to
`advantageously occupy all available surface area, and to
`partition this area optimally.
`Quite simply, the interior structures and geomet
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