DEC 0 9 UIOl
`U.S. UTILITY Patent Application
`
`FILING DATE CLASS I SUBCLASS GAU
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`t:XAMINER
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`De\ne ,.;ian; Devoe Lami::ert; Trinh Hung;
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`0 TERMINAL
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`DISC LAMER
`
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`
`FILED WITH:
`
`WARNING: The infonnation disclosed herein may be restricted.
`Unauthorized disclosure may be prohibited by the United States Code Title 35,
`368, Possession outside the U.S. Patent & Trademark
`and contractors
`
`0 DlSK (CRF}
`
`D CD-ROM
`
`(Attached In pocket on right Inside flap)
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`AVX CORPORATION 1002
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`

`
`I
`ORIGIJQAL
`CLASS
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`
`I ISSUE SLIP STAPLE AREA (for additional cross-references)
`ISSUING CLASSIFICATION
`CROSS REFERENCE(S)
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`SUBCLASS CONE SUBCLASS PER BLOC~
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`A Continued on Issue Slip Inside File Jacket
`INDEX OF CLAIMS
`- (Through numeral) ... Canceled
`N ............... Non-elected A ............... Appea~
`......... ... Resbicted
`...............
`···············
`I
`ere nee
`lnter1
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`Date
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`if 0
`51
`101
`52
`102
`103
`53
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`54
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`56
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`57
`108
`58
`109
`59
`110
`60
`111
`61.
`62
`112
`113
`63
`114
`'64
`115
`65
`116
`66
`67
`117
`118
`68
`119
`69
`70
`120
`121
`71
`72
`122
`123
`73
`124
`74
`75
`125
`126
`76
`77
`127
`78
`128
`129
`79
`130
`80
`81
`131
`132
`82
`133
`83
`134
`84
`135
`85
`136
`86
`137
`87
`138
`88
`139
`89
`140
`90
`141
`91
`142
`92
`143
`93
`144
`94
`145
`95
`146
`96
`147
`97
`148
`98
`149
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`100
`150,
`If more than 150 cla1ms or 9 actions staple add1t1onal sheet here
`
`
`000003
`
`

`
`SEARCH NOTES
`(List databases searched. Attach
`search strategy ·inside.)
`Date Exmr.-
`
`SEARCH
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`INTERFERENCE SEARCHED V'
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`
`

`
`PATENT APPLICATION SERIAL NO . - - - - - - - -
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`'11/2002 EHAll£1 00000042 10188696
`FC:201
`370.00 OP
`FC:202
`168.000P
`FC:203
`15J.OOOP
`
`PT0-1556
`(5/87)
`
`\ ·u.s. Government Printing Office: 2001- 481·697/59173
`
`
`000005
`
`

`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicant: Alan Devoe, Lambert Devoe, Hung Trinh
`
`Title:
`
`SINGLE LAYER CAPACITOR
`
`Atty. Docket: DEVOE I 09 ;;;;;;;;;!ili
`0
`,.,....,
`i-t ~
`p.'I.D :~
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`Vlco 't!!!!!f!i(cid:173)
`--------------------------------------------------------------------------~~~~· ~~
`-----------------------------------~----------------------------------~~---ssrr~
`c:::»-o
`cn-'e~
`CERTIFICATE OF MAILING BY EXPRESS MAIL- 37 CFR 1.10
`.,..,
`
`r
`
`'Express Mail' mailing label number: EV026539438US
`Date of Deposit: July 2, 2002
`
`::;...--'
`
`I certify that this paper or fee (along with the enclosures noted herein) is being deposited with the United States Postal Service
`'Express Mail Post Office to Addressee' service under 37 CFR 1.10 on the above date and is addressed to the Assistant Commissioner
`for Patents, Washington, D.C. 20231. ~ ~~
`'~5
`By: Dale Mitchell (person mailing paper)
`
`UTILITY PATENT APPLICATION TRANSMITTAL
`BOX PATENT APPLICATION
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`This is a request for filing, under 37 CFR § 1.53(b), a(n):
`
`181 Original (non-provisional) application.
`0 Divisional of prior application Serial No._, filed on_.
`0 Continuation of prior application Serial No. _, filed on _.
`0 Continuation-in-part of prior application Serial No. _, filed on _.
`
`PRELIMINARY AMENDMENT/CALCULATION OF FEES
`
`0 Please cancel claims_ without prejudice, and prior to calculating the fees. _total claim(s), of
`which _
`is( are) independent, is( are) pending after the amendment.
`
`0 Please enter the enclosed preliminary amendment identified below prior to calculating the fees. _
`total claim(s), of which_ is( are) independent, is( are) pending after the amendment.
`
`181 Small Entity Status is Requested
`
`181 The Fees are Calculated as Follows:
`I Fee:
`I Number of Claims:
`
`I
`
`Total Claims
`
`37
`
`Independent Claims
`
`7
`
`I MULTIPLE DEPENDENT ClAIM FEE
`I TOTAL OF ABOVE CALCULATIONS
`I REDUCTION BY 50% FOR FILING BY SMALL ENTITY
`
`BASIC FEE
`
`!TOTAL
`
`In Excess of:
`
`I
`
`20
`
`3
`
`Extra:
`
`17
`
`4
`
`I At Rate:
`
`II Amount:
`
`I
`
`$18
`
`$84
`
`$306.00
`
`$336.00
`
`I~
`
`II
`II
`II
`
`$1,382.00 1
`$691.00 1
`
`$69I.oo 1
`
`DEVOE/09
`Express Mail No. EV026539438US
`Page 1 of3
`
`
`000006
`
`

`
`ENCLOSURES
`181 Utility Patent Application Transmittal Form (in duplicate) containing Certificate of Mailing By
`Express Mail Under 37 CFR 1.10.
`181 Return Postcard.
`
`APPLICATION PAPERS
`
`181 Utility Patent Application, with: cover sheet, _JL page(s) specification (including _JJ_ total
`claim(s), of which ...1.__ is(are) independent), and _1_ page(s) abstract.
`181 Drawings:~ sheet(s) of formal drawings (_1Q_ total figure(s)).
`D Microfiche Computer Program (Appendix).
`D Nucleotide and/or Amino Acid Sequence, including (all are necessary): Computer Readable Copy,
`Paper Copy (identical to computer copy), and Statement verifying identity of copies.
`181 An Executed Declaration, Power of Attorney and Petition Form.
`D Copy of Executed Declaration, Power of Attorney and Petition Form from prior application
`identified above.
`D Certified Copy of priority document(s) identified as attached above.
`
`ADDITIONAL PAPERS
`
`181 Assignment to Presidio Components, Inc. of 7169 Construction Court, San Diego, CA 92121 ,
`Recordation Cover Sheet (Form PT0-1595)
`181 Nonpublication Request under 35 U.S.C. 122(b)(2)(B)(i)
`D Preliminary Amendment (to be entered prior to calculation of fees)
`Information Disclosure Statement,_ sheet(s) Form PT0-1449, _U.S. Patent Reference(s), _
`D
`Foreign Patent Reference(s) and_ Other Reference(s)
`D Other:
`
`CHECKS
`
`181 A Check of $691.00 for the filing fee.
`181 A Check of $40.00 for the assignment recording fee.
`
`DEVOE/09
`Express Mail No. EV026539438US
`Page 2 of3
`
`
`000007
`
`

`
`DEPOSIT ACCOUNT AUTHORIZATION
`
`0 Please charge Deposit Account No. 23-3000 in the amount of_.
`181 The Commissioner is authorized to charge any fees under 37 CFR 1.16 and 1.17 which may be
`required during the entire pendency of the application, or credit any overpayment, to Deposit
`Account No. 23-3000 . A duplicate of this transmittal is attached.
`o THE PAYMENT OF FEES IS BEING DEFERRED.
`
`Respectfully Submitted,
`
`WOOD, HERRON & EVANS, L.L.P.
`2700 Carew Tower
`441 Vine St.
`Cincinnati, Ohio 45202
`(513) 241-2324
`
`KLD/dcg
`
`DEVOE/09
`Express Mail No. EV026539438US
`Page 3 of3
`
`
`000008
`
`

`
`PTO/SB/35 (11-00)
`Approved for use through 10/31/2002. OMB 0651-0031
`U.S. Patent and Trademark Office; U. S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of Information unless it displays a valid OMB control number.
`
`NONPUBLICATION REQUEST
`UNDER
`35 U.S.C. 122(b)(2)(B)(i)
`
`First Named Inventor I Alan Devoe
`j SINGLE LAYER CAPACITOR
`Atty Docket Number I DEVOE-09
`
`Title
`
`'
`
`I hereby certify that the invention disclosed in the attached application has not and will not
`be the subject of an application filed in another country, or under a multilateral agreement,
`that requires publication at eighteen months after filing.
`
`I hereby request that the attached application not be published under 35 U.S.C.
`122(b).
`
`~~----
`
`Signature
`
`Alan Devoe, President
`
`Typed or printed name
`
`This request must be signed in compliance with 37 CFR 1.33(b) and submitted with the
`application upon filing.
`
`Applicant may rescind this nonpublication request at any time. If applicant rescinds a
`request that an application not be published under 35 U.S.C. 122(b), the application will be
`scheduled for publication at eighteen months from the earliest claimed filing date for which a
`benefit is claimed.
`
`If applicant subsequently files an application directed to the invention disclosed in the
`attached application in another country, or under a multilateral international agreement, that
`requires publication of applications eighteen months after filing, the applicant must notify the
`United States Patent and Trademark Office of such filing within forty-five (45) days after the
`date of the filing of such foreign or international application. Failure to do so will result in
`abandonment of this application {35 U.S.C. 122{b){2){B){iii)).
`
`Burden Hour Statement: This collection of information is required by 37 CFR 1.213(a). The information Is used by the public to request that an application not be
`published under 35 U.S.C. 122(b) (and the PTO to process that request). Confidentiality Is governed by 35 U.S.C. 122 and 37 CFR 1.14. This form is estimated
`to take 6 minutes to complete. This time will vary depending upon the needs of the Individual case. Any comments on the amount of lime you are required to
`complete this form should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, Washington, DC 20231. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Assistant Commissioner for Patents, Washington, DC 20231.
`
`
`000009
`
`

`
`EXPRESS MAIL NO.: EV026539438US
`
`APPLICATION FOR UNITED STATES PATENT
`
`Applicant: Alan Devoe; Lambert Devoe; Hung Trinh
`
`Title:
`
`SINGLE LAYER CAPACITOR
`
`Assignee:
`
`Presidio Components, Inc.
`
`Kristi L. Davidson, Esq.
`Wood, Herron & Evans, L.L.P.
`2700 Carew Tower
`441 Vine Street
`Cincinnati, Ohio 45202
`(513) 241-2324 (voice)
`(513) 421-7269 (facsimile)
`Ref. No.: DEVOE-09
`
`SPECIFICATION
`
`
`000010
`
`

`
`-1-
`
`SINGLE LAYER CAPACITOR
`
`Field of the Invention
`
`This invention relates to single layer capacitors, and in particular, surface
`
`mountable single layer capacitors and a method of making the capacitors.
`
`Back2round of the Invention
`
`5
`
`The "parallel plate" or "single layer" ceramic capacitor has a very useful
`
`form factor for assembly into microwave frequency and similar electrical circuits.
`
`These circuits may be laid out on printed circuit (pc) boards, or be present on integrated
`
`circuits (ICs) within chip carriers and other packages where space is typically even more
`
`precious. The dimensions of the ceramic capacitor can be matched to the width of a
`
`10
`
`strip line on the pc board or the chip carrier holding an IC.
`
`In assembly, the bottom face ofthe ceramic chip capacitor is typically
`
`soldered to or conductive epoxy attached to the surface of the pc board substrate. The
`
`top face ofthe ceramic capacitor normally presents one or more electrically conductive
`
`pads that are typically ribbon- or wire-bonded to another circuit connection point.
`
`
`000011
`
`

`
`Most ceramic chip capacitors currently offered are made by metallizing
`
`two faces of a thin sheet of sintered ceramic that is typically in the range of 4 mils to 10
`
`mils thick. The metallized ceramic sheet is then cut to size by sawing or abrasive
`
`cutting techniques. Typical sizes of the chip capacitors range from 10 mils square to 50
`
`5
`
`mils (inches) square, although some applications use rectangular forms.
`
`While the form factor of these simple devices- used in quantities of
`
`hundreds of millions per year- is highly desirable, the amount of capacitance that can
`
`be achieved and quality of the devices realizing maximum capacitance is starting to
`
`limit their usefulness in certain applications. The simplified equation fot the
`
`10
`
`capacitance of a parallel plate capacitor, c = KA/d where K is the dielectric constant, A
`
`the area of each of opposed plates, and d the distance of separation between plates,
`
`shows that a 20 mils square part (A) of 5 mils thickness (d) made from ceramic with a
`
`relative dielectric constant of 100 yields a capacitance of 8 picofarads.
`
`This five mils thickness- necessitated in order to establish some
`
`15
`
`structural strength for the given area size of, for example, 20 mils x 20 mils- means
`
`that the capacitor does not have much structural strength, and is subject to undesirable
`
`fracturing or chipping during routine handling and assembly into circuits. Thus, the
`
`physical resistance to damage of the highest-capacitance "parallel plate" or "single
`
`layer" ceramic capacitors is innately poor. The design of single layer capacitors in
`
`20
`
`general is a compromise between the use of thicker ceramic layers for greater strength
`
`and thinner ceramic layers for greater capacitance.
`
`In addition to the difficulties in achieving high capacitance while
`
`maintaining structural strength, due to the small size of the capacitors, they are difficult
`
`to attach automatically to a pc board. One approach has been to use a flat, horizontal
`
`25
`
`capacitor with the metallization on its lower side having a gap. A device of this type is
`
`-2-
`
`
`000012
`
`

`
`referred to as the GAP-CAP™ manufactured by Dielectric Laboratories, Inc. A GAP(cid:173)
`
`CAP™ device is shown in FIG. 1, mounted onto a pc board 10 in which metal traces 11
`
`and 12 constitute a transmission line. The flat capacitor 13 is horizontally disposed to
`
`bridge the gap between the traces 11, 12. The capacitor 13 has a dielectric chip or slice
`
`5
`
`14 that is elongated in the horizontal direction, with a metallized upper surface 15 and
`
`metallized lower surface portions 16a and 16b, which are electrically joined to the traces
`
`11 and 12, respectively. However, these devices can create unwanted resonances at
`
`frequencies above a few gigahertz. In addition, these capacitors are quite small,
`
`typically about 20-25 mils. At these sizes, the capacitors are difficult to handle, and
`
`1 0
`
`must be installed using a microscope. The capacitor 13 has a definite top and bottom,
`
`and it is crucial to install them in the proper orientation, to avoid shorting the circuit.
`
`Thus, mounting of the capacitor is difficult and expensive. Also, the additional
`
`requirement of attaching metal leads may further contribute to prohibitive
`
`manufacturing costs.
`
`15
`
`Another approach has been to use a standing dielectric chip with opposed
`
`. metallized surfaces, and with metal leads attached to the respective surfaces. A prior art
`
`standing leaded capacitor 18 is shown in FIG. 2 installed on the traces 11, 12 ofthe pc
`
`board 10. The capacitor is formed of a vertically-oriented ceramic chip 19 with
`
`metallized front and back surfaces 20, 21. There are flat metal leads 22, 23 affixed onto
`
`20
`
`the metallized surfaces 20, 21 and these are soldered onto the metal traces 11, 12,
`
`respectively. The capacitor 18 has to be held in place while the leads 22, 23 are
`
`soldered to their respective places. The leads 22, 23 are fragile, and require extreme
`
`care in fabrication, shipping, handling and soldering in place to the traces 11, 12. Thus,
`
`the capacitors 18 have to be installed manually under a microscope, and robotized or
`
`25
`
`automated circuit fabrication is difficult or impossible to obtain. In addition, the
`
`-3-
`
`
`000013
`
`

`
`standing leaded capacitor 18 produces significant signal resonances, especially for
`
`frequencies above a few gigahertz.
`
`It is desirable to provide a single layer capacitor that is surface
`
`mountable, thereby eliminating the requirement for wire bonding, which may be
`
`5
`
`prohibitively expensive, and/or that can utilize a thin dielectric layer without sacrificing
`
`structural strength. A surface mountable capacitor is described in U.S. Patent No.
`
`6,208,501, wherein metal or metal-coated ceramic end blocks are soldered to a
`
`vertically-oriented dielectric chip sandwiched there between, whereby the end blocks
`
`serve as leads for attaching to metallic surface traces on the pc board. While the
`
`10
`
`standing axial-leaded surface mount capacitor described in that patent is an
`
`improvement over the prior devices, the end blocks, which are described as 20-25 mils
`
`square blocks, must be manually assembled with the dielectric chip, which is a slow,
`
`intricate and expensive process subject to inaccurate alignment of the various
`
`components and to joint disattachment between the components during shipping and
`
`15
`
`handling. For example, the block and/or metallization may pull away from the
`
`. dielectric layer, causing the capacitor to open during use whereupon the capacitance will
`
`drop dramatically. In addition, the device described in that patent has a 20-25 mil width
`
`to match the width of a typical printed circuit trace. More specifically, the device is
`
`manufactured, for example, with a 50x20x20 mil size. However, at 40 gigahertz, the
`
`20
`
`required trace width on the pc board is 10 mils wide. So at 40 gigahertz, the optimal
`
`chip size is 20x10x10 mil. The smaller the chip size, the more difficult and expensive it
`
`will be to mechanically assemble the end blocks to the dielectric chip. Moreover, in
`
`practice, only a limited range of capacitance values may be produced, thereby limiting
`
`the flexibility of the product to meet consumer demands.
`
`-4-
`
`
`000014
`
`

`
`There is thus a need to provide a surface mountable single layer ceramic
`
`capacitor that may be easily assembled and inexpensively manufactured, and that has
`
`high capacitance and good structural strength.
`
`Summary of the Invention
`
`5
`
`The present invention provides a monolithic or essentially monolithic
`
`single layer capacitor with good structural strength that may be easily and inexpensively
`
`manufactured, and which may utilize thin dielectric layers to provide high capacitance.
`
`To this end, sheets of green-state ceramic dielectric material and ceramic/metal
`
`composite material are laminated together, diced into individual chips, and fired to
`
`10
`
`sinter the ceramic together. The composite material may comprise an amount of metal
`
`sufficient to render the composite conductive whereby the composite may be used for
`
`one or both electrodes and for mounting the capacitor to the pc board. Alternatively, the
`
`composite material may comprise an amount of metal insufficient to render the
`
`composite conductive but sufficient to act as seed points for an electroplating process
`
`15
`
`wherein the composite is preferentially coated with conductive metal, and the coated
`
`composite is mounted to the pc board and the coating provides an electrical connection
`
`to an internal electrode. By the present invention, a capacitor is provided having a
`
`vertically-oriented dielectric between composite end blocks to provide a surface
`
`mountable capacitor which is monolithic or essentially monolithic. By the present
`
`20
`
`invention a hybrid capacitor is also provided having a horizontally-oriented dielectric on
`
`a composite block mountable to the pc board and either a second composite block or a
`
`metallization on the dielectric for wire bonding to the pc board. By virtue of at least one
`
`composite block mountable to the pc board, a thin dielectric may be used while
`
`maintaining high structural integrity for the capacitor. Moreover, by assembling the
`
`25
`
`portions of the capacitor in the green-state, and co-firing the assembly, a monolithic or
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`-5-
`/ .,
`~'
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`000015
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`

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`essentially monolithic structure is formed having no preformed parts and containing no
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`epoxy, glue, solder, or attachment means within the capacitor body thus further
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`providing high structural integrity for the capacitor and simplifying the manufacturing
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`process while allowing for further miniaturization of capacitors. The green-state
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`5
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`method further provides flexibility that allows for a broad range of capacitor values to
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`be obtained as desired by the consumer.
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`Brief Description of the Drawin2s
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`The accompanying drawings, which are incorporated in and constitute a
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`part of this specification, illustrate embodiments of the invention and, together with a
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`10
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`general description ofthe invention given above, and the detailed description given
`
`below, serve to explain the invention.
`
`FIG. lis a cross-sectional view of a prior art flat capacitor.
`
`FIG. 2 is a cross-sectional view of a prior art standing leaded capacitor.
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`FIG. 3A is a cross-sectional view of one embodiment of a surface
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`15
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`mounted standing capacitor of the present invention having non-conductive composite
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`end blocks plated with conductive metal.
`
`FIG. 3B is a perspective view of the capacitor of FIG. 3A.
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`FIG. 4A is a cross-sectional view of another embodiment of a surface
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`mounted standing capacitor of the present invention having conductive composite end
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`20
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`blocks.
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`FIG. 4B is a perspective view of the capacitor of FIG. 4A.
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`FIG. 5 is a graph illustrating the effect of composition on the
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`conductivity of the composite end blocks that form a portion of the capacitors ofthe
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`present invention.
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`-6-
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`000016
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`FIG. 6 is a cross-sectional view of another embodiment of a surface
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`mounted standing capacitor of the present invention having non-conductive composite
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`end blocks plated with conductive metal.
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`FIGS. 7A and 7B are alternative embodiments ofthe capacitors ofFIGS.
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`5
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`3A and 4A, respectively, each having buried electrodes.
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`FIG. 8 is a perspective view of a hybrid flat capacitor in accordance with
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`the present invention.
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`FIGS. 9A and 9B are cross-sectional views of alternative embodiments
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`of a flat capacitor of the present invention, having a plated non-conductive end block
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`10
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`and conductive end block, respectively.
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`FIGS. lOA and lOB are alternative embodiments ofthe capacitors of
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`FIGS. 9A and 9B, respectively, each having a buried electrode.
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`FIG. llA is a flow chart setting forth an exemplary method in
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`accordance with the present invention for fabricating the capacitor of FIGS. 3A-3B.
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`15
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`FIG. llB is a flow chart setting forth an exemplary method in accordance
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`with the present invention for fabricating the capacitor of FIGS. 4A-4B.
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`FIG. 12A is a perspective view of a partially assembled array for forming
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`a plurality of the capacitors of FIGS. 3A-3B in accordance with the exemplary method
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`set forth in FIG. llA.
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`20
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`FIG. 12B is a perspective view of a partially formed capacitor of the
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`present invention made by the method set forth in FIG. llA.
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`FIG. 13 is a partial side view of an alternative array for forming a
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`plurality of the capacitors of FIGS. 4A-4B in accordance with the exemplary method set
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`forth in FIG. llB.
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`-7-
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`000017
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`Detailed Description
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`The present invention provides surface mountable single layer capacitors
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`that may be easily assembled and inexpensively manufactured. The capacitors of the
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`present invention may utilize thin dielectric layers to provide high capacitance without
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`5
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`sacrificing structural strength. Structural strength is provided by composite end blocks
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`that are either conductive or plated with conductive metal, which further serve as the
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`electrodes or to electrically connect internal electrodes, or metallizations, of the
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`capacitor to the metal surface traces on the pc board.
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`The capacitors of the present invention are manufactured starting in the
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`10
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`green st~te. In one embodiment, a green-state ceramic dielectric sheet is metallized on
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`both sides and placed between a pair of green-state composite metal/ceramic sheets.
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`The sheets are laminated together, then the laminate is diced into a plurality of
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`individual chips. The chips are then fired to sinter the ceramic material. The
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`metallizations on the center dielectric layer, i.e., the internal electrodes, cover less than
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`15
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`the entire area of the dielectric layer, extending to two opposing edges of the dielectric
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`layer and falling short of the other two opposing edges. The ceramic dielectric layer and
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`the ceramic portion of the composite end blocks sinter together at the edges where the
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`metallization falls short, providing increased structural support to the capacitor by virtue
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`of being an essentially monolithic structure. Lastly, the fired chip is electroplated with a
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`20
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`conductive metal. The composite end blocks contain conductive metal, and the center
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`dielectric layer does not contain metal. Thus, the composite end blocks will be
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`preferentially plated due to the metal in the composite, and the pure ceramic of the
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`dielectric layer will not plate. The resulting capacitor is a plated, essentially monolithic
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`structure, meaning that it is an essentially solid structure of materials that are sintered
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`25
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`together, thereby eliminating boundaries/joints within the structure and the structure
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`-8-
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`cr
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`000018
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`contains no epoxy, glue, solder or other attachment means between layers. To state
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`another way, monolithic is generally understood to refer to an object comprised entirely
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`of one single piece (although polycrystalline or even heterogeneous) without joints or
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`seams as opposed to being built up of preformed units. In the present invention, the
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`5
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`only assembly occurs in the green state, and the individual capacitors obtained are
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`sintered, monolithic or essentially monolithic structures. By "essentially" we refer to
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`the presence of the internal metallizations that create a partial boundary or seam within
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`the structure, but because the metallizations do not cover the entire area of the dielectric
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`layer, the ceramic materials sinter together around the edges of the metallizations to
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`10
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`essentially form a monolithic structure. Thus, by monolithic , we refer to the absence of
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`a complete or continuous boundary or seam within the specified structure, with no
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`boundary at all being completely monolithic and a partial boundary being essentially
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`monolithic. The capacitors of the present invention are relatively easy to manufacture
`
`due to assembly occurring before dicing and firing the chips, which further allows for
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`15
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`easy and accurate alignment ofthe components.
`
`In another embodiment of the invention, the green-state dielectric sheet is
`
`placed between the pair of green-state composite metal/ceramic sheets without
`
`metallizations on the dielectric sheet. The metal content in the composite metaVceramic
`
`sheets is sufficient to cause the composite to be conductive. The sheets are then
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`20
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`laminated together, the laminate is diced into a plurality of individual chips, and the
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`chips are fired to sinter the ceramic material. Because the composite end blocks are
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`conductive, plating with conductive metal is unnecessary. The conductive composite
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`end blocks function as the capacitor electrodes and are mountable on the printed metal
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`traces on a pc board. This embodiment eliminates the need to print metallizations on
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`25
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`the dielectric layer, and eliminates the need for plating the end blocks. The resulting
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`-9-
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`000019
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`capacitor is a monolithic structure, with the ceramic in the composite layers sintered
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`together with the center ceramic dielectric layer to eliminate boundaries within the
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`structure thereby providing structural integrity.
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`With reference to the drawings, in which like reference numerals are
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`5
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`used to refer to like parts, FIG. 3A depicts in cross-sectional view a vertically-oriented,
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`surface mountable, single layer capacitor 30 of the present invention. The standing or
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`vertical capacitor 30 is provided having a vertically-oriented ceramic dielectric layer 32
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`with a metallization 34, 36 on each of substantially opposed coplanar surfaces 32a, 32b
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`of the dielectric layer 32. As will be shown and described in further detail below, the
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`10
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`metallizations 34, 36 do not cover the entire area of coplanar surfaces 32a, 32b.
`
`Metal/ceramic composite end blocks 38, 40 are adjacent respective metallizations 34,
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`36. Thereby, an internal face 38a, 40a of each end block 38, 40 is in contacting relation
`
`with a respective metallization 34, 36. The remaining faces 38b, 40b of the end blocks
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`38, 40, referred to as the external faces, are coated with a conductive metal42. The
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`15
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`coating 42 is provided by a plating technique, for example electroless plating, whereby
`
`the conductive metal preferentially plates to the composite end blocks due to the
`
`presence of the metal in the composite, which acts as seed points for the plating metal.
`
`The ceramic dielectric layer 32 does not receive the coating due to the absence of the
`
`metal within the material. The resulting capacitor 30 is shown in perspective view in
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`20
`
`FIG. 3B. Capacitor 30 has four-way symmetry that makes it possible to pick and place
`
`the capacitors mechanically without regard for the orientation, which allows the
`
`capacitor 30 to be positioned and soldered robotically. The end blocks 38, 40 can be
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`soldered using solder 44 directly to printed metal traces 11, 12 on a pc board 10.
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`FIG. 4A depicts in cross-sectional view a vertically-oriented, surface
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`25
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`mountable, single layer capacitor 30' of the present invention. The standing capacitor
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`-10-
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`\ l
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`000020
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`30' is provided having a vertically-oriented ceramic dielectric layer 32. No
`
`metallizations need be provided to opposing surfaces 32a, 32b. Conductive
`
`metaVceramic composite end blocks 38', 40' are adjacent respective opposing surfaces
`
`32a, 32b. Due to capacitor 30' being co fired, the boundary between end blocks 38', 40'
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`5
`
`and dielectric layer 32 is essentially eliminated, as indicated in phantom, by sintering
`
`together the ceramic material, such that capacitor 30' is monolithic, as shown in
`
`perspective view in FIG. 4B. As with capacitor 30, capacitor 30' has four-way
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`symmetry such that it may be positioned and soldered robotically without regard for
`
`orientation. Conductive end blocks 38', 40' can be soldered directly to printed metal
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`10
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`traces 11, 12 on a pc board 10, thereby providing axial leads for the capacitor 30'.
`
`In the embodiment depicted in FIGS. 3A and 3B, the end blocks 38, 40
`
`comprise a composite metal/ceramic material in which particles of conductive metal are
`
`dispersed in a ceramic matrix. The metal particles provide seed points for the
`
`electroplating process, drawing the conductive metal42 to the end blocks 38, 40 while
`
`15
`
`allowing the ceramic gap 32 to remain un-coated. The metal particles may be in the
`
`form of a powder or flakes, for example. The powder or flakes are added to the
`
`ceramic, and the mixture is formed into a green-state tape or sheet, which may
`
`subsequently be assembled with the dielectric layer, diced, and hardened by co firing the
`
`structure. Alternatively, the composite metaVceramic material may comprise a ceramic
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`20
`
`powder wherein the particles are coated with the conductive metal, for example a
`
`ceramic coated with a palladium-silver alloy, and the coated powder is formed into a
`
`green-state tape or sheet, followed by assembly, dicing and firing.
`
`In the embodiment depicted in FIGS. 4A and 4B, the end blocks 38', 40'
`
`comprise a composite metaVceramic material in which the particles of conductive metal
`
`25
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`are present in an amount sufficient to render the composite matrix conductive. In
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`-11-
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`r7
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`~..,~"
`
`II
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`000021
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`

`
`general, the matrix becomes conductive when the metal particles start to touch.
`
`Referring to FIG. 5, the graph indicates that 100% ceramic is non-conductive and 100%
`
`metal is conductive. For composites between 100% cerami