(12) United States Patent
`Devoe et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,661,639 B1
`Dec. 9, 2003
`
`US006661639B1
`
`(54) SINGLE LAYER CAPACITOR
`
`1/1999 Haq et al. ................. .. 428/210
`5,855,995 A
`6,088,215 A * 7/2000 Webb et al. ........... .. 361/3063
`
`
`Inventors: Alan Devoe, La Jolla, Lambert Devoe, San Diego, CA (US);
`Hung Trinh, San Diego, CA (US)
`
`Ingalls et al. . . . . . . . . . . . . . ..
`OTHER PUBLICATIONS
`
`_
`(73) Asslgnee?
`
`_
`
`_
`
`_
`Components, Inc» San D1eg0>
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`.
`.
`patent is extended or adJusted under 35
`U-S-C- 154(k)) by 0 days-
`
`(21) APPL No: 10/188,696
`_
`Jul- 2! 2002
`(22) Flled?
`(51) Int. c1.7 ...................... .. H01G 4/005; H01G 4/228;
`H016 4/ 06
`(52) US. Cl. ................... .. 361/303; 361/306.1; 361/311
`(58) Field of Search ......................... .. 361/3011, 301.3,
`361/3014, 303_305, 306_1_306_3, 307,
`308_1_308_3, 309, 310_313, 320
`
`(56)
`
`References Cited
`
`U-S~ PATENT DOCUMENTS
`4,439,s13 A
`3/1984 Dougherty et al. ....... .. 361/321
`4,819,128 A
`4/1989 Florian et aL
`361/321
`4’864’465 A
`9 /1989 Robbins ____________ __
`361/320
`4,881,308 A * 11/1989 McLaughlin et a1, ____ __ 29/25_42
`5,177,663 A
`1/1993 Ingleson et al.
`361/321
`5,220,483 A
`6/1993 seott -------------- --
`-- 361/313
`2
`£21110“ et 91- ~~
`91159110 """" "
`7
`’
`5’59O’016 A 12/1996 Fullshl?" et a1‘ """"" " 361/313
`5,599,414 A
`2/1997 Roethlingshoefer et a1. .. 156/89
`5,712,758 A
`1/1998 Amano et a1. ......... .. 361/3212
`5,757,611 A
`5/1998 Gurovich et al. ...... .. 361/3214
`
`American Technical Ceramics, AT C Millimeter Wavelength
`Single Layer Capacitors, Brochure, 3 pp., Revised Feb.
`1998.
`Com-P6X- COrp’MlCrOWave Chip Capacitors’ Brochure’ 3 pp'
`publication (date unknown).
`
`* cited by examiner
`
`Primary Examiner—Dean A. Reichard
`ssistant xaminer
`r1c
`omas
`A '
`E ' —E Th
`(74) Attorney, Agent, or Firm—Wood, Herron & Evans,
`LLP
`(57)
`
`ABSTRACT
`_
`_
`_
`_
`_
`_
`_
`Amonclhttnc or essennany monohthlc smgle layer Capacltor
`With high structural strength and capacitance. Sheets of
`green-state ceramic dielectric material and ceramic/metal
`composite material are laminated together, diced into indi
`vidual chips, and ?red to sinter the ceramic together. The
`composite material may contain an amount of metal su?i
`cient to render the composite conductive Whereby the com
`posltemay be use?‘ for one or, both electrodes_and for
`mounting the capacitor. Alternatively, the composite mate
`rial may contain an amount of metal insuf?cient to render the
`composite conductive but suf?cient to act as seed points for
`an electroplating process Wherein the composite is prefer
`entially coated With conductive metal, the coated composite
`is mounted, and the coating provides an electrical connec
`tion to an internal electrode. Vertically-oriented surface
`mountable capacitors and hybrid capacitors are provided.
`
`21 Claims, 6 Drawing Sheets
`
`AVX CORPORATION 1001
`
`000001
`
`

`
`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 1 6f 6
`
`US 6,661,639 B1
`
`74
`6
`(/5 ( 7&6
`\
`
`
`
`
`
`/éa
`//
`
`
`
`
`I / / I , / I I [w / k) \ 1 1 1 i 1 I I 1 1 1(
`
`'/%///7'/7///
`
`g9\[/ P/_“J/
`:/ '
`/ / w
`
`J
`V///7///'///%
`
`/0/ PRIQR ART
`FIG. 2
`
`PRIOR ART
`FIG. 1
`
`31;?‘ 341% ‘fag/15¢ ‘46
`3,9255%
`'if/ékf/y
`T
`1'
`
`38a
`
`35a
`
`3/96
`
`\
`\ \ I I
`
`1
`
`“\E
`
`”\
`
`FIG. 3A
`
`FIG. 3B
`
`000002
`
`

`
`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 2 6f 6
`
`US 6,661,639 B1
`
`30
`
`I ///
`
`ll/ //
`
`FIG. 4A
`
`40’
`
`32
`
`f3”
`
`FIG. 4B
`
`I
`
`METAL FORMS
`’
`METAL F
`f'_* CONDUCTIVE
`SEED POIN
`:
`MATRIX
`ELECTROP
`i
`IL
`100% NON-CONDUCTIVE X% CERAMIC/
`CERAMIC
`Y% METAL
`
`1'
`100% CONDUCTIVE
`METAL
`
`FIG. 5
`
`000003
`
`

`
`US 6,661,639 B1
`
`V r A v v v a r
`
`fé0
`
`U.S. Patent
`
`Dec. 9, 2003
`
`(5%
`
`54
`
`3.9
`
`56.2’
`
`Sheet 3 6f 6
`36 /
`
`3.3
`
`34
`
`h ~ ~ a ~ ~ ~ ~ ~
`
`~ \ ~ ~ ~ n ~ ~ ~
`
`\\\\\
`
`K56
`
`58
`
`K56
`
`$13
`
`~ ~ N ~ ~ ~ ~ ~ u ~ ~
`
`I'IIII' 1
`
`g! 4
`
`ééa
`
`FIG. 6
`
`I Mi.
`
`FIG. 7A
`
`FIG. 7B
`
`$5
`
`/3/
`
`FIG. 8
`
`000004
`
`

`
`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 4 6f 6
`
`US 6,661,639 B1
`
`Q6
`7847
`A88
`
`FIG. 13
`
`000005
`
`

`
`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 5 6f 6
`
`US 6,661,639 B1
`
`PROVIDE GREEN STATE
`DIELECTRIC SHEET
`
`PLACE DIELECTRIC SHEET 0N GREEN
`sTATE CERAMIC/METAL COMPOSITE
`SHEET
`
`PLACE GREEN STATE CERAMIC/METAL
`COMPOSITE sHEET ON DIELECTRIC
`SHEET
`
`LAMIIAQLETEEFEETS
`
`DICE THE LAMINATE
`INTO CHIPS
`
`FIRE THE CHIPS
`
`PROVIDE GREEN STATE
`DIELECTRIC SHEET
`
`I
`PRINT METALLIZATIONS ON EACH
`OPPOSING FACE OF D'ELECTR'C
`SHEET IN SPACED STRIPS
`EXTENDING TO oPPosED EDGEs
`
`PLACE METALLIZED DIELECTRIC
`sHEET 0N GREEN sTATE
`CERAMIC/METAL COMPOSITE SHEET
`
`PLACE GREEN sTATE CERAMIC/METAL
`COMPOSITE sHEET ON METALLIZED
`DIELECTRIC SHEET
`
`LAMINATE SHEETS
`TOGETHER
`
`DICE THE LAMINATE INTO CHIPS, FIRST
`ALONG SPACES BETWEEN THE
`METALLIZATION STRIPS, THEN CROSSWISE
`
`FIRE THE CHIPS
`
`I
`ELECTROPLATE CHIPS TO PROVIDE METAL
`COATING ON EXPOSED EXTERNAL FACES OF
`COMPOSITE, BUT NOT ON DIELECTRIC
`
`FIG. 11A
`
`000006
`
`

`
`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 6 6f 6
`
`US 6,661,639 B1
`
`FIG. 12A
`
`7130/
`
`FIG. 12B
`
`000007
`
`

`
`US 6,661,639 B1
`
`1
`SINGLE LAYER CAPACITOR
`
`FIELD OF THE INVENTION
`
`This invention relates to single layer capacitors, and in
`particular, surface mountable single layer capacitors and a
`method of making the capacitors.
`
`BACKGROUND OF THE INVENTION
`
`The “parallel plate” or “single layer” ceramic capacitor
`has a very useful form factor for assembly into microWave
`frequency and similar electrical circuits. These circuits may
`be laid out on printed circuit (pc) boards, or be present on
`integrated circuits (ICs) Within chip carriers and other pack
`ages Where space is typically even more precious. The
`dimensions of the ceramic capacitor can be matched to the
`Width of a strip line on the pc board or the chip carrier
`holding an IC.
`In assembly, the bottom face of the ceramic chip capacitor
`is typically soldered to or conductive epoxy attached to the
`surface of the pc board substrate. The top face of the ceramic
`capacitor normally presents one or more electrically con
`ductive pads that are typically ribbon- or Wire-bonded to
`another circuit connection point.
`Most ceramic chip capacitors currently offered are made
`by metalliZing tWo faces of a thin sheet of sintered ceramic
`that is typically in the range of 4 mils to 10 mils thick. The
`metalliZed ceramic sheet is then cut to siZe by saWing or
`abrasive cutting techniques. Typical siZes of the chip capaci
`tors range from 10 mils square to 50 mils (inches) square,
`although some applications use rectangular forms.
`While the form factor of these simple devices—used in
`quantities of hundreds of millions per year—is highly
`desirable, the amount of capacitance that can be achieved
`and quality of the devices realiZing maximum capacitance is
`starting to limit their usefulness in certain applications. The
`simpli?ed equation for the capacitance of a parallel plate
`capacitor, c=KA/d Where K is the dielectric constant, A the
`area of each of opposed plates, and d the distance of
`separation betWeen plates, shoWs that a 20 mils square part
`(A) of 5 mils thickness (d) made from ceramic With a
`relative dielectric constant of 100 yields a capacitance of 8
`picofarads.
`This ?ve mils thickness—necessitated in order to estab
`lish some structural strength for the given area siZe of, for
`example, 20 mils><20 mils—means that the capacitor does
`not have much structural strength, and is subject to unde
`sirable fracturing or chipping during routine handling and
`assembly into circuits. Thus, the physical resistance to
`damage of the highest-capacitance “parallel plate” or “single
`layer” ceramic capacitors is innately poor. The design of
`single layer capacitors in general is a compromise betWeen
`the use of thicker ceramic layers for greater strength and
`thinner ceramic layers for greater capacitance.
`In addition to the dif?culties in achieving high capaci
`tance While maintaining structural strength, due to the small
`siZe of the capacitors, they are dif?cult to attach automati
`cally to a pc board. One approach has been to use a ?at,
`horiZontal capacitor With the metalliZation on its loWer side
`having a gap. A device of this type is referred to as the
`GAP-CAPTM manufactured by Dielectric Laboratories, Inc.
`A GAP-CAPTM device is shoWn in FIG. 1, mounted onto a
`pc board 10 in Which metal traces 11 and 12 constitute a
`transmission line. The ?at capacitor 13 is horiZontally dis
`posed to bridge the gap betWeen the traces 11, 12. The
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`2
`capacitor 13 has a dielectric chip or slice 14 that is elongated
`in the horiZontal direction, With a metalliZed upper surface
`15 and metalliZed loWer surface portions 16a and 16b, Which
`are electrically joined to the traces 11 and 12, respectively.
`HoWever, these devices can create unWanted resonances at
`frequencies above a feW gigahertZ. In addition, these capaci
`tors are quite small, typically about 20—25 mils. At these
`siZes, the capacitors are dif?cult to handle, and must be
`installed using a microscope. The capacitor 13 has a de?nite
`top and bottom, and it is crucial to install them in the proper
`orientation, to avoid shorting the circuit. Thus, mounting of
`the capacitor is dif?cult and expensive. Also, the additional
`requirement of attaching metal leads may further contribute
`to prohibitive manufacturing costs.
`Another approach has been to use a standing dielectric
`chip With opposed metalliZed surfaces, and With metal leads
`attached to the respective surfaces. A prior art standing
`leaded capacitor 18 is shoWn in FIG. 2 installed on the traces
`11, 12 of the pc board 10. The capacitor is formed of a
`vertically-oriented ceramic chip 19 With metalliZed front and
`back surfaces 20, 21. There are ?at metal leads 22, 23 af?xed
`onto the metalliZed surfaces 20, 21 and these are soldered
`onto the metal traces 11, 12, respectively. The capacitor 18
`has to be held in place While the leads 22, 23 are soldered
`to their respective places. The leads 22, 23 are fragile, and
`require extreme care in fabrication, shipping, handling and
`soldering in place to the traces 11, 12. Thus, the capacitors
`18 have to be installed manually under a microscope, and
`robotiZed or automated circuit fabrication is difficult or
`impossible to obtain. In addition, the standing leaded capaci
`tor 18 produces signi?cant signal resonances, especially for
`frequencies above a feW gigahertZ.
`It is desirable to provide a single layer capacitor that is
`surface mountable, thereby eliminating the requirement for
`Wire bonding, Which may be prohibitively expensive, and/or
`that can utiliZe a thin dielectric layer Without sacri?cing
`structural strength. A surface mountable capacitor is
`described in US. Pat. No. 6,208,501, Wherein metal or
`metal-coated ceramic end blocks are soldered to a vertically
`oriented dielectric chip sandWiched there betWeen, Whereby
`the end blocks serve as leads for attaching to metallic surface
`traces on the pc board. While the standing axial-leaded
`surface mount capacitor described in that patent is an
`improvement over the prior devices, the end blocks, Which
`are described as 20—25 mils square blocks, must be manually
`assembled With the dielectric chip, Which is a sloW, intricate
`and expensive process subject to inaccurate alignment of the
`various components and to joint disattachment betWeen the
`components during shipping and handling. For example, the
`block and/or metalliZation may pull aWay from the dielectric
`layer, causing the capacitor to open during use Whereupon
`the capacitance Will drop dramatically. In addition, the
`device described in that patent has a 20—25 mil Width to
`match the Width of a typical printed circuit trace. More
`speci?cally, the device is manufactured, for example, With a
`50><20><20 mil siZe. HoWever, at 40 gigahertZ, the required
`trace Width on the pc board is 10 mils Wide. So at 40
`gigahertZ, the optimal chip siZe is 20><10><10 mil. The
`smaller the chip siZe, the more dif?cult and expensive it Will
`be to mechanically assemble the end blocks to the dielectric
`chip. Moreover, in practice, only a limited range of capaci
`tance values may be produced, thereby limiting the ?exibil
`ity of the product to meet consumer demands.
`There is thus a need to provide a surface mountable single
`layer ceramic capacitor that may be easily assembled and
`inexpensively manufactured, and that has high capacitance
`and good structural strength.
`
`000008
`
`

`
`US 6,661,639 B1
`
`3
`SUMMARY OF THE INVENTION
`The present invention provides a monolithic or essentially
`monolithic single layer capacitor With good structural
`strength that may be easily and inexpensively manufactured,
`and Which may utiliZe thin dielectric layers to provide high
`capacitance. To this end, sheets of green-state ceramic
`dielectric material and ceramic/metal composite material are
`laminated together, diced into individual chips, and ?red to
`sinter the ceramic together. The composite material may
`comprise an amount of metal sufficient to render the com
`posite conductive Whereby the composite may be used for
`one or both electrodes and for mounting the capacitor to the
`pc board. Alternatively, the composite material may com
`prise an amount of metal insuf?cient to render the composite
`conductive but suf?cient to act as seed points for an elec
`troplating process Wherein the composite is preferentially
`coated With conductive metal, and the coated composite is
`mounted to the pc board and the coating provides an
`electrical connection to an internal electrode. By the present
`invention, a capacitor is provided having a vertically
`oriented dielectric betWeen composite end blocks to provide
`a surface mountable capacitor Which is monolithic or essen
`tially monolithic. By the present invention a hybrid capaci
`tor is also provided having a horizontally-oriented dielectric
`on a composite block mountable to the pc board and either
`a second composite block or a metalliZation on the dielectric
`for Wire bonding to the pc board. By virtue of at least one
`composite block mountable to the pc board, a thin dielectric
`may be used While maintaining high structural integrity for
`the capacitor. Moreover, by assembling the portions of the
`capacitor in the green-state, and co-?ring the assembly, a
`monolithic or essentially monolithic structure is formed
`having no preformed parts and containing no epoxy, glue,
`solder, or attachment means Within the capacitor body thus
`further providing high structural integrity for the capacitor
`and simplifying the manufacturing process While alloWing
`for further miniaturiZation of capacitors. The green-state
`method further provides ?exibility that alloWs for a broad
`range of capacitor values to be obtained as desired by the
`consumer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying draWings, Which are incorporated in
`and constitute a part of this speci?cation, illustrate embodi
`ments of the invention and, together With a general descrip
`tion of the invention given above, and the detailed descrip
`tion given beloW, serve to explain the invention.
`FIG. 1 is a cross-sectional vieW of a prior art ?at capacitor.
`FIG. 2 is a cross-sectional vieW of a prior art standing
`leaded capacitor.
`FIG. 3A is a cross-sectional vieW of one embodiment of
`a surface mounted standing capacitor of the present inven
`tion having non-conductive composite end blocks plated
`With conductive metal.
`FIG. 3B is a perspective vieW of the capacitor of FIG. 3A.
`FIG. 4A is a cross-sectional vieW of another embodiment
`of a surface mounted standing capacitor of the present
`invention having conductive composite end blocks.
`FIG. 4B is a perspective vieW of the capacitor of FIG. 4A.
`FIG. 5 is a graph illustrating the effect of composition on
`the conductivity of the composite end blocks that form a
`portion of the capacitors of the present invention.
`FIG. 6 is a cross-sectional vieW of another embodiment of
`a surface mounted standing capacitor of the present inven
`tion having non-conductive composite end blocks plated
`With conductive metal.
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`4
`FIGS. 7A and 7B are alternative embodiments of the
`capacitors of FIGS. 3A and 4A, respectively, each having
`buried electrodes.
`FIG. 8 is a perspective vieW of a hybrid ?at capacitor in
`accordance With the present invention.
`FIGS. 9A and 9B are cross-sectional vieWs of alternative
`embodiments of a ?at capacitor of the present invention,
`having a plated non-conductive end block and conductive
`end block, respectively.
`FIGS. 10A and 10B are alternative embodiments of the
`capacitors of FIGS. 9A and 9B, respectively, each having a
`buried electrode.
`FIG. 11A is a How chart setting forth an exemplary
`method in accordance With the present invention for fabri
`cating the capacitor of FIGS. 3A—3B.
`FIG. 11B is a How chart setting forth an exemplary
`method in accordance With the present invention for fabri
`cating the capacitor of FIGS. 4A—4B.
`FIG. 12A is a perspective vieW of a partially assembled
`array for forming a plurality of the capacitors of FIGS.
`3A—3B in accordance With the exemplary method set forth
`in FIG. 11A.
`FIG. 12B is a perspective vieW of a partially formed
`capacitor of the present invention made by the method set
`forth in FIG. 11A.
`FIG. 13 is a partial side vieW of an alternative array for
`forming a plurality of the capacitors of FIGS. 4A—4B in
`accordance With the exemplary method set forth in FIG.
`11B.
`
`DETAILED DESCRIPTION
`
`The present invention provides surface mountable single
`layer capacitors that may be easily assembled and inexpen
`sively manufactured. The capacitors of the present invention
`may utiliZe thin dielectric layers to provide high capacitance
`Without sacri?cing structural strength. Structural strength is
`provided by composite end blocks that are either conductive
`or plated With conductive metal, Which further serve as the
`electrodes or to electrically connect internal electrodes, or
`metalliZations, of the capacitor to the metal surface traces on
`the pc board.
`The capacitors of the present invention are manufactured
`starting in the green state. In one embodiment, a green-state
`ceramic dielectric sheet is metalliZed on both sides and
`placed betWeen a pair of green-state composite metal/
`ceramic sheets. The sheets are laminated together, then the
`laminate is diced into a plurality of individual chips. The
`chips are then ?red to sinter the ceramic material. The
`metalliZations on the center dielectric layer, i.e., the internal
`electrodes, cover less than the entire area of the dielectric
`layer, extending to tWo opposing edges of the dielectric layer
`and falling short of the other tWo opposing edges. The
`ceramic dielectric layer and the ceramic portion of the
`composite end blocks sinter together at the edges Where the
`metalliZation falls short, providing increased structural sup
`port to the capacitor by virtue of being an essentially
`monolithic structure. Lastly, the ?red chip is electroplated
`With a conductive metal. The composite end blocks contain
`conductive metal, and the center dielectric layer does not
`contain metal. Thus, the composite end blocks Will be
`preferentially plated due to the metal in the composite, and
`the pure ceramic of the dielectric layer Will not plate. The
`resulting capacitor is a plated, essentially monolithic
`structure, meaning that it is an essentially solid structure of
`materials that are sintered together, thereby eliminating
`
`000009
`
`

`
`US 6,661,639 B1
`
`5
`boundaries/joints Within the structure and the structure con
`tains no epoxy, glue, solder or other attachment means
`betWeen layers. To state another Way, monolithic is generally
`understood to refer to an object comprised entirely of one
`single piece (although polycrystalline or even
`heterogeneous) Without joints or seams as opposed to being
`built up of preformed units. In the present invention, the only
`assembly occurs in the green state, and the individual
`capacitors obtained are sintered, monolithic or essentially
`monolithic structures. By “essentially” We refer to the pres
`ence of the internal metalliZations that create a partial
`boundary or seam Within the structure, but because the
`metalliZations do not cover the entire area of the dielectric
`layer, the ceramic materials sinter together around the edges
`of the metalliZations to essentially form a monolithic struc
`ture. Thus, by monolithic , We refer to the absence of a
`complete or continuous boundary or seam Within the speci
`?ed structure, With no boundary at all being completely
`monolithic and a partial boundary being essentially mono
`lithic. The capacitors of the present invention are relatively
`easy to manufacture due to assembly occurring before dicing
`and ?ring the chips, Which further alloWs for easy and
`accurate alignment of the components.
`In another embodiment of the invention, the green-state
`dielectric sheet is placed betWeen the pair of green-state
`composite metal/ceramic sheets Without metalliZations on
`the dielectric sheet. The metal content in the composite
`metal/ceramic sheets is sufficient to cause the composite to
`be conductive. The sheets are then laminated together, the
`laminate is diced into a plurality of individual chips, and the
`chips are ?red to sinter the ceramic material. Because the
`composite end blocks are conductive, plating With conduc
`tive metal is unnecessary. The conductive composite end
`blocks function as the capacitor electrodes and are mount
`able on the printed metal traces on a pc board. This embodi
`ment eliminates the need to print metalliZations on the
`dielectric layer, and eliminates the need for plating the end
`blocks. The resulting capacitor is a monolithic structure,
`With the ceramic in the composite layers sintered together
`With the center ceramic dielectric layer to eliminate bound
`aries Within the structure thereby providing structural integ
`rity.
`With reference to the draWings, in Which like reference
`numerals are used to refer to like parts, FIG. 3A depicts in
`cross-sectional vieW a vertically-oriented, surface
`mountable, single layer capacitor 30 of the present inven
`tion. The standing or vertical capacitor 30 is provided having
`a vertically-oriented ceramic dielectric layer 32 With a
`metalliZation 34, 36 on each of substantially opposed copla
`nar surfaces 32a, 32b of the dielectric layer 32. As Will be
`shoWn and described in further detail beloW, the metalliZa
`tions 34, 36 do not cover the entire area of coplanar surfaces
`32a, 32b. Metal/ceramic composite end blocks 38, 40 are
`adjacent respective metalliZations 34, 36. Thereby, an inter
`nal face 38a, 40a of each end block 38, 40 is in contacting
`relation With a respective metalliZation 34, 36. The remain
`ing faces 38b, 40b of the end blocks 38, 40, referred to as the
`external faces, are coated With a conductive metal 42. The
`coating 42 is provided by a plating technique, for example
`electroless plating, Whereby the conductive metal preferen
`tially plates to the composite end blocks due to the presence
`of the metal in the composite, Which acts as seed points for
`the plating metal. The ceramic dielectric layer 32 does not
`receive the coating due to the absence of the metal Within the
`material. The resulting capacitor 30 is shoWn in perspective
`vieW in FIG. 3B. Capacitor 30 has four-Way symmetry that
`makes it possible to pick and place the capacitors mechani
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`6
`cally Without regard for the orientation, Which alloWs the
`capacitor 30 to be positioned and soldered robotically. The
`end blocks 38, 40 can be soldered using solder 44 directly
`to printed metal traces 11, 12 on a pc board 10.
`FIG. 4A depicts in cross-sectional vieW a vertically
`oriented, surface mountable, single layer capacitor 30‘ of the
`present invention. The standing capacitor 30‘ is provided
`having a vertically-oriented ceramic dielectric layer 32. No
`metalliZations need be provided to opposing surfaces 32a,
`32b. Conductive metal/ceramic composite end blocks 38‘,
`40‘ are adjacent respective opposing surfaces 32a, 32b. Due
`to capacitor 30‘ being co?red, the boundary betWeen end
`blocks 38‘, 40‘ and dielectric layer 32 is essentially
`eliminated, as indicated in phantom, by sintering together
`the ceramic material, such that capacitor 30‘ is monolithic, as
`shoWn in perspective vieW in FIG. 4B. As With capacitor 30,
`capacitor 30‘ has four-Way symmetry such that it may be
`positioned and soldered robotically Without regard for ori
`entation. Conductive end blocks 38‘, 40‘ can be soldered
`directly to printed metal traces 11, 12 on a pc board 10,
`thereby providing axial leads for the capacitor 30‘.
`In the embodiment depicted in FIGS. 3A and 3B, the end
`blocks 38, 40 comprise a composite metal/ceramic material
`in Which particles of conductive metal are dispersed in a
`ceramic matrix. The metal particles provide seed points for
`the electroplating process, draWing the conductive metal 42
`to the end blocks 38, 40 While alloWing the ceramic gap 32
`to remain un-coated. The metal particles may be in the form
`of a poWder or ?akes, for example. The poWder or ?akes are
`added to the ceramic, and the mixture is formed into a
`green-state tape or sheet, Which may subsequently be
`assembled With the dielectric layer, diced, and hardened by
`co?ring the structure. Alternatively, the composite metal/
`ceramic material may comprise a ceramic poWder Wherein
`the particles are coated With the conductive metal, for
`example a ceramic coated With a palladium-silver alloy, and
`the coated poWder is formed into a green-state tape or sheet,
`folloWed by assembly, dicing and ?ring.
`In the embodiment depicted in FIGS. 4A and 4B, the end
`blocks 38‘, 40‘ comprise a composite metal/ceramic material
`in Which the particles of conductive metal are present in an
`amount suf?cient to render the composite matrix conductive.
`In general, the matrix becomes conductive When the metal
`particles start to touch. Referring to FIG. 5, the graph
`indicates that 100% ceramic is non-conductive and 100%
`metal is conductive. For composites betWeen 100% ceramic
`and x% ceramic/y% metal, the metal content is insuf?cient
`to render the composite matrix conductive, but the metal Will
`act as seed points for electroless plating of the end blocks 38,
`40. For composites betWeen x% ceramic/y% metal and
`100% metal, the metal content is suf?cient for the metal
`particles to touch each other, thereby rendering the compos
`ite matrix conductive. Electroplating is optional because end
`blocks 38‘, 40‘ are already conductive. The internal metal
`liZations 34, 36 are also optional because the conductive end
`blocks 38‘, 40‘ are capable of serving as the electrodes for the
`capacitor.
`The amount of metal suf?cient to render the composite
`matrix conductive Will vary depending mainly on the metal
`particle morphology. For example, y% Will generally need to
`be higher for spherical poWder metal than for metal ?akes.
`The metal portion of the composite material advantageously
`comprises betWeen about 10% and about 90% of the com
`posite. If present in an amount less than about 10%, the
`content may be insuf?cient to establish seed points that
`alloW the conductive metal 42 to preferentially plate the
`composite end blocks 38, 40. While an amount greater than
`
`000010
`
`

`
`US 6,661,639 B1
`
`10
`
`15
`
`20
`
`25
`
`7
`about 90% may be used, the ceramic content is advanta
`geously present in an amount suf?cient to adhere the com
`posite to the dielectric layer 32, and to control the sintering
`of the composite such that it more closely relates to the
`sintering of the dielectric layer 32. By Way of example, using
`Ag ?akes, Where the Ag content of the composite is in the
`range of about 10% up to less than about 40%, the metal
`tends to act as seed points for the preferential plating of the
`end blocks 38, 40. Where the Ag content is at least about
`40% up to about 90%, the entire composite matrix becomes
`conductive.
`The conductive metal may be Ag, AgNO3 or AgCO3, for
`example. Alternatively, Cu and Ni and alloys thereof may be
`used, but these metal systems Will generally require a
`reducing atmosphere. Pd, Pt, Au and alloys thereof may also
`be used, but these metal systems are generally more expen
`sive than Ag-based systems. Advantageously, the ceramic
`material is an ultra-loW ?ring ceramic, for example, one that
`?res around 900° C. An exemplary ceramic is a BaTiO3
`based ceramic. The metals generally used for the conductive
`metal portion of the composite generally sinter around 800°
`C. such that the ultra-loW ?ring ceramic materials Will be
`most compatible With the metal portion. Regardless, the
`ceramic material must sinter beloW the melting point of the
`metal. Advantageously, the ceramic material in the compos
`ite is the same as the ceramic material used for dielectric
`layer 32.
`FIG. 6 provides an alternative embodiment in Which a
`capacitor 46 of the present invention includes end blocks 48,
`50 that comprise thin alternating layers of ceramic ?lm 52
`and metal ?lm 54 Whereby each ceramic ?lm 52 in the end
`blocks 48, 50 is thin enough that electroplating Will occur
`over the ceramic ?lm from metal layer 54 to metal layer 54
`to provide the conductive metal coating 56 on the end blocks
`48, 50. Because the metal ?lms 54 do not touch each other,
`the composite matrix Will not be conductive, and thus,
`electroplating the end blocks 48, 50 is necessary.
`Advantageously, the layers adjacent the dielectric layer 32
`are ceramic ?lms 52 such that the ceramic ?lm 52 sinters
`With the dielectric layer 32 in the unmetalliZed areas. While
`the metal ?lms 54 technically create boundaries Within the
`structure, the capacitor 46 is still considered essentially
`monolithic due to the absence of preformed parts that
`require epoxy, glue, solder or other attachments means
`betWeen layers.
`45
`Another alternative embodiment is provided in FIGS. 7A
`and 7B, Wherein capacitors 60 and 60‘, similar to capacitors
`30 and 30‘, respectively, are provided having a dielectric
`layer 62 that includes buried electrodes. Speci?cally, for
`capacitor 60 as shoWn in FIG. 7A, a pair of internal buried
`electrodes 64a, 64b are provided Within the dielectric layer
`62, and connected to metalliZation areas 66a, 66b by a
`plurality of vias 68. Any number of vias 68 may be used
`providing that at least one via connects each buried electrode
`64a, 64b to a respective metalliZation 66a, 66b. For capaci
`tor 60‘ as shoWn in FIG. 7B, vias 68 connect the buried
`electrodes 64a, 64b to respective conductive end blocks 38‘,
`40‘. Advantageously, the buried electrodes 64a, 64b and vias
`68 comprise the same metal as the metalliZations 66a, 66b
`or end blocks 38‘, 40‘. Use of the buried electrodes and vias
`enables variation of the capacitance of capacitors 60, 60‘.
`If desired, the same basic constructions used for capaci
`tors 30, 30‘, 46, 60 and 60‘ may be used With different aspect
`ratios to create a horiZontally-oriented hybrid capacitor 31,
`as shoWn in perspective vieW in FIG. 8. FIG. 8 depicts a
`horiZontally-disposed capacitor chip 74 betWeen top and
`bottom composite end blocks 71, 72 plated With conductive
`
`30
`
`35
`
`40
`
`50
`
`55
`
`60
`
`65
`
`8
`metal 80, Wherein bottom end block 72 is mounted on the pc
`board 10 (not shoWn) and the top end block 71 is connected
`by Wire bonding (not shoWn). Hybrid refers to the fact that
`the tWo electrodes of the capacitor 31 are electrically con
`nected to the pc board by tWo different methods. While the
`horiZontally-oriented capacitor 31 requires Wire bonding,
`the capacitor 31 is still symmetrical, alloWing for its place
`ment on the pc board 10 Without regard for orientation,
`thereby representing an advantage over prior art Wire
`bonded capacitors. Moreover, due to the presence of the
`composite material end blocks 71, 72, the dielectric layer 74
`may be made thinner Without sacri?cing the structural
`integrity of the capacitor 31.
`While FIG. 8 depicts in perspective vieW a horiZontally
`disposed capacitor chip 74 betWeen top and bottom com
`posite end blocks 71, 72, it may be appreciated that the top
`end block 71 may be eliminated, for example as shoWn in
`FIGS. 9A and 9B. FIG. 9A depicts a horiZontally-disposed
`hybrid capacitor 70 With a single composite block 72 for
`mounting directly on the pc board 10. The dielectric layer 74
`is oriented horiZontally With respect to th