UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
`
`Petitioner
`
`v.
`
`AU OPTRONICS CORPORATION
`
`Patent Owner
`
`
`
`Patent No. 6,689,629 C1
`Issued: November 14, 2014
`Filed: March 16, 2010
`
`Inventors: Takatoshi TSUJIMURA et al.
`
`Title: ARRAY SUBSTRATE FOR DISPLAY, METHOD OF
`MANUFACTURING ARRAY SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`
`
`Inter Partes Review No.: Unassigned
`
`
`
`DECLARATION OF YUE KUO, DR.ENG.SCI.
`
`
`
`
`
`ChinaStar Ex.1011
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
`
`Petitioner
`
`v.
`
`AU OPTRONICS CORPORATION
`
`Patent Owner
`
`
`
`Patent No. 6,689,629 C1
`Issued: November 14, 2014
`Filed: March 16, 2010
`
`Inventors: Takatoshi TSUJIMURA et al.
`
`Title: ARRAY SUBSTRATE FOR DISPLAY, METHOD OF
`MANUFACTURING ARRAY SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`
`
`Inter Partes Review No.: Unassigned
`
`
`
`DECLARATION OF YUE KUO, DR.ENG.SCI.
`
`
`
`
`
`ChinaStar Ex.1011
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION AND BACKGROUND .................................................... 1
`
`SUMMARY OF MY OPINIONS ................................................................... 4
`
`A.
`
`B.
`
`Instructions ............................................................................................ 4
`
`Effective Filing Dates and Prior Art Patents and Printed Publications 9
`
`III. OVERVIEW OF THE TECHNOLOGY ....................................................... 10
`
`A.
`
`Summary of the Prosecution History of the '629 Patent ..................... 12
`
`IV. CLAIM CONSTRUCTION .......................................................................... 13
`
`V. ANALYSIS .................................................................................................... 15
`
`A. Ground 1: Claims 1, 3, 5-6, 9, 11, 14, and 17 are obvious under
`35 U.S.C. § 103 in view of Noda, AAPA, Tsujimura, Ichioka, and
`Shimizu. ............................................................................................... 15
`
`B.
`
`Ground 2: Claims 7-8 and 15-16 are obvious under 35 U.S.C. § 103
`in view of Noda, AAPA, Tsujimura, Ichioka, Shimizu, and Wicke. .. 33
`
`C. Ground 3: Claims 1, 9, and 17 are obvious under 35 U.S.C. § 103
`under Noda, AAPA, Tsujimura, Ichioka, and Ono. ............................ 36
`
`VI. CONCLUSION .............................................................................................. 42
`
`
`
`
`
`i
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`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`EXHIBITS
`
`I may refer to the following Exhibits that I understand were submitted by
`
`Petitioner in connection with this Inter Partes Review ("IPR").
`
`1006
`
`1007
`1008
`
`Exhibit Description
`1001
`U.S. Patent No. 6,689,629 C1 ("the '629 Patent")
`1002
`File History of U.S. Patent No. 6,689,629 C1
`1003
`U.S. Patent No. 6,689,629 B2
`1004
`File History of U.S. Patent No. 6,689,629 B2
`1005
`Certified English Translation of Japanese Publication No. P2000-
`98909A ("Noda")
`Low Resistance Gate Line for High-Resolution TFT/LCD Display
`("Tsujimura")
`U.S. Patent No. 5,546,013 ("Ichioka")
`Certified English Translation of Japanese Publication No. HEI 2-
`189922 ("Shimizu")
`U.S. Patent No. 2,990,282 ("Wicke")
`Certified English Translation of Japanese Publication No. SHO 63-
`181355 ("Ono")
`Power of Attorney
`Japanese Application No. 2001-029587
`Japanese Publication No. P2000-98909A
`Japanese Publication No. HEI 2-189922
`Japanese Publication No. SHO 63-181355
`
`1009
`1010
`
`1012
`1013
`1014
`1015
`1016
`
`
`
`ATTACHMENT A: CV of Dr. Yue Kuo
`
`
`
`ii
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`
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`I.
`
`INTRODUCTION AND BACKGROUND
`
`1.
`
`I have been retained by counsel for Shenzhen China Star
`
`Optoeletronics Technology Co., Ltd. (“CSOT” or “Petitioner”), and asked to
`
`review and provide my opinion on the patentability of claims 1, 3, 5-9, 11, and 14-
`
`17 of U.S. Patent 6,689,629 C1 (Ex. 1001, “the ’629 Patent”). I am being
`
`compensated for my time at my normal consulting rate of $450 per hour. My
`
`compensation is not contingent on the outcome of this proceeding or the content of
`
`my opinions.
`
`2.
`
`I am the Dow Professor of Chemical Engineering with a joint
`
`appointment in Electrical Engineering and Materials Science and Engineering, at
`
`Texas A&M University. I received my B.S. (1974) from National Taiwan
`
`University and M.S. (1978) and Dr. Eng. Sci. (1979) from Columbia University.
`
`3.
`
`I spent about 20 years at the IBM T. J. Watson Research Center,
`
`Yorktown Heights, NY, Semiconductor Division of Data General in Silicon
`
`Valley, etc. as well as 17 years at Texas A&M University. My research has been
`
`focused on device fabrication processes with understanding of materials and
`
`physics of ICs and thin film transistors (TFTs) for LCDs. My research results and
`
`inventions have been used in numerous worldwide productions.
`
`4.
`
`I am the editor and co-author of the following textbooks:
`
`
`
`1
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`i.
`
`Thin Film Transistors: Materials and Processes Volume 1:
`
`Amorphous Silicon Thin Film Transistors; and
`
`ii.
`
`Thin Film Transistors: Materials and Processes Volume 2:
`
`Polycrystalline Silicon Thin Film Transistors.
`
`These textbooks were published by Kluwer Academic Publishers on
`
`February 1, 2004 and have been widely used in universities and industry
`
`worldwide.
`
`5.
`
`I have authored over 400 papers, hold 11 patents and more than 40
`
`invention disclosures, mostly on TFT technologies. Many of my papers have been
`
`highly cited, downloaded, and awarded, such as the #1 most cited papers in ECS
`
`Trans., Jpn. J. Appl. Phys., J. Vac. Sci. Technol. B, J. Appl. Phys., Appl. Phys.
`
`Lett., Microelectronics Reliability, AIP/APS Virtual J. Nanoscale Sci. and
`
`Technol., Virtual J. Biological Phys. (7 times), IIE Trans., IEEE Spectrum, and
`
`IEEE EDS News Letters. I edited 30 journals and conference proceedings, two
`
`TFT textbooks, and 3 short course books.
`
`6.
`
`I have been honored with the following awards and appointments:
`
`Gordon E. Moore Medal of Solid State Science and Technology by
`
`Electrochemical Society (ECS), Fellow of IEEE, Fellow of ECS, ECS Electronics
`
`and Photonics award, Distinguished Research Achievement Award of Texas A&M
`
`University, Innovation Award of Texas A&M University System, 10 IBM awards,
`
`
`
`2
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
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`honorary professorships, 160 plenary, keynote, and invited speeches in
`
`international conferences, universities, and R&D centers, numerous best/most
`
`downloaded/highlighted/ awarded papers, etc. I served on advisory and review
`
`boards, and panels for US National Academies, industry, universities, and
`
`governments.
`
`7.
`
`I have served in various positions in professional societies, such as
`
`Vice President of ECS, committees, editorial boards, symposium organizers,
`
`chairs, etc. I have organized, chaired, and co-chaired over 90 international
`
`conferences on TFTs, ICs, thin films, and plasma technology. I have been the
`
`founder and key organizer of the world's longest, continuously held TFT
`
`symposium series for 26 years. My ULSIC vs. TFT international conference
`
`celebrated the 10th year anniversary in 2015. I have consulted for semiconductor
`
`companies and advised PhD students in American, European, and Asian
`
`universities.
`
`8. My Thin Film Nano & Microelectronics Research Laboratory is
`
`dedicated to interdisciplinary research and education. This laboratory is an
`
`incubator for training young talents and also a venue for hosting seminars
`
`delivered by leading researchers. Over 57 PhD, MS, BS students, postdoctoral, and
`
`visiting researchers have graduated from my laboratory.
`
`
`
`3
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`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`9. While teaching at Texas A&M University, I also formed my own
`
`consulting company, Y. K. Associates. My work for Y.K. Associates generally
`
`involves technical and commercial matters related to intellectual property.
`
`10. A more complete summary of my experience, expertise, and
`
`publications is set forth in my CV, which is attached as Attachment A to this
`
`Declaration.
`
`II.
`
`SUMMARY OF MY OPINIONS
`
`11.
`
`It is my opinion that claims 1, 3, 5-9, 11, and 14-17 of the '629 Patent
`
`are unpatentable. My opinions are based on my expertise in the technology of the
`
`'629 Patent at the time the application was filed, as well as my review of the '629
`
`Patent, its file history, and the prior art provided by the Petitioner. If the patent
`
`owner is allowed to submit additional evidence pertaining to the validity of the
`
`'629 Patent, I intend to review that as well and update my analysis and conclusions
`
`as appropriate and allowed under the rules of this proceeding.
`
`A.
`
`12.
`
`Instructions
`
`I am not an attorney. My analysis and opinions are based on my
`
`expertise in this technical field, as well as the instructions I have been given by
`
`counsel for the legal standards relating to patentability.
`
`13. The materials I have revised in connection with my analysis include
`
`the '629 Patent, its file history, and the cited references and exhibits.
`
`
`
`4
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
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`14.
`
`I understand that unpatentability in this proceeding must be proven by
`
`a preponderance of the evidence, and this is the standard I have used throughout
`
`my declaration. Further, I understand that each patent claim is considered
`
`separately for purposes of unpatentability.
`
`15. My analysis assumes that a "person having ordinary skill in the art,"
`
`or "PHOSITA," at the time of the alleged invention would have had at least a
`
`bachelor's degree in electrical engineering, chemical engineering, physics,
`
`materials science and/or engineering, or other similar technology, and at least two
`
`years of experience in transistor structure design, fabrication, and/or analysis.
`
`16.
`
`I am informed that a patent claim is unpatentable as "anticipated" if
`
`each and every feature of the claim is found in a single prior art reference, it would
`
`have been obvious to a PHOSITA at the time of the invention, taking into account:
`
`i.
`
`ii.
`
`the scope and content of the prior art;
`
`the difference between the prior art and the claim under
`
`construction; and
`
`iii.
`
`the level of ordinary skill in the art.
`
`17.
`
`I am informed that legal principles regarding unpatentability of a
`
`claim due to obviousness have been addressed by the U.S. Supreme Court. I am
`
`informed that, while not absolute, the principles relating to a “motivation,”
`
`"suggestion," or "teaching" in the prior art to combine references are useful in
`
`
`
`5
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`analyzing whether an invention is obvious. I am informed that the suggestion or
`
`motivation may be either explicit or implicit, and may come from knowledge
`
`generally available to a PHOSITA, from the nature of the problem to be solved, or
`
`from a combination of these factors. The test for an implicit motivation,
`
`suggestion, or teaching is what the combined teachings, knowledge of a
`
`PHOSITA, and the nature of the problem to be solved as a whole would have
`
`suggested to those of ordinary skill in the art. The problem examined is not the
`
`specific problem solved by the invention, but the general problem that confronted
`
`the inventor before the invention was made.
`
`18.
`
`I am further informed that the U.S. Supreme Court has clarified that
`
`additional principles may also be applied in such an analysis. Some of those
`
`principles are set forth below.
`
`19. As I understand it, it is no longer always required to present evidence
`
`of an explicit teaching, suggestion, or motivation to combine prior art references
`
`for purposes of determining whether an invention is obvious. Prior art can be
`
`combined based on an express teaching, suggestion, or motivation from the prior
`
`art itself, or from a reasoned explanation of an expert or other witness.
`
`20. A patent claim composed of several elements, however, is not proved
`
`obvious merely by demonstrating that each of its elements was, independently,
`
`known in the prior art. In order to prove obviousness, it must be shown that the
`
`
`
`6
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`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`improvement is not more than the predictable use of prior-art elements according
`
`to their established functions. To determine whether there was an apparent reason
`
`to combine the known elements in the way a patent claims, it will often be
`
`necessary to look to interrelated teachings of multiple pieces of prior art, to the
`
`effects of demands known to the design community or present in the marketplace,
`
`and to the background knowledge possessed by a PHOSITA. Also, in determining
`
`obviousness, one must be aware of the distortion caused by hindsight bias and be
`
`cautious of arguments relying upon hindsight reasoning. An obviousness argument
`
`cannot be sustained by mere conclusory statements. Instead, it must be some
`
`articulated reasoning with some rational underpinnings to support the legal
`
`conclusion of obviousness.
`
`21.
`
`In an obviousness analysis, it is my understanding that there are
`
`“secondary considerations” that should be analyzed if they apply. I am told that
`
`these considerations include (a) whether the prior art teaches away from the
`
`claimed invention, (b) whether there was a long felt but unresolved need for the
`
`claimed invention, (c) whether others tried but failed to make the claimed
`
`invention, (d) skepticism of experts, (e) whether the claimed invention was
`
`commercially successful, (f) whether the claimed invention was praised by others,
`
`and (g) whether the claimed invention was copied by others.
`
`
`
`7
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`
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`22.
`
`I have also been instructed that in the instant Inter Partes Review
`
`("IPR"), claims are given their ordinary and customary meaning, as understood by
`
`a PHOSITA at the time of the invention, taking into consideration the language of
`
`the claims, the specification, and the prosecution history of record construed in
`
`light of how a PHOSITA would understand the claims. I have also been informed
`
`that the Board construes claims during IPR according to the “broadest reasonable
`
`interpretation” in view of the specification to the PHOSITA. Therefore, it is my
`
`understanding that what is to be considered includes the claims, the patent
`
`specifications and drawings, and the prosecution history, including any art listed by
`
`the Examiner or the Applicant. It is my understanding that information external to
`
`the patent, including expert and inventor testimony and unlisted prior art, are to be
`
`considered in construing the claims only if ambiguities remain. However, expert
`
`testimony may be useful in helping to explain the technology. In my analysis, I
`
`have considered and applied the proposed claim constructions of the Petitioner,
`
`unless otherwise indicated.
`
`23.
`
`I have been informed that for product, device, or apparatus claims, the
`
`method of making the product, device, or apparatus is irrelevant to the patentability
`
`of the claimed structure. I am informed that this is also the law for "product-by-
`
`process" claims. Thus, if a claim is directed to a product that is made by a certain
`
`
`
`8
`
`
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`process, the aspects of the claim that deal with the process are not given patentable
`
`weight.
`
`B.
`
`24.
`
`Effective Filing Dates and Prior Art Patents and Printed
`
`Publications
`
`I am informed that the Petitioner relies upon the following patents and
`
`publications, none of which was considered during the prosecution of the ’629
`
`Patent, and all of which I understand are prior art to all claims of the ’629 Patent:
`
`25. Ex. 1005 – Japanese Publication No. P2000-98909A (“Noda”),
`
`published on April 7, 2000.
`
`26. Ex. 1006 – Low Resistance Gate Line for High-Resolution TFT/LCD
`
`Display ("Tsujimura"), published on October 10-13, 1994.
`
`27. Ex. 1007 - U.S. Patent No. 5,546,013 ("Ichioka"), published on
`
`August 13, 1996.
`
`28. Ex. 1008 - Japanese Publication No. HEI 2-189922 ("Shimizu"),
`
`published on July 25, 1990.
`
`29. Ex. 1009 - U.S. Patent No. 2,990,282 ("Wicke"), published on June
`
`27, 1961.
`
`30. Ex. 1010 - Japanese Publication No. SHO 63-181355 ("Ono"),
`
`published on July 26, 1988.
`
`31. The chart below summarizes my conclusions of unpatentability.
`
`
`
`9
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`
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`Ground '629 Patent Claims
`
`Basis for Rejection:
`
`1
`
`1, 3, 5-6, 9, 11, 14, and
`
`Obviousness: Noda, Applicants' Admitted
`
`17
`
`Prior Art (AAPA), Tsujimura, Ichioka, and
`
`Shimizu
`
`2
`
`7-8 and 15-16
`
`Obviousness: Noda, AAPA, Tsujimura,
`
`Ichioka, Shimizu, and Wicke
`
`3
`
`1, 9, and 17
`
`Obviousness: Noda, AAPA, Tsujimura,
`
`Ichioka, and Ono
`
`III. OVERVIEW OF THE TECHNOLOGY
`
`32. The '629 Patent is directed to a TFT array layout for a display and a
`
`method for forming the same. The '629 Patent focuses on the use of larger dummy
`
`conductive patterns 29 between connection pads 25 and 27.
`
`33.
`
`In FIGS. 2 and 5C of the '629 Patent, below, an array substrate
`
`includes an insulating substrate 1 (pink), a TFT array (TFTs 21) on the insulating
`
`substrate 1, and a plurality of wirings 2 (grey) (scan lines 23 and signal lines 24) on
`
`the insulating substrate 1, each wiring 2 having a first end, each wiring 2 in
`
`communication with at least one transistor (the TFT 21) in the thin film array, and
`
`at least one of the wirings 2 having an upper layer and a lower layer of conductive
`
`materials. See Ex. 1003 at FIGS. 2 and 5A-5C, 4:42-67, 5:1-10, 6:17-55.
`
`
`
`10
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`FIG. 5
`
`
`
`34. The array substrate further includes a plurality of connection pads 25
`
`and 27 (blue), each connection pad 25 or 27 contacting a first end of at most one of
`
`the plurality of wirings 2. The array substrate further includes a plurality of pixel
`
`electrodes 22 (green) and a plurality of dummy conductive patterns 29 (red) on the
`
`insulating substrate 1, the plurality of dummy conductive patterns 29 including at
`
`least about 30% of an area of the insulating substrate 1 between the connection
`
`pads 25 and 27 and the pixel electrodes 22, and the dummy conductive patterns 29
`
`being not in contact with any of the wirings 2. See Ex. 1003 at FIGS. 2 and 5A-
`
`5C, 4:42-67, 5:1-10, 5:29-42, 6:17-55.
`
`35. According to the '629 Patent, the dummy conductive patterns 29 have
`
`a wiring density of at least 30%. See Ex. 1003 at 6:7-13, 5:55-67, 6:1-6. By
`
`keeping the wiring density of the dummy conductive patterns 29 above 30%, the
`
`
`
`11
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`
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`effect of "undercutting" during etching can be reduced, and a gentler taper of the
`
`wiring 2 can be formed. See Ex. 1003 at 5:29-42, 7:8-18, FIG. 8.
`
`36. Claims 3 and 11 specify that the lower layer wiring material is
`
`selected from the group consisting of aluminum and aluminum alloys.
`
`A.
`
`Summary of the Prosecution History of the '629 Patent
`
`37. The '629 Patent issued on November 14, 2014, from Reexamination
`
`Request No. 90/009,697 ("the '697 Reexamination") filed on March 16, 2010. The
`
`original U.S. Application No. 10/068,500 ("the '500 Application") was filed on
`
`February 5, 2002, and issued as U.S. Patent No. 6,689,629 B2 Patent on February
`
`10, 2004, and claimed priority from Japanese Application No. 2001-029587 filed
`
`February 6, 2001. Ex. 1001-1004.
`
`38.
`
`In the '500 Application, an Office Action dated May 29, 2003 was
`
`issued, based on U.S. Patent No. 5,285,301 and U.S. Patent No. 6,163,356. Ex.
`
`1004.117-122. An Amendment was filed on August 29, 2003, in response to the
`
`Office Action, in which the subject matter of claim 2 was incorporated into claim
`
`1, i.e., the feature “the dummy patterns comprises at least about 30% of the area of
`
`the insulating substrate." Ex. 1004.123-130. A Notice of Allowance dated Oct. 1,
`
`2003, was issued. Ex. 1004.131-135.
`
`39. The '629 Patent was assigned from IBM to AUO on December 29,
`
`2009.
`
`
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`12
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`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`40.
`
`In the '697 Reexamination, a Non-Final Office Action dated January
`
`6, 2011, was issued, in which EP Publication No. 0 887 695 and U.S. Patent No.
`
`5,995,189 ("the '189 Patent") are cited as main references and the AAPA in the
`
`'629 Patent is cited as a secondary reference. Ex. 1002.1096-1007. A
`
`Supplemental Amendment was filed on May 18, 2011, in response to the Non-
`
`Final Office Action in which the subject matter of claims 2 and 4 was incorporated
`
`into claim 1, i.e., the feature "at least one of the wirings comprises at least an upper
`
`layer and a lower layer of conductive materials, wherein the upper layer wiring
`
`material is selected from the group consisting of molybdenum, chromium,
`
`tantalum, titanium and alloys thereof." Ex. 1002.1278-1306. A Final Office
`
`Action dated June 6, 2012, was issued, in which the '189 Patent is cited as the main
`
`reference and the AAPA in the '629 Patent is cited as a secondary reference. Ex.
`
`1002.1580-1495. A Supplemental Amendment was filed on September 19, 2012,
`
`in response to the Final Office Action, in which the claims were amended as issued
`
`in the '629 Patent. Ex. 1002.1632-1641. A Notice of Intent to Issue a Reexam
`
`Certificate dated September 26, 2014, was issued. Ex. 1002.1866-1872.
`
`IV. CLAIM CONSTRUCTION
`
`41.
`
`I am informed that a claim subject to IPR is given its “broadest
`
`reasonable construction in light of the specification of the patent in which it
`
`appears.” I am also informed that the words of the claim are given their plain
`
`
`
`13
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`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`meaning from the perspective of one of ordinary skill in the art unless that meaning
`
`is inconsistent with the specification.
`
`42.
`
`I am informed that the Petitioner has proposed definitions for the
`
`following terms.
`
`A.
`
`43.
`
`"a plurality of dummy conductive patterns on the insulating
`substrate" (claims 1, 9, and 17)
`
`I have applied the interpretation of this phrase, which is found in
`
`independent claims 1, 9, and 17 of the '629 Patent, as "conductive material
`
`disposed on an insulating substrate and not contacting any wirings." See Ex. 1003
`
`at FIGS. 2 and 5A-5C, 5:29-42, 6:17-55.
`
`B.
`
`44.
`
`"wherein the plurality of dummy conductive patterns comprises
`at least about 30% of an area of the insulating substrate between
`the connection pads and the pixel electrodes" (claims 1, 9, and 17)
`
`I have applied the interpretation of this phrase, which is found in
`
`independent claims 1, 9, and 17 of the '629 Patent, as that "the area covered by the
`
`dummy conductive patterns covers 30% or more of a region between the
`
`connection pads and pixel electrodes." For example, the '629 Patent refers to this
`
`concept as the "wiring density" and states that "the term 'wiring density' refers to
`
`an area ratio of an area of portions where the signal lines, the scan lines, the
`
`drawing lines, and the dummy conductive patterns are formed [to] an area of a
`
`specific region where the dummy conductive patterns are formed." Ex. 1003 at
`
`5:55-67, 6:1-6.
`
`
`
`14
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`V. ANALYSIS
`
`A. Ground 1: Claims 1, 3, 5-6, 9, 11, 14, and 17 are obvious under
`
`35 U.S.C. § 103 in view of Noda, AAPA, Tsujimura, Ichioka, and
`
`Shimizu.
`
`45.
`
`In my opinion, the combination of the teachings in Noda, the AAPA,
`
`Tsujimura, Ichioka, and Shimizu taught all of the features of claims 1, 3, 5-6, 9, 11,
`
`14, and 17. For example, claim 1 recites:
`
`An array substrate for display, comprising:
`an insulating substrate;
`a thin film transistor array on the insulating
`substrate;
`a plurality of wirings on the insulating substrate,
`each wiring having a first end, each wiring in
`communication with at least one transistor in the thin
`film array, and at least one of the wirings comprising at
`least an upper layer and a lower layer of conductive
`materials, wherein the upper layer wiring material is
`selected from the group consisting of molybdenum,
`chromium, tantalum, titanium and alloys thereof;
`a plurality of connections pads, each connection
`pad contacting the first end of at most one of the plurality
`of wirings;
`a plurality of pixel electrodes; and
`a plurality of dummy conductive patterns on the
`insulating substrate, wherein the plurality of dummy
`conductive patterns comprises at least about 30% of an
`area of the insulating substrate between the connection
`pads and the pixel electrodes, and the dummy conductive
`patterns are not in contact with any of the wirings.
`
`46. Noda is directed to a polysilicon-typed TFT mode active matrix liquid
`
`
`
`15
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`crystal device (see Ex. 1005 at ¶¶ [0001]-[0002]), which is an array substrate as in
`
`the display of the '629 Patent. In my opinion, Noda expressly taught most of the
`
`features of the 12 claims of the '629 Patent. In addition to the features squarely
`
`taught by Noda, other features were already well-known and would have been
`
`obvious to use in view of the AAPA, Tsujimura, Ichioka, and Shimizu.
`
`47.
`
`Independent claims 1, 9, and 17 include "an insulating substrate," "a
`
`thin film transistor array on the insulating substrate," and "a plurality of pixel
`
`electrodes." In my opinion, Noda taught these features.
`
`48. Referring to FIG. 5 reproduced below, Noda taught that (emphasis
`
`added) "[p]ixel electrodes [12] [green] formed by ITO are provided in a matrix
`
`shape on a transparent insulating substrate of a TFT array side substrate 11
`
`which constitutes a polysilicon-typed TFT active-matrix liquid crystal display."
`
`Ex. 1005 at Abstract, FIG. 5. Thus, in my opinion, Noda taught the claimed
`
`insulating substrate, thin film transistor array, and plurality of pixel electrodes.
`
`
`
`16
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`FIG. 5
`
`49.
`
`Independent claims 1, 9, and 17 include "a plurality of dummy
`
`
`
`conductive patterns on the insulating substrate, wherein … the dummy conductive
`
`patterns are not in contact with any of the wirings." The use of dummy patterns
`
`(i.e., conductive material that is not in contact with the wirings) to increase wiring
`
`density and thereby reduce undercut effects of etching, was well-known prior to
`
`2001 as taught by Noda for example.
`
`50. Referring to FIG. 5 reproduced above, Noda taught (emphasis added):
`
`[I]t may be a shape that surrounds the periphery of
`the pixel electrode 12 as a set of the dummy films 5a
`[red] having a shape cut corresponding to the shape of
`the pixel electrodes 12. The dummy films are provided
`to the same substrate end side with the pixel electrodes
`12 on the transparent insulating substrate 11a so as to
`surround the periphery of the pixel electrodes 12 … .
`Further, the dummy film 5 … may be formed of other
`materials such as Al (aluminum), Cr (chromium) and
`the like.
`
`
`
`17
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`Ex. 1005 at ¶¶ [0032]-[0033], FIG. 5. Aluminum and chromium are conductive.
`
`Also, as shown in FIG. 5, the dummy films 5a are not in contact with any of the
`
`wirings, i.e., drain wires DL and gate lines GL. Thus, in my opinion, Noda taught
`
`the claimed plurality of dummy conductive patterns.
`
`51.
`
`Independent claims 1, 9, and 17 include "a plurality of wirings on the
`
`insulating substrate, each wiring having a first end, each wiring in communication
`
`with at least one transistor in the thin film array, and at least one of the wirings
`
`comprising at least an upper layer and a lower layer of conductive materials,
`
`wherein the upper layer wiring material is selected from the group consisting of
`
`molybdenum, chromium, tantalum, titanium and alloys thereof." These features
`
`were also well-known, as taught by Noda, the AAPA, and Tsujimura.
`
`52. For example, referring again to FIG. 5, Noda taught that (emphasis
`
`added) "[i]n the TFT array side substrate 11 … the pixel electrode 12 of each of
`
`the display pixels constituting the liquid crystal display is pattern-formed in the
`
`vicinity of the intersection points of the drain wires DL connected to the drain
`
`driver and the gate lines GL connected to the gate driver." Ex. 1005 at ¶ [0024],
`
`FIG. 5. Also, as shown in FIG. 5, the drain wires DL and the gate lines GL are
`
`connected to TFTs of the TFT array side substrate 11 via contact holes 13. See Ex.
`
`1005 at ¶ [0025], FIG. 5. Thus, in my opinion, Noda taught the claimed plurality
`
`of wirings on the insulating substrate, each wiring having a first end (connected to
`
`
`
`18
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`the drain driver or the gate driver), and each wiring in communication with at least
`
`one transistor in the thin film array.
`
`53. As the patent applicant admitted in the AAPA, it was well-known to
`
`use "wiring using aluminum is constituted as a two-layer structure, in which
`
`aluminum is used as a lower conductive material, and a material harder to be
`
`oxidized than aluminum such as chromium, tantalum, titanium or molybdenum
`
`is used as an upper conductive material." Ex. 1003 at 1:33-38; 2:1-6. I agree
`
`with the AAPA that it was well-known to have at least one of the claimed wirings
`
`comprising at least the upper layer and the lower layer of conductive materials,
`
`wherein the upper layer wiring material is selected from the group consisting of
`
`molybdenum, chromium, tantalum, titanium and alloys thereof. Id.
`
`54. Consistent with the AAPA, it is my opinion that Tsujimura also taught
`
`that it was well-known to employ the claimed two-layer structure of wirings:
`
`"Fig.1 shows the cross section of our gate line structure. As Al makes hillocks or
`
`blisters at high temperature, we must make a multi-layer structure using high-
`
`melting point metal Mo … on Al." Ex. 1006 at page 424, column 1, last
`
`paragraph, page 424, column 2, first paragraph (emphasis added), FIG. 1. Thus,
`
`Tsujimura also taught at least one of the claimed wirings comprising at least the
`
`upper layer and the lower layer of conductive materials, wherein the upper layer
`
`
`
`19
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`wiring material is selected from the group consisting of molybdenum, chromium,
`
`tantalum, titanium and alloys thereof.
`
`55.
`
`Independent claims 1, 9, and 17 include "a plurality of connections
`
`pads, each connection pad contacting the first end of at most one of the plurality of
`
`wirings." In my opinion, Ichioka shows that these connection pads were also well-
`
`known and commonplace.
`
`56. While the drivers of Noda must include connection pads to connect
`
`the drivers to the respective wires, referring to FIG. 2 reproduced below, Ichioka
`
`expressly taught these connection pads: "[e]ach data line terminates in a data
`
`line electrode or data line pad 22 [blue]. Also formed on substrate 10 are a large
`
`number of gate lines 24 each terminating in a gate line electrode or a gate line
`
`pad 26 [blue]." Ex. 1007 at 3:21-29 (emphasis added), FIG. 2. Thus, Ichioka
`
`taught the need for connection pads.
`
`
`
`20
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`
`
`57.
`
`Independent claims 1, 9, and 17 include "wherein the plurality of
`
`dummy conductive patterns comprises at least about 30% of an area of the
`
`insulating substrate between the connection pads and the pixel electrodes." In my
`
`opinion, Shimizu taught that covering this much area or more was advantageous to
`
`reduce undercutting effects (emphasis added):
`
`[T]he shape of the aluminum film 3 obtained by
`etching is greatly influenced by the pattern density of the
`photoresist film 7 (the ratio of the area occupied by the
`photoresist film toward the area of the wafer), and side
`etching and undercut occur more easily as the pattern
`density becomes small.
`
`Ex. 1008 at page 2, lines 22-25, FIGS. 3A, 3B, and 4.
`
`
`
`21
`
`
`
`Declaration of Yue Kuo, Dr.Eng.Sci.
`U.S. Patent No. 6,689,629 C1
`
`FIG. 1A
`
`FIG. 1B
`
`58.
`
`
`
`Shimizu further taught (emphasis added):
`
`[A]s shown in Fig. 1 (a) [reproduced above],
`aluminum film 3 is formed on all over the surface of
`silicon oxide film 2 which has been grown on the surface
`of semiconductor substrate 1 [pink], and thereon
`photoresist film 4 in formed by patterning. Here, the
`photoresist film 4 forms dummy pattern 4b in the part
`which is essentially unnecessary, in addition to pattern 4
`which is necessary
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