UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________
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`
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`LAM RESEARCH CORP.,
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`Petitioner
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`v.
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`DANIEL L. FLAMM,
`
`Patent Owner
`___________
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`U.S. Patent No. RE40,264 E
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`Issued: April 29, 2008
`
`Named Inventor: Daniel L. Flamm
`
`Title: MULTI-TEMPERATURE PROCESSING
`___________
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`DECLARATION OF JOSEPH L. CECCHI IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW OF U.S. PATENT NO. RE40,264 E
`UNDER 37 C.F.R. § 1.68
`
`DECLARATION FOR SIXTH PETITION
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`Mail Stop: PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`TABLE OF CONTENTS
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`Page
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`I. 
`
`II. 
`
`III. 
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`IV. 
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`V. 
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`VI. 
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`
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`INTRODUCTION ....................................................................................... 1 
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`QUALIFICATIONS AND PROFESSIONAL EXPERIENCE .................. 1 
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`PERSON HAVING ORDINARY SKILL IN THE ART ........................... 9 
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`PRIORITY DATE OF THE '264 PATENT .............................................. 11 
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`A. 
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`B. 
`
`C. 
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`Independent Claim 27 ...................................................................... 11 
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`Independent Claim 37 ...................................................................... 12 
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`The Continuation-In-Part Provisional Application No.
`60/058,650 Disclosure Filed September 11, 1997 ........................... 13 
`
`1. 
`
`2. 
`
`Etching the Film (cl. 27) or Film Treatment (cl. 37) at
`the Selected First Temperature, Changing to a
`Selected Second Temperature, and Etching (cl. 27) or
`Film Treatment (cl. 37) at the Selected Second
`Temperature .......................................................................... 13 
`
`Using a Measured Substrate Temperature (cl. 27) or a
`Control Circuit and Substrate Temperature Sensor (cl.
`37) ......................................................................................... 14 
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`D.  Disclosure of Parent Application No. 09/151,163 Filed Dec.
`4, 1995 .............................................................................................. 15 
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`RELEVANT LEGAL STANDARDS ....................................................... 19 
`
`THE '264 PATENT ................................................................................... 22 
`
`A. 
`
`B. 
`
`Representative Claim 37 .................................................................. 23 
`
`The '264 Patent Disclosure ............................................................... 24 
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`1. 
`
`Multi-Temperature Etching .................................................. 24 
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`Page
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`2. 
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`3. 
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`4. 
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`Substrate Holder and Heat Transfer Device ......................... 25 
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`Temperature Sensor .............................................................. 25 
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`Control System ..................................................................... 25 
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`VII.  TECHNICAL BACKGROUND ............................................................... 26 
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`VIII.  OPINIONS RELATING TO EACH OF THE GROUNDS ...................... 29 
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`A.  Ground 1: Claims 27-29, 31-46, 50, 66, and 67 are Rendered
`Obvious by Kadomura in View of '485 Wang and Kawamura
`under 35 U.S.C. § 103(a) .................................................................. 29 
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`1. 
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`2. 
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`3. 
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`4. 
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`5. 
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`6. 
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`7. 
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`8. 
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`9. 
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`Kadomura in View of '485 Wang and Kawamura
`Teaches All the Limitations of Independent Claim 27 ......... 29 
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`Chart for Claim 27 ................................................................ 36 
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`Kadomura in view of '485 Wang and Kawamura
`Teaches All the Limitations of Dependent Claims 28-
`29, 31-36, 66 ......................................................................... 40 
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`Chart for Claims 28-29, 31-36, and 66 ................................. 46 
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`Kadomura in View of '485 Wang and Kawamura
`Teaches All the Limitations of Independent Claim 37 ......... 48 
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`Chart for Claim 37 ................................................................ 54 
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`Kadomura in View of '485 Wang and Kawamura
`Teaches All the Limitations of Dependent Claims 38-
`46, 50, and 67 ........................................................................ 56 
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`Chart for Claims 38-46, 50, and 67 ...................................... 64 
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`Reasons for Combinability for Claims 27-29, 31-46,
`50, 66, and 67 ........................................................................ 65 
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`Page
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`B. 
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`Ground 2: Kadomura in View of '485 Wang, Kawamura, and
`Tegal Teaches All the Limitations of Dependent Claims 30
`and 49 ............................................................................................... 68 
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`1. 
`
`2. 
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`Chart for Claims 30 and 49 ................................................... 68 
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`Reasons for Combinability for claims 30 and 49 ................. 69 
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`C. 
`
`Ground 3: Kadomura in View of EP Wang and Kawamura
`Teaches All the Limitations of Claims 37, 47, and 48 ..................... 69 
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`1. 
`
`2. 
`
`Chart for Claims 37, 47, and 48 ............................................ 72 
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`Reasons for Combinability for claims 37, 47, and 48 .......... 74 
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`IX. 
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`CONCLUSION ......................................................................................... 76 
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`I, Joseph L. Cecchi, declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`
`I am over 18 years of age and otherwise competent to make this
`
`Declaration.
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`2.
`
`I have been asked to provide my views regarding technical issues in
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`connection with the above-captioned inter partes review of U.S. Patent No.
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`RE40,264 E ("the '264 patent"). I opine only with respect to certain issues that are
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`discussed in this declaration.
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`II. QUALIFICATIONS AND PROFESSIONAL EXPERIENCE
`3.
`I am currently Dean of the School of Engineering and Professor of
`
`Chemical and Biological Engineering at the University of New Mexico ("UNM").
`
`This is my second term as Dean, and the term began in February 2014. I have held
`
`my appointment as Professor since joining UNM in 1994. I also serve
`
`concurrently as Associate Provost for National Laboratory Relations.
`
`4.
`
`From 2011 to 2012, while on leave from UNM, I served as Provost
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`and Professor of Engineering at the Masdar Institute of Science and Technology in
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`Abu Dhabi, United Arab Emirates.
`
`5. My first appointment as Dean of the School of Engineering extended
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`from 2000 to 2009. From 2004 to 2011, I was Chair of the Board of Directors of
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`the Science and Technology Corp. at UNM, the university's technology transfer
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`organization responsible for patenting and licensing UNM's intellectual property. I
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`currently serve as Vice Chair of the Science and Technology Corp. at UNM.
`
`6.
`
`From 1994 until 2000, I was Chair of the Department of Chemical and
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`Nuclear Engineering at UNM. Previously, I was a Lecturer with the rank of
`
`Professor in the Department of Chemical Engineering at Princeton University,
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`where I also directed the Graduate Program in Plasma Science and Technology. I
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`was associated with the Plasma Physics Laboratory at Princeton University for
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`twenty-one years, as leader of the Plasma Processing Group (1987-1994); Principal
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`Research Physicist (1984-1994); leader of the Materials Physics Group (1979-
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`1987); Research Physicist (1978-1984); and Staff Physicist (1972-1978).
`
`7.
`
`From 1991 to 1994, I was Director of the New Jersey SEMATECH
`
`Center of Excellence for Plasma Etching. This organization, which involved four
`
`universities and one industrial laboratory, was engaged in state-of-the-art research
`
`in plasma processing for semiconductor manufacturing.
`
`8.
`
`From 1992 to 2001, I worked on three committees established by the
`
`Semiconductor Industry Association ("SIA") to generate technology "roadmaps"
`
`for semiconductor manufacturing. Most recently, from 1998 to 2000, I was a
`
`member of the Interconnect Technical Working Group ("TWG") for the SIA
`
`International Technology Roadmap for Semiconductors ("ITRS").
`
`9.
`
`I obtained my Ph.D. in physics from Harvard University in 1972. I
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`also received a Master's degree in physics from Harvard University in 1969, a
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`Bachelor's degree in physics from Knox College in 1968, and a Master's of
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`Business Administration (MBA) degree from the University of New Mexico in
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`2011.
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`10.
`
`I have had significant research experience in a number of areas
`
`pertaining to semiconductor devices and their manufacturing, including plasma
`
`physics, plasma chemistry, plasma etching, plasma enhanced chemical vapor
`
`deposition (PECVD), atomic layer deposition (ALD), which is a form of chemical
`
`vapor deposition, plasma-assisted ALD, and chemical-mechanical-polishing
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`(CMP), sometimes called "chemical-mechanical-planarization".
`
`11.
`
`I have published over ninety papers in my fields of expertise. Among
`
`the eight United States patents on which I am an inventor and an additional patent
`
`application for which the claims have been allowed, the following six patents are
`
`in the area of plasma technology for manufacturing semiconductors and other
`
`materials:
`
` "Method and Apparatus for Coupling a Microwave Source in an
`
`Electron Cyclotron Resonance System," U.S. Patent No.
`
`5,111,111, issued September 30, 1991;
`
` "Apparatus and Method for Uniform Microwave Plasma
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`Processing Using TE11 and TM01 Modes," U.S. Patent No.
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`5,302,803, issued April 12, 1994;
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` "Apparatus and Process for Producing High Density Axially
`
`Extended Plasmas," U.S. Patent No. 5,587,038, issued
`
`December 24, 1996;
`
` "Method of Making Dense, Conformal, Ultra-Thin Cap layers
`
`for Nanoporous Low-k ILD by Plasma Assisted Atomic Layer
`
`Deposition," U.S. Patent No. 7,947,579, issued May 24, 2011;
`
`and
`
` "Ultra-Thin Microporous/Hybrid Materials," U.S. Patent No.
`
`8,187,678, issued May 29, 2012.
`
` “Enzymatically Active High-Flux Selectively Gas-Permeable
`
`Membranes,” U.S. Patent Application No.: 14/215,962, Claims
`
`Allowed, September 29, 2015.
`
`12.
`
`I have been elected as a fellow in AVS, The Society for the Science
`
`and Technology of Materials, Interfaces, and Processing.
`
`13.
`
`I am aware of research and development activities ongoing in
`
`semiconductor manufacturing and devices since the 1980s time frame. As a result
`
`of my research experience in the plasma etching, deposition, and CMP areas, I am
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`also familiar with other silicon semiconductor process technologies that directly
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`impact these areas, including such things as lithography and cleaning techniques.
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`14. As a professor, I have taught courses in silicon semiconductor devices
`
`and process technology at undergraduate and graduate levels. Many of the
`
`students I have taught have gone on to work for companies engaged in
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`semiconductor manufacturing. I have supervised the research of a number of
`
`students in semiconductor manufacturing as part of their work for their M.S. and
`
`Ph.D. degrees.
`
`15. My curriculum vitae (CV) (Exhibit 1010) includes additional details
`
`about my experience and professional background.
`
`16. The '264 patent generally relates to "plasma processing" (Ex. 1001,
`
`1:18), with specific applications to plasma etching, plasma assisted chemical vapor
`
`deposition, and materials that include silicon, silicon dioxide, silicon nitride,
`
`polysilicon, and others. Id. at 1:23-31. The specification of the '264 patent also
`
`discloses that "[p]referably, the plasma discharge is derived from the inductively
`
`couple plasma source that is a de-coupled plasma source ('DPS') or a helical
`
`resonator, though other sources can be employed." Id. at 4:4-7.
`
`17.
`
`In my research, I have designed, constructed, and used de-coupled
`
`plasma sources, including inductively coupled plasma sources, helicon plasma
`
`sources, and electron cyclotron plasma (ECR) sources. These sources are also
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`high-density plasma sources. I have used these plasma sources for plasma etching
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`and plasma assisted chemical vapor deposition. For example, publication 74 in my
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`CV (Ex. 1010 at 15), describes a plasma processing apparatus, including an
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`electron cyclotron resonance (ECR) plasma source used for plasma etching of
`
`polysilicon, silicon dioxide and silicon. The plasma processing apparatus, shown
`
`in Figure 1 of this publication, includes an ECR source chamber and a downstream
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`processing chamber. The latter includes a water cooled wafer chuck (or substrate
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`holder) that incorporated Helium at 1-2 Torr pressure between the wafer and the
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`chuck to provide enhanced heat transfer.
`
`18. Publications 75 and 77 in my CV (Ex. 1010 at 15) describe improved
`
`operational characteristics of an ECR plasma etch reactor based on optimizing the
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`coupling of the microwave power to the plasma. The optimized coupling reduces
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`the reflected power to less than 5% of the incident power without external tuning,
`
`simplifying control of the plasma operation. This work underpins U.S. Patent,
`
`5,111,111, on which I am co-inventor.
`
`19. Publication 78 and 79 in my CV (Ex. 1010 at 15) describe a method
`
`for producing more uniform plasmas in ECR plasma etch reactors. This work
`
`includes results of etching a photoresist patterned, n-doped polysilicon layer
`
`deposited over an oxide layer on a silicon wafer, using an SF6/Ar gas mixture. An
`
`important result is that the polysilicon etch rate uniformity across the wafer was
`
`correlated with the plasma uniformity. When the plasma uniformity was
`
`maximized, the polysilicon etch rate across the wafer was uniform to within about
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`2%.
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`20. Publication 81 in my CV (Ex. 1010 at 15) describes a method for
`
`providing independent radio frequency (rf) wafer biasing on the wafer chuck in a
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`manner that produces more uniform ion bombardment across substrates being
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`processed. This work shows that using a lower rf frequency for wafer biasing
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`results in a more uniform distribution of ion bombardment across the wafer.
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`21. Publication 88 in my CV (Ex. 1010 at 16) addresses a critical issue of
`
`using an inductively couple plasma (ICP) source to etch silicon dioxide with high
`
`selectivity to silicon. Selectivity is achieved by introducing gas mixtures
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`containing C, F, and H into the plasma source, which dissociates the feedstock
`
`gases to produce fluorocarbon radicals that deposit a polymer on the wafer surface.
`
`The polymer suppresses etch rates of silicon compared to the etch rates of silicon
`
`dioxide, thus promoting selectivity of oxide etching. The wafer chuck in this
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`plasma apparatus was water cooled. Helium at 10 Torr was introduced between
`
`the water cooled chuck and wafer to promote heat transfer. The wafer temperature
`
`was measured using a Luxtron fluoroptic thermometer. Concentrations of the
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`fluorocarbon radicals were measured by diode laser absorption spectroscopy and
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`correlated to measurements of the thickness of the deposited polymer.
`
`22. As further examples, publications 92, 93, and 94 in my CV (Ex. 1010
`
`at 16) relate to a process of plasma-assisted atomic layer deposition, which is a
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`form of plasma-assisted chemical vapor deposition that provides layer-by-layer
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`control of thin film deposition. An inductively coupled plasma source was used in
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`this work. Publications 92 and 93 describe how plasma-assisted atomic layer
`
`deposition of silicon dioxide can be applied to producing a material that can be
`
`used for interlevel dielectrics between conductors in integrated circuits. These
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`plasma processes are also the subject matter in U.S. Patent Nos. 7,947,579 and
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`8,187,678, on which I am an inventor.
`
`23.
`
`I am being compensated for my time at my standard hourly rate of
`
`$450 in connection with this proceeding. My compensation is in no way
`
`contingent upon my performance or the outcome of this case.
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`24.
`
`I have been asked my technical opinions regarding the understanding
`
`of a person of ordinary skill in the art (discussed below) as it relates to the '264
`
`patent and other reference documents.
`
`25.
`
`I have also been asked to provide my technical opinions on concepts
`
`discussed in the '264 patent and other reference documents, as well as my technical
`
`opinions on how these concepts relate to several claim limitations of the '264
`
`patent in the context of the specification.
`
`26.
`
`In reaching the opinions stated herein, I have considered the '264
`
`patent, its prosecution history, and the references listed in the table below, and
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`have also drawn as appropriate upon my own education, training, research,
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`knowledge, and personal and professional experience.
`
`Exhibit
`1001
`
`Description
`U.S. Patent No. RE40,264 (the '264 patent)
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1010
`
`U.S. Patent No. 6,063,710 (Kadomura)
`
`U.S. Patent No. 5,219,485 ('485 Wang)
`
`European Patent Application Number 90304724.9 (Tegal)
`
`U.S. Patent No. 5,892,207 (Kawamura)
`
`European Patent Application Number 87311193.4 (EP Wang)
`
`Continuation-in-Part Provisional Application No. 0/058,650 filed
`Sept. 11, 1997
`
`Parent Application No. 08/567,224 filed Dec. 5, 1995
`
`Curriculum Vitae of Joseph L. Cecchi, Ph.D.
`
`III. PERSON HAVING ORDINARY SKILL IN THE ART
`27.
`I have approached my analysis of the '264 patent from the perspective
`
`of a person having ordinary skill in the art (a PHOSITA) at the time of the
`
`purported invention of the '264 patent. As explained below in Section IV, the
`
`parent application does not disclose numerous limitations of the challenged claims.
`
`Thus, I have been informed that the relevant time of the purported invention is
`
`September 11, 1997, the date of the provisional application to which the '264
`
`patent claims priority.
`
`28.
`
`I have been informed by counsel that a person having ordinary skill in
`
`the art is a hypothetical person who is presumed to have known all of the relevant
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`art at the time of the invention. Factors that may be considered in determining the
`
`level of ordinary skill in the art may include: (1) type of problems encountered in
`
`the art; (2) prior art solutions to those problems; (3) rapidity with which
`
`innovations are made; (4) sophistication of the technology; and (5) educational
`
`level of active workers in the field. I have been informed by counsel that it is from
`
`the viewpoint of a person of ordinary skill in the art that determined patentability.
`
`29. Based on these factors, in my opinion, a person having ordinary skill
`
`in the art of the '264 patent would generally have had either (i) a Bachelor's degree
`
`in engineering, physics, chemistry, materials science, or a similar field, and three
`
`or four years of work experience in semiconductor manufacturing or related fields,
`
`or (ii) a Master's degree in engineering, physics, chemistry, materials science, or a
`
`similar field and two or three years of work experience in semiconductor
`
`manufacturing or related fields.
`
`30. Based on this understanding of a PHOSITA for the '264 patent, I
`
`believe that I am at least a person having ordinary skill in the art for purposes of
`
`the '264 patent. For example, my qualifications and experiences discussed in
`
`Section II above, and in my CV (Ex. 1010), demonstrate my familiarity with and
`
`knowledge of the art of the '264 patent. I therefore believe that I am qualified to
`
`offer this declaration as to how such a person would have interpreted the '264
`
`patent and the prior art on or about September 11, 1997. Unless otherwise stated,
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`my statements below refer to the knowledge, beliefs and abilities of a person
`
`having ordinary skill in the art of the '264 patent at the time of the purported
`
`invention of the '264 patent.
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`IV. PRIORITY DATE OF THE '264 PATENT
`31. The '264 patent is a reissue of U.S. Patent No. 6,231,776 ("the '776
`
`patent"), which issued from Application No. 09/151,163 filed on Sept. 10, 1998
`
`and Provisional Application No. 60/058,650 filed on Sept. 11, 1997 ("the
`
`continuation-in-part provisional application"), which is a continuation-in-part of
`
`Application No. 08/567,224 ("the parent application") filed on Dec. 4, 1995. Ex.
`
`1001. As discussed below, claims 27-50, 66, and 67 were not disclosed and
`
`adequately supported by the parent application.
`
`A.
`Independent Claim 27
`32. Claim 27 recites a method comprising (a) "heating a substrate holder
`
`to a first substrate holder temperature with a heat transfer device, the substrate
`
`holder having at least one temperature sensing unit; (b) "placing a substrate having
`
`a film thereon on a substrate holder within a chamber;" (c) "etching a first portion
`
`of the film at a selected first substrate temperature;" (d) "etching a second portion
`
`of the film at a selected second substrate temperature, the selected second substrate
`
`temperature being different from the selected first substrate temperature;" (e)
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`"wherein substrate temperature is changed from the selected first substrate
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`temperature to the selected second substrate temperature, using a measured
`
`substrate temperature, within a preselected time interval for processing" (f) "and at
`
`least the first substrate temperature or the second substrate temperature, in single or
`
`in combination, is above room temperature." Ex. 1001, 22:10-28.
`
`B.
`Independent Claim 37
`33. Claim 37 recites a method comprising (a) "placing a substrate having
`
`a film thereon on a substrate holder within a chamber of a plasma discharge
`
`apparatus;" (b) "performing a first film treatment of a first portion of the film at a
`
`selected first substrate temperature;" (c) "with the substrate temperature control
`
`circuit, changing from the selected first substrate temperature to a selected second
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`substrate temperature;" and (d) "performing a second film treatment of a second
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`portion of the film at the selected second substrate temperature." Ex. 1001, 22:59-
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`23:14.
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`34. For step (c), claim 37 recites "the substrate temperature control
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`circuit" to be "operable to change the substrate temperature from the selected first
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`substrate temperature to the selected second substrate temperature within a
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`preselected time period to process the film." Ex. 1001, 23:17-21. The claim also
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`requires that the plasma discharge apparatus comprises (1) "a substrate temperature
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`control system comprising a substrate temperature sensor and a substrate
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`temperature control circuit operable to adjust the substrate temperature to a
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` Declaration for Petition 6
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`predetermined substrate temperature value with a first heat transfer process" and
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`(2) "a substrate holder temperature control system comprising a substrate holder
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`temperature sensor and a substrate holder temperature control circuit operable to
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`adjust the substrate holder temperature to a predetermined substrate holder
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`temperature value with a second heat transfer process." Id. at 22:62-23:5.
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`C. The Continuation-In-Part Provisional Application No. 60/058,650
`Disclosure Filed September 11, 1997
`1.
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`Etching the Film (cl. 27) or Film Treatment (cl. 37) at the
`Selected First Temperature, Changing to a Selected Second
`Temperature, and Etching (cl. 27) or Film Treatment (cl.
`37) at the Selected Second Temperature
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`35.
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`In the Summary of the continuation-in-part provisional application,
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`the following is disclosed: "In another aspect of the invention provides an
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`apparatus for etching a substrate in the manufacture of a device using different
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`temperatures during etching." Ex. 1007-11, lines 28-29. Claim 1 of the
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`continuation-in-part provisional application recites "performing a first etching of a
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`first portion of said film at a first temperature and performing a second etching of a
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`second portion of said film at a second temperature, said first temperature being
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`different from said second temperature." Ex. 1007-32, lines 5-7. The specification
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`and Figure 3 further disclose the programmed temperature process. Ex. 1007-49 –
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`1007-50 ("Programmed Temperature Process (Fig. 3)").
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` Declaration for Petition 6
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`2.
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`Using a Measured Substrate Temperature (cl. 27) or a
`Control Circuit and Substrate Temperature Sensor (cl. 37)
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`36.
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`In the description of Figure 6 of the continuation-in-part provisional
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`application, the following is disclosed: "Also possible to have fiber optic for
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`interference or band edge IR sensor or [L]uxtron probe to sense bottom surface
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`temperature of wafer and control on this temperature." Ex. 1007-46, second para.,
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`fifth sentence. In the description of Figure 1 of the continuation-in-part provisional
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`application, the following is disclosed: "The desired fluid temperature is
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`determined by comparing the desired wafer or wafer chuck setpoint temperature to
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`a measured wafer or wafer chuck temperature (this measurement can be performed
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`with a thermocouple, thermistor, pyrometer, fluoroptic® sensor or other sensing
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`means)." Ex. 1007-48, first para., fourth sentence. In the description of Figure 2
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`of the continuation-in-part provisional application, the following is disclosed: "In
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`addition to the sensors TCl and TC2, it is convenient to monitor the top surface
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`chuck temperature and the wafer temperature so that TCl can be selected to
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`maintain the wafer temperature within a specified amount of a wafer etching or
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`CVD temperature . . . ." Ex. 1007-49, first para., sixth sentence. The continuation-
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`in-part application Figure 3 and the description for Figure 3 disclose the etching of
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`the native oxide at room temperature, the etching of tungsten silicide at the higher
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`temperature, the etching of the polysilicon at a reduced temperature , all done in
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` Declaration for Petition 6
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`the same chamber. Ex. 1007-49 – 1007-50.
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`D. Disclosure of Parent Application No. 09/151,163 Filed Dec. 4, 1995
`37.
`In my opinion, the parent application, filed on Dec. 4, 1995, does not
`
`provide written description support for any of claims 27-50, 66, and 67 of the '264
`
`patent, and thus the challenged claims are entitled to priority of no earlier than
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`Sept. 11, 1997. Missing from the parent application is all the above referenced
`
`disclosure as well as the above referenced Figures 1, 2, 3, and 6 in the
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`continuation-in-part provisional application. See Ex. 1008-53 – 1008-65 (parent
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`application figs. 1-9).
`
`38. As discussed above, claims 27 and 37 of the '264 patent recites a
`
`method of performing film treatment or etching on a substrate on a substrate
`
`holder, where the film treatment or etching takes place at both a first temperature
`
`and a second temperature of the substrate and the temperature is changed within a
`
`specific time interval. Claim 27 requires measuring the substrate temperature and
`
`claim 37 requires using a substrate temperature control circuit and a substrate
`
`temperature sensor. The concepts of etching the film at the selected first
`
`temperature and etching at a second portion of the film at the selected second
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`temperature while on the same substrate holder and using a substrate temperature
`
`control circuit and a substrate temperature sensor are entirely lacking from the
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`disclosure of the parent application, and thus the '264 patent cannot claim priority
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`to the parent application.
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` Declaration for Petition 6
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`39. There is no mention of using a substrate temperature control circuit
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`and a substrate temperature sensor in the parent application. Also, there is no
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`mention of changing the substrate holder temperature within a specific time
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`interval.
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`40. Only approximately one page out of 36 pages of the text of the parent
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`application's specification touches on processing a substrate at different
`
`temperatures. Ex. 1008-45. Instead of disclosing changing the temperature of a
`
`single substrate holder to two different temperatures for processing as recited in
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`claims 27-50, 66, and 67, the parent application discloses multiple different
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`substrate holders (or "pedestals") within different chambers, each of which is kept
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`at a different temperature. Id.
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`41. The parent application teaches that the temperature of the substrate is
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`changed by moving the substrate to a different chamber having a different pedestal
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`between each processing step. The photoresist stripping is taught as comprising
`
`two steps, followed by a cooling step. First, stripping occurs in a first chamber
`
`having a pedestal set to "a temperature of about 40 °C to maintain a lower wafer
`
`temperature." Ex. 1008-45, lines 16-23. In the second step, the "wafer was
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`transferred into a [second] chamber," where "overashing was performed to
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`substantially remove all photoresist material from the wafer." Id. at lines 24-31.
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` Declaration for Petition 6
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`The "pedestal of this chamber was at 150 to 200 °C." Id. Then, after the stripping
`
`process is completed, "the wafer is removed" from the previous chamber "and
`
`placed on the cooling station," which "reduces the temperature of the wafer. Ex.
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`1008-46, lines 2-5.
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`42. Thus, the stripping process described in the parent application requires
`
`at least three separate substrate temperature-adjusting devices—at least two
`
`substrate holders (one for each stripping chamber), and a separate "cooling station"
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`to cool the wafer after the photoresist has been removed. This is in contrast to
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`claims 27-50, 66, and 67, which recite changing the temperature of a single
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`substrate holder to influence the film treatment or etching process.
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`43. Accordingly, in my opinion, the parent application does not disclose
`
`at least the following limitations for claims 27-36 and 66:
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` "placing a substrate having a film thereon on the substrate holder in a
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`chamber; etching a first portion of the film at a selected first substrate
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`temperature; and etching a second portion of the film at a selected
`
`second substrate temperature, the selected second substrate
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`