`Thomas et a1.
`
`[11]
`[45]
`
`Patent Number:
`Date of Patent:
`
`4,680,086
`Jul. 14, 1987
`
`[54]
`
`[75]
`
`[73]
`[21]
`[22]
`[51]
`[52]
`
`[58]
`
`[56]
`
`DRY ETCHING OF MULTI-LAYER
`STRUCTURES
`Inventors: Patrick K. Thomas, lPflugerville;
`Dennis C. Hartman, Austin; Jasper
`W. Dockrey, P?ugerville, all of Tex.
`Assignee: Motorola, Inc., Schaumburg, Ill.
`Appl. No.: 841,976
`Filed:
`Mar. 20, 1986
`
`Int. Cl.4 ................. .. H01L 21/306; H01L 21/308
`US. Cl. .................................. .. 156/643; 156/646;
`156/653
`Field of Search ............. .. 156/ 653, 652, 646, 345,
`156/643, 662; 204/192 E, 298, 192.32, 192.34,
`192.35, 192.37
`
`References Cited
`
`_
`
`U.S. PATENT DOCUMENTS
`
`4,253,907 3/1981 Parry et a1. ....................... .. 156/646
`4,414,057 11/1983 Bourassa et a]. .
`..... .. 156/643
`4,464,223 8/1984 Gorin .................... .. 156/345
`4,563,240 1/1986 Shibata et a1. .................... .. 156/646
`
`Primary Examiner-Kenneth M. Schor
`Attorney, Agent, or Firm-John A. Fisher; Jeffrey Van
`Myers; Jonathan P. Meyer
`[57]
`ABSTRACT
`A method for etching multi-layer structures particu
`larly suited for patterning refractory metal silicide/
`polysilicon sandwiches. A ?rst dry etch process is car
`ried out in a ?rst dry etch chamber and is selected to
`rapidly and anisotropically etch the uppermost layer,
`typically a refractory metal silicide. A second dry etch
`process is carried out in a second etch chamber and is
`selected to rapidly and anisotropically etch the underly
`ing layer, typically polysilicon, while having a high
`selectivity to any material underlying the underlying
`layer. The ?rst process is preferably a ?uorine-chemis
`try process with low frequency RF energy and the
`substrate resting on the grounded electrode. The second
`process is preferrably a chlorine-chemistry process with
`high frequency RF energy and the substrate resting on
`the powered electrode.
`
`6 Claims, 4 Drawing Figures
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`FIG. 2C’
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`chemistry etch in which the lower electrode of the
`chamber is grounded. This etch removes unmasked
`portions of the silicide layer and also etches the upper
`portions of the polysilicon layer. The edge pro?le is
`basically that of an anisotropic etch. A second stage,
`which is carried out in a second chamber, comprises a
`high frequency, chlorine chemistry etch in which the
`RF power is applied to the lower electrode. This pro
`cess removes the remaining polysilicon rapidly and
`anisotropically, without signi?cant undercutting, and
`has a very high selectivity to the underlying silicon
`dioxide.
`These and other objects and advantages of the pres
`ent invention will be apparent to one skilled in the art
`from the detailed description below taken together with
`the drawings.
`
`1
`
`DRY ETCHING OF MULTI-LAYER STRUCTURES
`
`FIELD OF THE INVENTION
`The present invention relates, in general, to the dry
`etching of multi-layer structures. More particularly, the
`invention relates to a method useful for dry etching
`refractory metal silicide/polysilicon structures in the
`manufacture, for instance, of semiconductor integrated
`circuits.
`
`5
`
`20
`
`BACKGROUND OF THE INVENTION
`Dry etching, as that term is used in the semiconduc
`tor industry, encompasses a number of related pro
`cesses. The common feature of these processes is the
`presence of a gas or plasma which contains at least one
`reactive specie and which is. energized by the applica
`tion of RF energy. The gas or plasma is placed in
`contact with the structure being etched, a reaction takes
`place at the surface of the material and reacted material
`is removed in gaseous form.
`The various distinct dry etching processes include
`reactive ion etching (RIE) and plasma etching. While
`the precise de?nition of these terms is not completely
`settled, the different processes are typically character
`ized by the pressure of the gas or plasma, the frequency
`of the RF energy supplied thereto, the con?guration of
`the chamber in which the reaction takes place, the
`method of applying the RF energy to the gas or plasma
`and the chemistry of the gas or plasma. The generic
`term dry etching will be used throughout to refer to all
`of these related processes.
`A structure which is of increasing interest in the ?eld
`of integrated circuit manufacturing comprises a two
`layer “sandwich” of polysilicon underlying a refractory
`35
`metal silicide. Such a structure typically overlies a thin
`layer of silicon dioxide dielectric, for example, and
`comprises the gate of an insulated-gate ?eld effect tran
`sistor (IGFET) device. It has been found that such a
`structure is quite dif?cult to etch using dry etching
`40
`techniques because of the differences in the response of
`the silicide and polysilicon materials to the etching
`processes.
`For small geometry devices, it is necessary to care
`fully control the edge pro?le of the structure being
`etched. In addition, since the underlying dielectric is
`often quite thin, a process with a very high selectivity to
`silicon dioxide is required. Despite numerous attempts,
`the prior art does not disclose a dry etching process
`which can effectively etch a silicide/polysilicon struc
`ture with good edge pro?le control and high selectivity
`to an underlying dielectric.
`
`25
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simpli?ed cross-sectional view of an appa
`ratus suitable for practicing the present invention; and
`FIGS. 2A-2C are cross-sectional views illustrating
`various stages during etching according to the princi
`ples of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 is a simpli?ed cross-sectional view of a multi
`chamber dry etching apparatus which is suitable for use
`in practicing the present invention. A similar commer
`cial etcher, although having three chambers instead of
`two, is available from the Zylin Corporation. The appa
`ratus comprises a ?rst etch chamber 10 and a second
`etch chamber 11. Wafers to be etched are loaded into
`?rst chamber 10 by means of an access door 12. Etched
`wafers are removed from second chamber 11 by means
`of an access door 13. Wafers are transported from ?rst
`chamber 10 to second chamber 11 by means of a wafer
`transport 14 which carries the wafers through a passage
`15 which joins ?rst chamber 10 to second chamber 11.
`Inside ?rst chamber 10 are a lower electrode 18 and
`an upper electrode 19. Electrodes 18 and 19 have gener
`ally planar surfaces and are parallel to one another.
`Both upper electrode 19 and lower electrode 18 are
`electrically isolated from the walls of chamber 10. Simi
`larly, a lower electrode 20 and an upper electrode 21 are
`within second chamber 11, have generally planar, paral
`lel surfaces and are electrically isolated from the walls
`of chamber 11. As is familiar, lower electrodes 18 and
`20 are adapted to hold a wafer during the etching pro
`cess. Upper electrodes 19 and 21 are of the “shower
`head” type. That is, both are adapted to dispense the
`reactive gases into the space between the two elec
`trodes by means of a plurality of openings 22 in their
`lower surfaces.
`A ?rst gas supply and ?ow control apparatus 25 is
`coupled to upper electrode 19 in order to supply a con
`trolled ?ow of the chosen process gases to ?rst chamber
`10. Similarly, a second gas supply and ?ow control
`apparatus 26 is coupled to upper electrode 21 in order to
`supply a controlled ?ow of the chosen process gases to
`second chamber 11. For purposes of the present inven
`tion, it is important that each chamber have a dedicated
`gas supply and ?ow control apparatus. Similarly, a ?rst
`vacuum system 27 is coupled through a pressure control
`valve 28 to ?rst chamber 10 to control the pressure
`therein and to remove reaction products therefrom. A
`second vacuum system 32 is coupled through a second
`
`55
`
`SUMMARY OF THE INVENTION
`Accordingly, it is an object of the present invention
`to provide a method for dry etching of multi-layer
`structures which provides adequate edge pro?le control
`and high selectivity to underlying layers.
`It is a further object of the present invention to pro
`vide a method for dry etching of refractory metal silici
`de/polysilicon structures which provides adequate
`edge pro?le control and high selectivity to underlying
`dielectric layers.
`These and other objects and advantages of the pres
`ent invention are provided by a dry etching process of
`65
`two stages which is carried out in a two chamber dry
`etching apparatus. A ?rst stage, which proceeds in a
`?rst chamber, comprises a low frequency, ?uorine
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`pressure control valve 33 to second chamber 11 to con
`trol the pressure therein and to remove reaction prod
`ucts therefrom.
`First chamber 10 is energized, in the preferred em
`bodiment of the present invention, by means of a 50
`KHz power supply 30 which is electrically coupled to
`upper electrode 19. Lower electrode 18 is preferrably
`grounded. Second chamber 11 is energized, in the pre
`ferred embodiment, by means of a 13.56 MHz power
`supply 31 which is electrically coupled to lower elec
`trode 20. Upper electrode 21 is preferrably grounded.
`In operation, a wafer is loaded into ?rst chamber 10
`via access door 12 and placed on lower electrode 18.
`Access door 12 is closed and vacuum system 27 re
`moves the atmosphere from chamber 10 and and vac
`uum system 32 removes the atmosphere from chamber
`11. Once the internal pressure is at a predetermined
`level, gas supply and ?ow control apparatus 25 and 50
`KHz power supply 30 are activated and the ?rst stage
`of the etching process commences. When an endpoint
`of the ?rst stage is reached, which is determined either
`by time or other well known means, gas supply and
`?ow control apparatus 25 and 50 KHz power supply 30
`are de-activated, wafer transport 14 is operated to trans
`fer the wafer from lower electrode 18 to lower elec—
`trode 20 and the second stage of the etch process is
`commenced. Gas supply and ?ow control apparatus 26
`and 13.56 MHz power supply 31 are activated. When an
`endpoint is reached, these are deactivated, the internal
`pressure is equalized with external atmospheric pres
`sure, and the wafer is removed from lower electrode 20
`by means of access door 13.
`In the preferred embodiment of the present invention,
`the ?rst stage of the etch process is designed to rapidly
`and anisotropically etch a silicide material. Of particular
`interest are refractory metal silicide materials such as
`tungsten disilicide, titanium disilicide, molybdenum
`disilicide and tantalum disilicide. It is also possible to
`alter the ?rst stage process slightly in order to optimally
`etch a refractory metal layer. In the preferred embodi
`ment, the process gases supplied are tetrafluorome
`thane, CF4, (at a flow rate of approximately 190 SCCM)
`and oxygen (at a flow rate of approximately 5 SCCM).
`The pressure maintained in chamber 10 is approxi
`mately 1 torr, the power supplied is approximately 80
`watts, and the temperature is approximately 20 degrees
`C. The preferred electrode spacing is approximately 1
`inch. For tungsten silicide, this process produces an
`etch rate of approximately 2500 angstroms per minute
`and a relatively anisotropic edge pro?le. End point
`detection is achieved simply by timing the reaction,
`since it is simply required that the silicide be cleared and
`some portion of the polysilicon be etched. In addition to
`CF4, it is believed that CFC13, CFzClz, CF3Cl, NF3,
`SP6, C2F5Cl and C2F6 might be suitable for the ?rst
`stage of the process.
`’
`The second stage process is, according to the pre
`ferred embodiment, optimized to rapidly and anisotrop
`ically etch the polysilicon without signi?cant undercut
`ting and with a high selectivity to the underlying dielec
`tric, typically silicon dioxide. The process gases chosen
`are helium (?ow rate approximately 466 SCCM), hy
`drogen chloride (flow rate approximately 143 SCCM)
`and hydrogen iodide (?ow rate approximately 17
`SCCM). The pressure in chamber 11 is maintained at
`approximately 1.75 Torr, the temperature is approxi
`mately 5 degrees C. and the power applied is approxi
`mately 200 watts. The preferred electrode spacing is
`
`4,680,086
`4
`approximately 0.5 inch. End point detection is by means
`of monitoring changes in the DC bias between the
`upper and lower electrode, as is familiar in the art. To
`ensure complete removal of the polysilicon, a 100%
`overetch is preferrably used after the endpoint is de
`tected. This process produces very good etch charac
`teristics and has a selectivity to silicon dioxide of ap
`proximately 100:1. No observable undercut is apparent
`in photomicrographs of samples etched according to
`this process and the overall edge pro?le is substantially
`anisotropic. In addition to HCl, it is believed that C12,
`BCl3, CCl4 and SiCl4 might be suitable for the second
`stage of the process.
`-
`FIGS. 2A-2C more completely illustrate the various
`stages involved in the practice of the present invention.
`FIG. 2A illustrates a structure immediately prior to
`etching. An underlying substrate 40, such as a silicon
`wafer or the like, forms the base for the structure. Im
`mediately overlying substrate 40 is a relatively thin
`dielectric layer 41. For instance, layer 41 may comprise
`a gate oxide layer of approximately 250 angstroms
`thickness. Overlying dielectric layer 41 is a polysilicon
`layer 42 which may comprise, for instance, a portion of
`a multi-level gate electrode structure. Polysilicon layer
`42 is typically heavily doped for good conductivity and
`may be approximately 2500 angstroms thick. Overlying
`polysilicon layer 42 is a silicide layer 43 which may
`comprise, for instance, a tungsten disilicide layer form
`ing a portion of a multi-layer gate electrode structure
`and having a thickness of approximately 2500 ang
`stroms. Overlying silicide layer 43 is a patterned photo
`resist layer 44 which is used to create the pattern in the
`underlying layers.
`Photoresist layer 44 may be any of a large number of
`well known photoresist materials whose properties and
`used are familiar. Photoresist layer 44 is preferrably
`pre-treated with a 125 degree C. bake for approximately
`30 minutes and exposed with deep UV for stabilization
`purposes.
`_
`FIG. 2B illustrates the structure after the ?rst stage of
`the etch process. Except under patterned photoresist
`layer 44, all of silicide layer 43 has been removed in a
`substantially anisotropic fashion. In addition, the ?rst
`stage etch has proceeded slightly into polysilicon layer
`42. In the preferred embodiment, approximately 500
`45
`- angstroms of polysilicon are removed.
`FIG. 2C illustrates the structure after the ?nal stages
`of the etch process. The second stage etch has carried
`the pattern down through the remainder of polysilicon
`layer 42 and stopped at dielectric layer 41. In addition,
`a subsequent resist strip operation has removed the
`patterned photoresist. The edge pro?le illustrated in
`FIG. 2C, substantially anisotropic throughout with no
`observable undercut, is consistent with actual photomi
`crographs of samples etched according to the detailed
`process description given above.
`As will be apparent to one skilled in the art, the dis
`closed process provides an improved method for etch
`ing multiple layer structures and, particularly, an im
`proved method for etching silicide/polysilicon struc
`tures for use in semiconductor integrated circuit manu
`facture. The two stage process provides rapid, aniso
`tropic etching of the overlying silicide and also pro
`vides rapid, anisotropic etching of the underlying
`polysilicon with a high degree of selectivity to the un
`derlying dielectric.
`While the present invention has been described with
`reference to a preferred embodiment thereof, various
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`removing said substrate from said second dry etch
`modi?cations and changes thereto will be apparent to
`chamber after exposed portions of said polysilicon
`one skilled in the art and are within the spirit and scope
`have been completely removed wherein the lower
`of the present invention.
`energy of the ?rst RF frequency and the support of
`I claim:
`the substrate on the grounded electrode are such
`1. A method for dry etching a multi-layer structure
`that the silicide is etched rapidly and anisotropi
`comprising a refractory metal silicide overlying a
`cally, while the higher energy of the second RF
`polysilicon material overlying a dielectric material
`frequency and the support of the substrate on the
`comprising the steps of:
`powered electrode are such that the polysilicon is
`forming a patterned photoresist layer overlying said
`eteched rapidly and anisotropically without sub
`refractory metal silicide layer of said multi-layer
`stantially etching the dielectric material.
`structure to protect portions of said silicide layer;
`2. A method according to claim 1 wherein said ?rst
`supporting a substrate bearing said multi-layer struc
`reactive gas mixture comprises tetra?uormethane and
`ture on a grounded electrode in a ?rst parallel
`oxygen and said ?rst frequency RF energy is at approxi
`plate-type dry etch chamber;
`mately 50 KHz.
`energizing a ?rst reactive gas mixture comprising at
`3.‘ A method according to claim 1 wherein said sec
`least one ?uorine-containing compound in said ?rst
`ond'reactive gas mixture comprises hydrogen chloride
`dry etch chamber with energy of a‘ ?rst RF fre
`and hydrogen iodide and said second frequency RF
`quency coupled to a power electrode in said ?rst
`energy is at approximately 13.56 MHz.
`chamber to completely remove unprotected por
`4. A method according to claim 2 wherein a pressure
`tions of said refractory metal silicide;
`in said ?rst dry etch chamber is maintained at approxi
`transporting said substrate from said ?rst dry etch
`mately one Torr.
`chamber to a second parallel plate-type dry etch
`5. A method according to claim 3 wherein a pressure
`chamber after unprotected portions of said refrac
`in said second dry etch chamber is maintained at ap
`tory metal silicide have been completely removed
`proximately 1.75 Torr.
`to expose portions of said polysilicon;
`6. A method according to claim 1 wherein:
`supporting said substrate on a powered electrode in
`said ?rst reactive gas mixture comprises tetra
`said second parallel plate-type dry etch chamber;
`?uoromethane and oxygen at a pressure of approxi
`energizing a second reactive gas mixture comprising
`mately 1 Torr;
`said ?rst frequency is approximately 50 KHZ;
`at least one chlorine-containing compound in said
`said second reactive gas mixture comprises hydrogen
`second dry etch chamber with energy of a second
`RF frequency higher than said ?rst RF frequency
`chloride and hydrogen iodide at a pressure of ap
`coupled to said powered electrode to completely
`. proximately 1.75 Torr; and
`said second frequency is approximately 13.56 MHz.
`remove unprotected portions of said polysilicon;
`and
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