`c12) Reissued Patent
`Flamm
`
`I IIIII
`
`11111111
`
`1111111111111111111111111111111111111111111111
`USOORE40264E
`
`US RE40,264 E
`(10) Patent Number:
`(45) Date of Reissued Patent:
`Apr. 29, 2008
`
`(54) MULTI-TEMPERATURE PROCESSING
`
`(76)
`
`Inventor: DanielL. Flamm, 476 Green View Dr.,
`Walnut Creek, CA (US) 94596
`
`(21) Appl. No.: 10/439,245
`
`(22) Filed:
`
`May 14, 2003
`
`Related U.S. Patent Documents
`
`Reissue of:
`(64) Patent No.:
`Issued:
`Appl. No.:
`Filed:
`
`6,231,776
`May 15, 2001
`09/151,163
`Sep. 10, 1998
`
`U.S. Applications:
`(63) Continuation-in-part of application No. 08/567,224, filed on
`Dec. 4, 1995, now abandoned.
`(60) Provisional application No. 60/058,650, filed on Sep. 11,
`1997.
`
`(51)
`
`Int. Cl.
`HOSH 1100
`HOJL 211302
`
`(2006.01)
`(2006.01)
`
`(52) U.S. Cl. ............................. 216/59; 216/67; 216/68;
`216/74; 438/714; 438/715; 204/192.32;
`156/345.52; 156/345.53
`(58) Field of Classification Search ................. 438/715,
`4381719, 721, 725, 737, 738; 216/41, 49,
`216/63-67, 75, 79; 156/345.27, 345.52, 345.53
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,179,264 A
`5,294,778 A
`5,320,982 A *
`5,556,204 A *
`5,571,366 A
`5,609,720 A *
`5,645,683 A
`5,667,631 A
`5,695,564 A
`
`111993
`3/1994
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`9/1996
`1111996
`3/1997
`7/1997
`9/1997
`12/1997
`
`Cuomo eta!. ......... 219/121.43
`Carman et al .............. 219/385
`............ 428/714
`Tsubone et a!.
`Tamura eta!. .............. 374/161
`Ishii ........................... 156/345
`................. 438/715
`Lenz et a!.
`Miyamoto ............... 156/643.1
`Holland eta!. ............... 216/13
`Imahashi .................... 118/719
`
`12/1997 Ooishi ........................ 438/592
`5,700,734 A
`5,705,433 A * 111998 Olson et al ................. 438/695
`5,756,401 A
`5/1998 Iizuka ........................ 438/719
`5,770,099 A
`6/1998 Rice eta!. .................... 216/68
`5,863,376 A
`111999 Wicker et al ............... 156/345
`7/1999 Rice eta!. .................. 156/345
`5,925,212 A
`8/1999 Fong eta!. ............. 315/111.21
`5,939,831 A
`5,948,283 A
`9/1999 Grosshart .................... 216/67
`5,965,034 A * 10/1999 Vinogradov eta!. .......... 216/68
`6,008,139 A
`12/1999 Pan eta!. ................... 438/730
`6,033,478 A
`3/2000 Kholodenko ................ 118/500
`6,042,901 A
`3/2000 Denison eta!. ............. 427/579
`6,048,798 A
`4/2000 Gadgil et al ................ 438/714
`6,068,784 A
`5/2000 Collins eta!. ................ 216/68
`6,077,357 A * 6/2000 Rossman eta!. ........... 118/728
`6,087,264 A * 7/2000 Shin et a!. .................. 438/706
`6,090,303 A
`7/2000 Collins eta!. ................ 216/68
`6,140,612 A
`10/2000 Husain eta!. .............. 219/390
`12/2000 Collins eta!. .............. 156/345
`6,165,311 A
`6,167,834 B1
`1/2001 Wang eta!. ................ 418/723
`5/2002 Marks et a!.
`6,391,148 B2
`6,486,069 B1
`11/2002 Marks et a!.
`200110003676 A1
`6/2001 Marks et a!.
`FOREIGN PATENT DOCUMENTS
`
`EP
`7/2001
`1236226 A2
`59076876 A * 5/1984
`JP
`WO
`W0-01141189 A2
`7/2001
`* cited by examiner
`Primary Examiner-Anita Alanko
`(74) Attorney, Agent, or Firm-Daniel L. Flamm
`ABSTRACT
`(57)
`
`The present invention provides a technique, including a
`method and apparatus, for etching a substrate in the manu(cid:173)
`facture of a device. The apparatus includes a chamber and a
`substrate holder disposed in the chamber. The substrate
`holder has a selected thermal mass to facilitate changing the
`temperature of the substrate to be etched during etching
`processes. That is, the selected thermal mass of the substrate
`holder allows for a change from a first temperature to a
`second temperature within a characteristic time period to
`process a film. The present technique can, for example,
`provide different processing temperatures during an etching
`process or the like.
`
`59 Claims, 15 Drawing Sheets
`
`LAM Exh 1001-pg 1
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`U.S. Patent
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`Apr. 29, 2008
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`Apr. 29, 2008
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`US RE40,264 E
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`Apr. 29,2008
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`Sheet 4 of 15
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`US RE40,264 E
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`Apr. 29, 2008
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`US RE40,264 E
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`LAM Exh 1001-pg 6
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`Apr. 29, 2008
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`US RE40,264 E
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`Apr. 29, 2008
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`Apr. 29, 2008
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`Sheet 15 of 15
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`LAM Exh 1001-pg 16
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`
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`US RE40,264 E
`
`1
`MULTI-TEMPERATURE PROCESSING
`
`Matter enclosed in heavy brackets [ ] appears in the
`original patent but forms no part of this reissue specifi(cid:173)
`cation; matter printed in italics indicates the additions
`made by reissue.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This present application is a continuation-in-part of U.S.
`application Ser. No. 60/058,650 filed Sep. 11, 1997, and a
`continuation-in-part of U.S. application Ser. No. 08/567,224
`filed Dec. 4, 1995, now abandoned which are hereby incor(cid:173)
`porated by reference for all purposes.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`2
`processed in such chamber are controlled to be at a sub(cid:173)
`stantially a single value of temperature during processing.
`From the above it is seen that an improved technique,
`including a method and apparatus, for plasma processing is
`often desired.
`SUMMARY OF THE INVENTION
`The present invention provides a technique, including a
`method and apparatus, for fabricating a product using a
`plasma discharge. One aspect of the present technique relies
`upon multi-stage etching processes for selectively removing
`a film on a workpiece using differing temperatures. It
`overcomes serious disadvantages of prior art methods in
`which throughput and etching rate were lowered in order to
`avoid excessive device damage to a workpiece. In particular,
`15 this technique is extremely beneficial for removing resist
`masks which have been used to effect selective ion implan(cid:173)
`tation of a substrate in some embodiments. In general,
`implantation of ions into a resist masking surface causes the
`upper surface of said resist to become extremely cross-
`20 linked and contaminated by materials from the ion bom(cid:173)
`bardment. If the cross-linked layer is exposed to excessive
`temperature, it is prone to rupture and forms contaminative
`particulate matter. Hence, the entire resist layer is often
`processed at a low temperature to avoid this particle prob-
`25 !em. Processing at a lower temperature often requires exces(cid:173)
`sive time which lowers throughput. Accordingly, the present
`invention overcomes these disadvantages of conventional
`processes by rapidly removing a majority of resist at a higher
`temperature after an ion implanted layer is removed without
`substantial particle generation at a lower temperature.
`In another aspect, the present invention provides a process
`which utilizes temperature changes to achieve high etch
`rates while simultaneously maintaining high etch selectivity
`between a layer which is being pattered or removed other
`material layers. An embodiment of this process advanta-
`35 geously employs a sequence of temperature changes as an
`unexpected means to avoid various types of processing
`damage to the a device and material layers. A novel inven(cid:173)
`tive means for effecting a suitable controlled change in
`temperature as part of a process involves the use of a
`40 workpiece support which has low thermal mass in compari(cid:173)
`son to the heat transfer means. In an aspect of this invention,
`a fluid is utilized to change the temperature of a workpiece.
`In another aspect, the thermal capacity of a circulating fluid
`is sufficiently greater than the thermal capacity of the
`45 workpiece support that it permits maintaining the workpiece
`at a substantially uniform temperature.
`Still another aspect of the invention provides an apparatus
`for etching a substrate in the manufacture of a device using
`different temperatures during etching. The apparatus
`50 includes a chamber and a substrate holder disposed in the
`chamber. The substrate holder has a selected thermal mass to
`facilitate changing the temperature of the substrate to be
`etched. That is, the selected thermal mass of the substrate
`holder allows for a change from a first temperature to a
`55 second temperature within a characteristic time period to
`process a film. The present apparatus can, for example,
`provide different processing temperatures during an etching
`process or the like.
`The present invention achieves these benefits in the
`60 context of known process technology. However, a further
`understanding of the nature and advantages of the present
`invention may be realized by reference to the latter portions
`of the specification and attached drawings.
`
`30
`
`This invention relates generally to plasma processing.
`More particularly, one aspect of the invention is for greatly
`improved plasma processing of devices using an in-situ
`temperature application technique. Another aspect of the
`invention is illustrated in an example with regard to plasma
`etching or resist stripping used in the manufacture of semi(cid:173)
`conductor devices. The invention is also of benefit in plasma
`assisted chemical vapor deposition (CVD) for the manufac(cid:173)
`ture of semiconductor devices. But it will be recognized that
`the invention has a wider range of applicability. Merely by
`way of example, the invention also can be applied in other
`plasma etching applications, and deposition of materials
`such as silicon, silicon dioxide, silicon nitride, polysilicon,
`among others.
`Plasma processing techniques can occur in a variety of
`semiconductor manufacturing processes. Examples of
`plasma processing techniques occur in chemical dry etching
`(CDE), ion-assisted etching (IAE), and plasma enhanced
`chemical vapor deposition (PECVD), including remote
`plasma deposition (RPCVD) and ion-assisted plasma
`enhanced chemical vapor deposition (IAPECVD). These
`plasma processing techniques often rely upon radio fre(cid:173)
`quency power (rf) supplied to an inductive coil for providing
`power to produce with the aid of a plasma.
`Plasmas can be used to form neutral species (i.e.,
`uncharged) for purposes of removing or forming films in the
`manufacture of integrated circuit devices. For instance,
`chemical dry etching is a technique which generally depends
`on gas-surface reactions involving these neutral species
`without substantial ion bombardment.
`In a number of manufacturing processes, ion bombard(cid:173)
`ment to substrate surfaces is often undesirable. This ion
`bombardment, however, is known to have harmful effects on
`properties of material layers in devices and excessive ion
`bombardment flux and energy can lead to intermixing of
`materials in adjacent device layers, breaking down oxide
`and "wear out," injecting of contaminative material formed
`in the processing environment into substrate material layers,
`harmful changes in substrate morphology (e.g.
`amophotization), etc.
`Ion assisted etching processes, however, rely upon ion
`bombardment to the substrate surface in defining selected
`films. But these ion assisted etching processes commonly
`have a lower selectivity relative to conventional CDE pro(cid:173)
`cesses. Hence, CDE is often chosen when high selectivity is
`desired and ion bombardment to substrates is to be avoided.
`In generally most, if not all, of the above processes 65
`maintain temperature in a "batch" mode. That is, the tem(cid:173)
`perature of surfaces in a chamber and of the substrate being
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simplified diagram of a plasma etching
`apparatus according to the present invention;
`
`LAM Exh 1001-pg 17
`
`
`
`US RE40,264 E
`
`3
`FIGS. 2A-2E are simplified configurations using wave
`adjustment circuits according to the present invention;
`FIG. 3 is a simplified diagram of a chemical vapor
`deposition apparatus according to the present invention;
`FIG. 4 is a simplified diagram of a stripper according to
`the present invention;
`FIGS. 5A-5C are more detailed simplified diagrams of a
`helical resonator according to the present invention;
`FIG. 6 is a simplified block diagram of a substrate holder
`according to the present invention;
`FIG. 7 is a simplified diagram of a temperature control
`system according to an embodiment of the present inven(cid:173)
`tion;
`FIG. 8 is a simplified diagram of a fluid reservoir system
`according to an embodiment of the present invention;
`FIG. 9 is a [simplified diagram of a] simplified diagram of
`a semiconductor substrate according to an embodiment of
`the present invention; and
`FIG.10 is a simplified [flow diagram of a heating] process
`according to the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 is a simplified diagram of a plasma etch apparatus
`10 according to the present invention. This etch apparatus is
`provided with an inductive applicator, e.g., inductive coil.
`This etch apparatus depicted, however, is merely an
`illustration, and should not limit the scope of the claims as
`defined herein. One of ordinary skilled in the art may
`implement the present invention with other treatment cham(cid:173)
`bers and the like.
`The etch apparatus includes a chamber 12, a feed source
`14, an exhaust 16, a product support check or pedestal 18,
`an inductive applicator 20, a radio frequency ("rf') power
`source 22 to the inductive applicator 20, wave adjustment
`circuits 24, 29 (WACs), a radio frequency power source 35
`to the pedestal 18, a controller 36, an agile temperature
`control means [19], and other elements. Optionally, the etch
`apparatus includes a gas distributor 17.
`The chamber 12 can be any suitable chamber capable of
`housing a product 28, such as a wafer to be etched, and for
`providing a plasma discharge therein. The chamber can be a
`domed chamber for providing a uniform plasma distribution
`over the product 28 to be etched, but the chamber also can
`be configured in other shapes or geometries, e.g., flat ceiling,
`truncated pyramid, cylindrical, rectangular, etc. Depending
`upon the application, the chamber is selected to produce a
`uniform entity density over the pedestal18, providing a high
`density of entities (i.e., etchant species) for etching unifor- 50
`mity.
`The product support chuck can rapidly change its tem(cid:173)
`perature in ways defined herein as well as others. The wafer
`is often thermally coupled to the support check which
`permits maintaining the wafer temperature in a known 55
`relationship with respect to the chuck. Coupling will often
`comprise an electrostatic chuck or mechanical clamps,
`which apply a pressure to bring the product into close
`proximity with the support check, which enables a relatively
`good thermal contact between the wafer and support chuck. 60
`The support chuck and wafer are often maintained at a
`substantially equal temperature. A pressure of gas is often
`applied through small openings in the support chuck behind
`the wafer in order to improve thermal contact and heat
`transfer between the wafer and support chuck.
`The present chamber includes a dome 25 having an
`interior surface 26 made of quartz or other suitable materi-
`
`4
`als. The exterior surface of the chamber is typically a
`dielectric material such as a ceramic or the like. Chamber 12
`also includes a process kit with a focus ring 32, a cover (not
`shown), and other elements. Preferably, the plasma dis(cid:173)
`charge is derived from the inductively coupled plasma
`source that is a de-coupled plasma source ("DPS") or a
`helical resonator, although other sources can be employed.
`The de-coupled source originates from rf power derived
`from the inductive applicator 20. Inductively coupled power
`10 is derived from the power source 22. The rf signal frequen(cid:173)
`cies ranging from 800 kHz to 80 MHz can be provided to the
`inductive applicator 20. Preferably, the rf signal frequencies
`range from 5 MHz to 60 MHz. The inductive applicator
`(e.g., coil, antenna, transmission line, etc.) overlying the
`15 chamber ceiling can be made using a variety of shapes and
`ranges of shapes. For example, the inductive applicator can
`be a single integral conductive film, a transmission line, or
`multiple coil windings. The shape of the inductive applicator
`and its location relative to the chamber are selected to
`20 provide a plasma overlying the pedestal to improve etch
`uniformity.
`The plasma discharge (or plasma source) is derived from
`the inductive applicator 20 operating with selected phase 23
`and anti-phase 27 potentials (i.e., voltages) that substantially
`25 cancel each other. The controller 36 is operably coupled to
`the wave adjustment circuits 24, 29. In one embodiment,
`wave adjustment circuits 24, 29 provide an inductive appli(cid:173)
`cator operating at full-wave multiples 21. This embodiment
`of full-wave multiple operation provides for balanced
`30 capacitance of phase 23 and anti-phase voltages 27 along the
`inductive applicator (or coil adjacent to the plasma). This
`full-wave multiple operation reduces or substantially elimi(cid:173)
`nates the amount of capacitively coupled power from the
`plasma source to chamber bodies (e.g., pedestal, walls,
`35 wafer, etc.) at or close to ground potential. Alternatively, the
`wave adjustment circuits 24, 29 provide an inductive appli(cid:173)
`cator that is effectively made shorter or longer than a
`full-wave length multiple by a selected amount, thereby
`operating at selected phase and anti-phase voltages that are
`40 not full-wave multiples. Alternatively, more than two, one or
`even no wave adjustment circuits can be provided in other
`embodiments. But in all of these above embodiments, the
`phase and anti-phase potentials substantially cancel each
`other, thereby providing substantially no capacitively
`45 coupled power from the plasma source to the chamber
`bodies.
`In alternative embodiments, the wave adjustment circuit
`can be configured to provide selected phase and anti-phase
`coupled voltages coupled from the inductive applicator to
`the plasma that do not cancel. This provides a controlled
`potential between the plasma and the chamber bodies, e.g.,
`the substrate, grounded surfaces, walls, etc. In one
`embodiment, the wave adjustment circuits can be used to
`selectively reduce current (i.e., capacitively coupled current)
`to the plasma. This can occur when certain high potential
`difference regions of the inductive applicator to the plasma
`are positioned (or kept) away from the plasma region (or
`inductor-containing-the-plasma region) by making them go
`into the wafer adjustment circuit assemblies, which are
`typically configured outside of the plasma region. In this
`embodiment, capacitive current is reduced and a selected
`degree of symmetry between the phase and anti-phase of the
`coupled voltages is maintained, thereby provided a selected
`potential or even substantially ground potential. In other
`65 embodiments, the wave adjustment circuits can be used to
`selectively increase current (i.e., capacitively coupled
`current) to the plasma.
`
`LAM Exh 1001-pg 18
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`US RE40,264 E
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`5
`As shown, the wave adjustment circuits are attached (e.g.,
`connected, coupled, etc.) to ends of the inductive applicator.
`Alternatively, each of these wave adjustment circuits can be
`attached at an intermediate position away from the inductive
`application ends. Accordingly, upper and lower tap positions
`for respective wave adjustment circuits can be adjustable.
`But both the inductive applicator portions below and above
`each tap position are active. That is, they both can interact
`with the plasma discharge.
`A sensing apparatus can be used to sense plasma voltage 10
`which is used to provide automatic turning of the wave
`adjustment circuits and any rf matching circuit between the
`rf generator and the plasma treatment chamber. This sensing
`apparatus can maintain the average AC potential at zero or
`a selected value relative to ground or any other reference 15
`value. This wave adjustment circuit provides for a selected
`potential difference between the plasma source and chamber
`bodies. These chamber bodies may be at a ground potential
`or a potential supplied by another bias supply, e.g., See FIG.
`1 reference numeral 35. Examples of wave adjustment 20
`circuits are described by way of the FIGS. below.
`For instance, FIGS. 2A to 2E are simplified configurations
`using the wave adjustment circuits according to the present
`invention. These simplified configurations should not limit
`the scope of the claims herein. In an embodiment, these 25
`wave adjustment circuits employ substantially equal circuit
`elements (e.g., inductors, capacitors, transmission line
`sections, and others) such that the electrical length of the
`wave adjustment circuits in series with the inductive appli(cid:173)
`cator coupling power to the plasma is substantially an 30
`integral multiple of one wavelength. In other embodiments,
`the circuit elements provide for inductive applicators at
`other wavelength multiples, e.g., one-sixteenth-wave, one(cid:173)
`eighth-wave, quarter-wave, half-wave, three-quarter wave,
`etc. In these embodiments (e.g., full-wave multiple, half- 35
`wave, quarter-wave, etc.), the phase and anti-phase relation(cid:173)
`ship between the plasma potentials substantially cancel each
`other. In further embodiments, the wave adjustment circuits
`employ circuit elements that provide plasma applicators
`with phase and anti-phase potential relationships that do not 40
`cancel each other out using a variety of wave length por-
`tions.
`FIG. 2A is a simplified illustration of a plasma source 50
`using wave adjustment circuits and an agile temperature
`chuck 75 according to an embodiment of the present inven(cid:173)
`tion. This plasma source 50 includes a discharge tube 52, an
`inductive applicator 55, an exterior shield 54, an upper wave
`adjustment circuit 57, a lower wave adjustment circuit 59, an
`rf power supply 61, and other elements. The upper wave
`adjustment circuit 57 is a helical coil transmission line
`portion 69, outside of the plasma source region 60. Lower
`wave adjustment circuit 59 also is a helical coil transmission
`line portion 67 outside of the plasma source region 60. The
`power supply 61 is attached 65 to this lower helical coil
`portion 67, and is grounded 63. Each of the wave adjustment
`circuits also are shielded 66, 68.
`In this embodiment, the wave adjustment circuits are
`adjusted to provide substantially zero AC voltage at one
`point on the inductive coil (refer to point 00 in FIG. 2A).
`This embodiment also provides substantially equal phase 70
`and anti-phase 71 voltage distributions in directions about
`this point (refer to 00-A and 00-C in FIG. 2A) and provides
`substantially equal capacitance coupling to the plasma from
`physical inductor elements (00-C) and (00-A), carrying the
`phase and anti-phase potentials. Voltage distributions 00-A
`and 00-C are combined with C-D and A-B (shown by the
`phantom lines) to substantially comprise a full-wave voltage
`
`6
`distribution in this embodiment where the desired configu(cid:173)
`ration is a selected phase/anti-phase portion of a full-wave
`inductor (or helical resonator) surrounding the plasma
`source discharge tube.
`In this embodiment, it is desirable to reduce or minimize
`capacitive coupling current from the inductive element to
`the plasma discharge in the plasma source. Since the capaci(cid:173)
`tive current increases monotonically with the magnitude of
`the difference of peak phase and anti-phase voltages, which
`occur at points A and C in FIG. 2A, this coupling can be
`lessened by reducing this voltage difference. In FIG. 2A, for
`example, it is achieved by way of two wave adjustment
`circuits 57, 59. Coil 55 (or discharge source) is a helical
`resonator and the wave adjustment circuits 57, 59 are helical
`resonators.
`The discharge source helical resonator 53 can be con(cid:173)
`structed using conventional design formulae. Generally, this
`helical resonator includes an electrical length which is a
`selected phase portion "x" (A to 00 to C) of a full-wave
`helical resonator. The helical resonator wave adjustment
`circuits are each selected to jointly comprise a portion (2n-x)
`of full-wave helical resonators. Physical parameters for the
`wave adjustment helical resonators can be selected to realize
`practical physical dimensions and appropriate Q, Z0 , etc
`values. In particular, some or even all of the transmission
`line parameters (Q, Z0 , etc.) of the wave adjustment circuit
`sections may be selected to be substantially the same as the
`transmission line parameters of the inductive applicator. The
`portion of the inductive plasma applicator helical resonator,
`on the other hand, is designed and sized to provide selected
`uniformity values over substrate dimensions within an eco-
`nomical equipment size and reduced Q.
`The wave adjustment circuit provides for external rf
`power coupling, which can be used to control and match
`power to the plasma source, as compared to conventional
`techniques used in helical resonators and the like. In
`particular, conventional techniques often match to, couple
`power to, or match to the impedance of the power supply to
`the helical resonator by varying a tap position along the coil
`above the grounded position, or selecting a fixed tap position
`relative to a grounded coil end and matching to the imped-
`ance at this position using a conventional matching network,
`e.g., LC network, Jt network, etc. Varying this tap position
`along the coil within a plasma source is often cumbersome
`45 and generally imposes difficult mechanical design problems.
`Using the fixed tap and external matching network also is
`cumbersome and can cause unanticipated changes in the
`discharge Q, and therefore influences its operating mode and
`stability. In the present embodiments, the wave adjustment
`50 circuits can be positioned outside of the plasma source (or
`constrained in space containing the inductive coil, e.g., See
`FIG. 2A. Accordingly, the mechanical design (e.g., means
`for varying tap position, change in the effective rf power
`coupling point by electrical means, etc.) of the tap position
`55 are simplified relative to those conventional techniques.
`In the present embodiment, rf power is fed into the lower
`wave adjustment circuit 59. Alternatively, rf power can be
`fed into the upper wave adjustment circuit (not shown). The
`rf power also can be coupled directly into the inductive
`60 plasma coupling applicator (e.g., coil, etc.) in the wave
`adjustment circuit design, as illustrated by FIG. 2B.
`Alternatively, other applications will use a single wave
`adjustment circuit, as illustrated by FIG. 2C. Power can be
`coupled into this wave adjustment circuit or by conventional
`65 techniques such as a tap in the coil phase. In some
`embodiments, this tap in the coil phase is positioned above
`the grounded end. An external impedance matching network
`
`LAM Exh 1001-pg 19
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`US RE40,264 E
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`15
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`20
`
`7
`may then be operably coupled to the power for satisfactory
`power transfer efficiency from, for example, a conventional
`coaxial cable to impedances (current to voltage rations)
`existing between the wave adjustment circuit terminated end
`of the applicator and the grounded end.
`A further embodiment using multiple inductive plasma
`applicators also is provided, as shown in FIG. 2D. This
`embodiment includes multiple plasma applicators (PA 1,
`PA2 ... PAn). These plasma applicators respectively provide
`selected combinations of inductively coupled power and 10
`capacitively coupled power from respective voltage poten(cid:173)
`tials (Vl, V2 ... Vn). Each of these plasma applicators
`derives power from its power source (PSI, PS2 ... PSn)
`either directly through an appropriate matching or coupling
`network or by coupling to a wave adjustment circuit as
`described. Alternatively, a single power supply using power
`splitters and impedance matching networks can be coupled
`to each (or more than two) of the plasma applicators.
`Alternatively, more than one power supply can be used
`where at least one power supply is shared among more than
`one plasma applicator. Each power source is coupled to its
`respective wave adjustment circuits (WAC!, WAC2 ...
`WACn).
`Generally, each plasma applicator has an upper wave
`adjustment circuit (e.g., WACla, WAC2a ... WACna) and a
`lower wave adjustment circuit (e.g.,