DATA SHEET
`
`m PD75004(A), 75006(A), 75008(A)
`
`MOS INTEGRATED CIRCUIT
`
`4-BIT SINGLE-CHIP MICROCOMPUTER
`
`DESCRIPTION
`The m PD75008(A) is one of the 75X Series 4-bit single-chip microcomputer.
`In addition to high-speed operation with 0.95 m s minimum instruction execution time for the CPU, the
`m PD75008(A) employs a serial bus interface with standard NEC format, the m PD75004(A) is a powerful product
`with a high cost/performance ratio.
`The m PD75P008 with PROM, which is provided with m PD75008(A), is applicable for evaluating systems under
`development.
`
`Detailed functions are described in the following user’s manual. Be sure to read it for designing.
`m PD7500X Series User’s Manual: IEM-5033
`
`FEATURES
`• More reliable than the m PD75008
`• Capable of high-speed operation and variable instruction execution time to power save
`• 0.95 m s, 1.91 m s, 15.3 m s (Main system clock: operating at 4.19 MHz)
`• 122 m s (Subsystem clock: operating at 32.768 kHz)
`• 75X architecture comparable to that for an 8-bit microcomputer is employed
`• Built-in NEC standard serial bus interface (SBI)
`• Clock operation at reduced power dissipation (5 m A TYP. : operating at 3 V)
`• Enhanced timer function (3 channels)
`• Interrupt functions especially enhanced for applications, such as remote control receiver
`
`APPLICATIONS
`Suitable for automotive and transportation equipments, etc.
`
`Unless otherwise specified, m PD75008(A) is treated as the representative model throughout this manual.
`
`The information in this document is subject to change without notice.
`
`Document No.
`(O. D. No.
`Date Published
`Printed in Japan
`
`IC-2832B
`IC-8267B)
`January 1994 P
`
`The mark H shows major revised points.
`
` NEC Corporation 1990
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0001
`
`ª
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`ORDERING INFORMATION
`Part Number
`m PD75004CU(A)-xxx
`m PD75004GB(A)-xxx-3B4
`m PD75006CU(A)-xxx
`m PD75006GB(A)-xxx-3B4
`m PD75008CU(A)-xxx
`m PD75008GB(A)-xxx-3B4
`
`Remarks: xxx is code number.
`
`Package
`
`Quality Grade
`
`42-pin plastic shrink DIP (600 mil)
`44-pin plastic QFP (nn 10 mm)
`42-pin plastic shrink DIP (600 mil)
`44-pin plastic QFP (nn 10 mm)
`42-pin plastic shrink DIP (600 mil)
`44-pin plastic QFP (nn 10 mm)
`
`Special
`Special
`Special
`Special
`Special
`Special
`
`Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by
`NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
`
`2
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0002
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`DIFFERENCES BETWEEN m PD7500X(A) AND m PD7500X SERIES
`
`Product
`
`m PD75004(A)
`m PD75006(A)
`m PD75008(A)
`Special
`Not offered
`
`m PD75004
`m PD75006
`m PD75008
`Standard
`Offered
`
`Absolute
`Maximum
`Ratings
`DC Characteris-
`tics
`
`Differ in high level and low level output
`current.
`
`Differ in low level output voltage.
`
`Item
`Quality Grade
`Directly Driving LED
`
`Electrical Specifications
`
`FUNCTIONAL OUTLINE
`
`Item
`Instruction
`Execution Time
`
`Internal
`Memory
`
`ROM
`
`RAM
`General-Purpose
`Registers
`
`Function
`0.95, 1.91, and 15.3 m s, (Main system clock: operating at 4.19 MHz)
`122 m s (Subsystem clock: operating at 32.768 kHz)
`4096 ·
` 8-bit (m PD75004(A))
`6016 ·
` 8-bit (m PD75006(A))
`8064 ·
` 8-bit (m PD75008(A))
`512 ·
` 4-bit
`• 4-bit manipulation: 8
`• 8-bit manipulation: 4
` 8
`CMOS Input pins
`
`I/O Port
`
`34
`
`18
`
`CMOS input/output pins
`
` 8
`
`N-ch open-drain
`input/output
`
`Internal pull-up resistor
`specification by software
`is possible. : 25
`
`Withstand voltage: 10V
`Internal pull-up resistor
`specification by mask option
`is possible.
`
`Timer
`
`Serial
`Interface
`
`3 chs
`
`Timer/event counter
`Basic interval timer: Also serves as watchdog timer
`Watch timer: Buzzer output possible
`• 3-line serial I/O mode
`• 2-line serial I/O mode
`• SBI mode
`16 bits
`
`Bit Sequential
`Buffer
`fx/23, fx/24, fx/26
`Clock Output Function F,
`Vector Interrupt
`External: 3, Internal: 3
`Test Input
`External: 1, Internal: 1
`System Clock
`• Main system clock oscillation ceramic/crystal oscillator
`Oscillator
`• Subsystem clock oscillation crysal ocillator
`Standby Function
`STOP/HALT mode
`–40 to +85(cid:176) C
`Operating
`Temperature Range
`Operating Supply
`Voltage
`Package
`
`2.7 to 6.0 V
`
`• 42-pin plastic shrink DIP (600 mil)
`• 44-pin plastic QFP (nn 10 mm)
`
`3
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0003
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`CONTENTS
`
`1. PIN CONFIGURATION (Top View) ................................................................................................
`
`2. BLOCK DIAGRAM ...........................................................................................................................
`
`3. PIN FUNCTIONS..............................................................................................................................
`3.1
`PORT PINS .............................................................................................................................................
`3.2
`NON PORT PINS ...................................................................................................................................
`3.3
`PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................
`3.4
`SELECTION OF MASK OPTION ..........................................................................................................
`3.5
`RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................
`3.6
`NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................
`
`6
`
`8
`
`9
`9
`11
`12
`14
`14
`15
`
`4. MEMORY CONFIGURATION .......................................................................................................... 16
`
`5. PERIPHERAL HARDWARE FUNCTIONS........................................................................................ 20
`5.1
`PORTS ....................................................................................................................................................
`20
`5.2
`CLOCK GENERATOR CIRCUIT ............................................................................................................
`21
`5.3
`CLOCK OUTPUT CIRCUIT ....................................................................................................................
`22
`5.4
`BASIC INTERVAL TIMER .....................................................................................................................
`23
`5.5 WATCH TIMER ......................................................................................................................................
`24
`5.6
`TIMER/EVENT COUNTER .....................................................................................................................
`24
`5.7
`SERIAL INTERFACE ..............................................................................................................................
`26
`5.8
`BIT SEQUENTIAL BUFFER ...................................................................................................................
`28
`
`6.
`
`INTERRUPT FUNCTIONS................................................................................................................ 28
`
`7. STANDBY FUNCTIONS .................................................................................................................. 30
`
`8. RESET FUNCTION ........................................................................................................................... 31
`
`9.
`
`INSTRUCTION SET .........................................................................................................................
`
`33
`
`10. ELECTRICAL SPECIFICATIONS ...................................................................................................... 40
`
`11. PACKAGE DRAWINGS ................................................................................................................... 52
`
`4
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0004
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 55
`
`APPENDIX A. DEFFERENCES BETWEEN m PD7500X(A) SERIES
`AND RELATED PROM VERSIONS ............................................................................. 56
`
`APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 57
`
`APPENDIX C. RELATED DOCUMENTS .............................................................................................. 58
`
`5
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0005
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`1. PIN CONFIGURATION (Top View)
`
`• 42-pin plastic shrink DIP (600 mil)
`
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`24
`23
`22
`
`V
`SS
`P40
`P41
`P42
`P43
`P50
`P51
`P52
`P53
`P60/KR0
`P61/KR1
`P62/KR2
`P63/KR3
`P70/KR4
`P71/KR5
`P72/KR6
`P73/KR7
`P20/PTO0
`P21
`P22/PCL
`P23/BUZ
`
`m
`
`m
`
`m
`
`PD75004CU(A)-xxx
`
`PD75006CU(A)-xxx
`
`PD75008CU(A)-xxx
`
`1
`
`2 3 4 5 6 7 8 9
`
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`
`XT1
`XT2
`RESET
`X1
`X2
`P33
`P32
`P31
`P30
`P81
`P80
`SI/SB1/P03
`SO/SB0/P02
`SCK/P01
`INT4/P00
`TI0/P13
`INT2/P12
`INT1/P11
`INT0/P10
`NC
`VDD
`
`NC
`P12/INT2
`P11/INT1
`P10/INT0
`
`DD
`
`C
`V N
`
`P23/BUZ
`P22/PCL
`P21
`P20/PTO0
`P73/KR7
`
`• 44-pin plastic QFP (nn 10 mm)
`
`P03/TI0
`P00/INT4
`P01/SCK
`P02/SO/SB0
`P03/SI/SB1
`P80
`P81
`P30
`P31
`P32
`P33
`
`44 43 42 41 40 39 38 37 36 35 34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`0
`24
`11
`23
`12 13 14 15 16 17 18 19 20 21 22
`
`1
`
`2 3 4 5 6 7 8 9 1
`
`P72/KR6
`P71/KR5
`P70/KR4
`P63/KR3
`P62/KR2
`P61/KR1
`P60/KR0
`P53
`P52
`P51
`P50
`
`m
`
`PD75004GB(A)–xxx–3B4
`
`m
`
`m
`
`PD75006GB(A)–xxx–3B4
`
`PD75008GB(A)–xxx–3B4
`
`X2
`X1
`RESET
`XT2
`XT1
`V
`SS
`P40
`P41
`P42
`P43
`NC
`
`6
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0006
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`Pin names
`
`P00-P03 : Port 0
`P10-P13 : Port 1
`P20-P23 : Port 2
`P30-P33 : Port 3
`P40-P43 : Port 4
`P50-P53 : Port 5
`P60-P63 : Port 6
`P70-P73 : Port 7
`P80-P81 : Port 8
`KR0-KR7 : Key Return
`SCK
`: Serial Clock
`SI
`: Serial Input
`
`SO
`SB0,SB1
`RESET
`TI0
`PTO0
`BUZ
`PCL
`INT0, 1, 4
`INT2
`X1, 2
`XT1, 2
`NC
`
`: Serial Output
`: Serial Bus 0,1
`: Reset Input
`: Timer Input 0
`: Programmable Timer Output 0
`: Buzzer Clock
`: Programmable Clock
`: External Test Interrupt 0,1,4
`: External Test Input 2
`: Main System Clock Oscillation 1,2
`: Subsystem Clock Oscillation 1,2
`: No Connection
`
`7
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0007
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`2. BLOCK DIAGRAM
`
`PORT 0
`
`4
`
`P00-P03
`
`PORT 1
`
`4
`
`P10-P13
`
`PORT 2
`
`4
`
`P20-P23
`
`PORT 3
`
`4
`
`P30-P33
`
`CY
`
`ALU
`
`SP (8)
`
`BANK
`
`GENERAL REG.
`
`PORT 4
`
`4
`
`P40-P43
`
`DECODE
`AND
`CONTROL
`
`DATA
`MEMORY
`(RAM)
`512 4 BITS
`
`PORT 5
`
`4
`
`P50-P53
`
`PORT 6
`
`4
`
`P60-P63
`
`PORT 7
`
`4
`
`P70-P73
`
`PORT 8
`
`2
`
`P80-P81
`
`PROGRAM
`COUNTER *
`
`PROGRAM
`MEMORY
`(ROM)
`4096 8 BITS
`( PD75004(A))
`6016 8 BITS
`( PD75006(A))
`8064 8 BITS
`m
`( PD75008(A))
`
`m m
`
`f /2X
`
`N
`
`CLOCK
`OUTPUT
`CONTROL
`
`CLOCK
`DIVIDER
`
`SYSTEM CLOCK
`GENERATOR
`
`SUB MAIN
`
`STAND BY
`CONTROL
`
`CPU
`CLOCK
`
`PCL/P22
`
`XT1 XT2 X1
`
`X2
`
`V DD
`
`V SS RESET
`
`8
`
`BASIC
`INTERVAL
`TIMER
`
`INTBT
`
`TI0/P13
`PTO0/P20
`
`TIMER/EVENT
`COUNTER
`#0
`
`BUZ/P23
`
`SI/SB1/P03
`SO/SB0/P02
`SCK/P01
`
`INT0/P10
`
`INT1/P11
`INT2/P12
`INT4/P00
`KR0/P60
`–KR7/P73
`
`INTT0
`
`WATCH
`TIMER
`
`INTW
`
`CLOCKED
`SERIAL
`INTERFACE
`
`INTCSI
`
`INTERRUPT
`CONTROL
`
`BIT SEQ.
`BUFFER (16)
`
`m
`m
`m
`*: For PD75004(A), 12 bits. For PD75006(A) and PD75008(A), 13 bits.
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0008
`
`·
`·
`·
`·
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`3. PIN FUNCTIONS
`
`3.1
`
`PORT PINS (1/2)
`
`Pin Name Input/Output
`
`Also Served
`As
`
`Function
`
`8-Bit I/O When Reset
`
`Input
`
`INT4
`
`SCK
`
`SO/SB0
`
`SO/SB1
`
`INT0
`
`INT1
`
`INT2
`
`TI0
`
`PTO0
`
`—
`
`PCL
`
`BUZ
`
`— — — —
`
`—
`
`—
`
`P00
`
`P01
`
`P02
`
`P03
`
`P10
`
`P11
`
`P12
`
`P13
`
`P20
`
`P21
`
`P22
`
`P23
`
`P30
`
`P31
`
`P32
`
`P33
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`Input
`
`Input/
`Output
`
`Input/
`Output
`
`P40-43
`
`Input/
`Output
`
`P50-53
`
`Input/
`Output
`
`Input/
`Output
`Circuit
`TYPE*
`
`B
`
`F -A
`
`F -B
`
`M -C
`
`4-bit input port (PORT0)
`Pull-up resistors can be specified in 3-bit
`units for the P01 to P03 pins by software.
`
`X
`
`Input
`
`With noise elimination function
`
`4-bit input port (PORT1)
`Internal pull-up resistors can be
`specified in 4-bit units by software.
`
`X
`
`Input
`
`B -C
`
`4-bit input/output port (PORT2)
`Internal pull-up resistors can be
`specified in 4-bit units by software.
`
`Programmable 4-bit input/output port
`(PORT3)
`This port can be specified for input/
`output in bit units.
`Internal pull-up resistors can be
`specified in 4-bit units by software.
`
`N-ch open-drain 4-bit input/output port
`(PORT4)
`Internal pull-up resistors can be
`specified in bit units. (mask option)
`Resistive voltage is 10 V in the open-
`drain mode.
`
`N-ch open-drain 4-bit input/output port
`(PORT5)
`Internal pull-up resistors can be
`specified in bit units. (mask option)
`Resistive voltage is 10 V in the open-
`drain mode.
`
`X
`
`X
`
`ll
`
`Input
`
` E-B
`
`Input
`
` E-B
`
`High level
`(with internal
`pull-up
`resistor) or
`high imped-
`ance
`
`High level
`(with internal
`pull-up
`resistor) or
`high imped-
`ance
`
`M
`
`M
`
`* : Circles indicate Schmitt trigger inputs.
`
`9
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0009
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`3.1
`
`PORT PINS (2/2)
`
`Pin Name Input/Output
`
`Also Served
`As
`
`Function
`
`8-Bit I/O When Reset
`
`Input/
`Output
`Circuit
`TYPE*
`
`Programmable 4-bit input/output port
`(PORT6)
`This port can be specified for input/
`output in bit units.
`Internal pull-up resistors can be
`specified in 4-bit units by software.
`
`ll
`
`4-bit input/output port (PORT7)
`Internal pull-up resistors can be
`specified in 4-bit units by software.
`
`2-bit input/output port (PORT8)
`Internal pull-up resistors can be
`specified in 2-bit units by software.
`
`Input
`
`F -A
`
`Input
`
`F -A
`
`X
`
`Input
`
` E-B
`
`KR0
`
`KR1
`
`KR2
`
`KR3
`
`KR4
`
`KR5
`
`KR6
`
`KR7
`
`— —
`
`P60
`
`P61
`
`P62
`
`P63
`
`P70
`
`P71
`
`P72
`
`P73
`
`P80
`
`P81
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`*: Circles indicate Schmitt trigger inputs.
`
`10
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0010
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`3.2
`
`NON PORT PINS
`
`Pin Name Input/Output
`
`Also Served
`As
`
`Functon
`
`When Reset
`
`TI0
`
`PTO0
`
`PCL
`
`BUZ
`
`SCK
`
`SO/SB0
`
`SI/SB1
`
`INT4
`
`INT0
`
`Input
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`Input/
`Output
`
`Input
`
`Input
`
`P13
`
`P20
`
`P22
`
`P23
`
`P01
`
`P02
`
`P03
`
`P00
`
`P10
`
`Timer/event counter external event pulse Input
`
`Timer/event counter output
`
`Clock output
`
`Fixed frequency output (for buzzer or for trim-
`ming the system clock)
`
`Serial clock input/output
`
`Serial data output
`Serial bus input/output
`Serial data input
`Serial bus input/output
`
`Edge detection vector interrupt input (both
`rising and falling edge detection are effective)
`
`Clock synchronous
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input/
`Output
`Circuit
`TYPE*1
`
`B -C
`
`E-B
`
`E-B
`
`E-B
`
`F -A
`
`F -B
`
`M -C
`
`B
`
`11
`
`Edge detection vector
`interrupt input (detection
`edge can be selected)
`
`Asynchronous
`
`B -C
`
`Edge detection testable
`input (rising edge detection)
`
`Asynchronous
`
`Input
`
`B -C
`
`P11
`
`P12
`
`Input
`
`Input
`
`F -A
`
`F -A
`
`Input
`
`—
`
`—
`
`B
`
`—
`
`—
`
`—
`
`Input
`
`—
`
`—
`
`—
`
`— —
`
`P60-P63
`
`Parallel falling edge detection testable input
`
`P70-P73
`
`Parallel falling edge detection testable input
`
`To connect the crystal/ceramic oscillator to the
`main system clock generator. When inputting the
`external clock, input the external clock to pin X1,
`and the reverse phase of the external clock to pin
`X2.
`To connect the crystal oscillator to the subsystem
`clock generator.
`When the external clock is used, pin XT1 inputs
`the external clock. In this case, pin XT2 must be
`left open.
`
`System reset input
`
`No connection
`
`Positive power supply
`
`GND
`
`—
`
`—
`
`— —
`
`——
`
`INT1
`
`INT2
`
`Input
`
`KR0-KR3
`
`KR4-KR7
`
`Input/
`Output
`
`Input/
`Output
`
`X1, X2
`
`Input
`
`XT1
`
`XT2
`
`Input
`
`—
`
`RESET
`
`Input
`
`— — —
`
`NC *2
`
`VDD
`
`VSS
`
`*1: Circles indicate Schmitt trigger inputs.
`2: When sharing the printed circut board with the m PD75P008, the NC pin must be directly
`connected to VDD (during the emulation).
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0011
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`PIN INPUT/OUTPUT CIRCUITS
`3.3
`The following shows a simplified input/output circuit diagram for each pin of the m PD75008(A).
`
`TYPE A (for TYPE E–B)
`
`TYPE D (for TYPE E
`–
`
`–B, F
`A)
`
`IN
`
`VDD
`
`P–ch
`
`N–ch
`
`VDD
`
`OUT
`
`data
`
`output
`disable
`
`Input buffer of CMOS standard
`
`Push–pull output that can be set in a output
`high–impedance state (both P–ch and N–ch are off)
`
`TYPE B
`
`TYPE E–B
`
`IN
`
`data
`
`output
`disable
`
`VDD
`
`P.U.R.
`
`P–ch
`
`P.U.R.
`enable
`
`Type D
`
`IN/OUT
`
`Type A
`
`Schmitt trigger input with hysteresis characteristics
`
`P.U.R. : Pull–Up Resistor
`
`TYPE B–C
`
`TYPE F–A
`
`VDD
`
`P.U.R.
`
`P–ch
`
`IN
`
`P.U.R.
`enable
`
`data
`
`output
`disable
`
`VDD
`
`P.U.R.
`
`P–ch
`
`P.U.R.
`enable
`
`Type D
`
`IN/OUT
`
`Type B
`
`P.U.R. : Pull–Up Resistor
`
`P.U.R. : Pull–Up Resistor
`
`12
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0012
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`TYPE F–B
`
`output
`disable
`(P)
`
`data
`output
`disable
`
`output
`disable
`(N)
`
`P.U.R.
`enable
`
`VDD
`
`P.U.R.
`
`P–ch
`
`IN/OUT
`
`VDD
`
`P-ch
`
`N-ch
`
`TYPE M–C
`
`data
`
`output
`disable
`
`P.U.R.
`enable
`
`VDD
`
`P.U.R.
`
`P–ch
`
`IN/OUT
`
`N-ch
`
`P.U.R. : Pull–Up Resistor
`
`P.U.R. : Pull–Up Resistor
`
`TYPE M
`
`data
`
`output
`disable
`
`VDD
`
`P.U.R.
`enable
`(Mask option)
`
`IN/OUT
`
`N-ch
`(withstand
` voltage:
` +10 V)
`
`Middle voltage input buffer
`(withstand voltage: +10 V)
`
`P.U.R. : Pull–Up Resistor
`
`13
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0013
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`SELECTION OF MASK OPTION
`3.4
`The following mask operations are available and can be specified for each pin.
`
`Table 3-1 Mask Option Selection
`
`Mask Option
`
`• With pull-up resistor
`
`• Without pull-up resistor
`
`Pin
`
`P40-P43,
`P50-P53
`
`*: Mask option can be specified in bit units.
`
`H
`
`3.5
`
`RECOMMENDED PROCESSING OF UNUSED PINS
`
`Table 3-2 Processing of Unused Pins
`
`Pin
`
`Recommended Connections
`
`P00/INT4
`P01/SCK
`P02/SO/SB0
`P03/SI/SB1
`P10/INT0-P12/INT2
`P13/TI0
`P20/PTO0
`P21
`P22/PCL
`P23/BUZ
`P30-P33
`P40-P43
`P50-P53
`P60-P63
`P70-P73
`P80-P81
`XT1
`XT2
`
`Connect to VSS
`
`Connect to VSS or VDD
`
`Connect to VSS
`
`: Connect to VSS or VDD
`Input
`Output: Open
`
`Connect to VSS or VDD
`Open
`
`14
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0014
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`NOTES ON USING THE P00/INT4, AND RESET PINS
`3.6
`In addition to the functions described in Sections 3.1 PORT PINS and 3.2 NON PORT PINS, an exclusive
`function for setting the test mode, in which the internal fuctions of the m PD75008(A) are tested (solely used
`for IC tests), is provided to the P00/INT4 and (cid:82)(cid:69)(cid:83)(cid:69)(cid:84) pins.
`If a voltage exceeding VDD is applied to either of these pins, the m PD75008 is put into test mode. Therefore,
`even when the m PD75008 is in normal operation, if noise exceeding the VDD is input into any of these pins, the
`m PD75008 will enter the test mode, and this will cause problems for normal operation.
`As an example, if the wiring to the P00/INT4 pin or the (cid:82)(cid:69)(cid:83)(cid:69)(cid:84) pin is long, stray noise may be picked up
`and the above montioned problem may occur.
`Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot
`be avoided, suppress the noise using a capacitor or diode as shown in the figure below.
`
`H
`
`• Connect a diode having a low VF across
`P00/INT4 and RESET, and VDD. (0.3 V max.)
`
`• Connect a capacitor across P00/INT4 and
`RESET, and VDD.
`
`VDD
`
`VDD
`
`Low VF
`diode
`
`VDD
`
`VDD
`
`P00/INT4, RESET
`
`P00/INT4, RESET
`
`15
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0015
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`4. MEMORY CONFIGURATION
`
` 8 bits (0000H-0FFFH) : m PD75004(A)
`• Program memory (ROM) ... 4096 ·
`... 6016 ·
` 8 bits (0000H-177FH) : m PD75006(A)
` 8 bits (0000H-1F7FH) : m PD75008(A)
`... 8064 ·
`• 0000H-0001H : Vector table to which address from which program is started is written after reset
`• 0002H-000BH: Vector table to which address from which program is started is written after interrupt
`• 0020H-007FH : Table area referenced by GETI instruction
`
`• Data memory (RAM)
`• Data area .... 512 ·
` 4 bits (000H–1FFH)
`• Peripheral hardware area .... 128 ·
` 4 bits (F80H–FFFH)
`
`0
`
`Internal reset start address (upper 4 bits)
`
`Internal reset start address (lower 8 bits)
`
`4 0
`
`0
`
`INTBT/INT4 start address (upper 4 bits)
`
`INTBT/INT4 start address (lower 8 bits)
`
`0
`
`INT0 start address (upper 4 bits)
`
`INT0 start address (lower 8 bits)
`
`0
`
`INT1 start address (upper 4 bits)
`
`INT1 start address (lower 8 bits)
`
`0
`
`INTCSI start address (upper 4 bits)
`
`INTCSI start address (lower 8 bits)
`
`0
`
`INTT0 start address (upper 4 bits)
`
`INTT0 start address (lower 8 bits)
`
`Address
`
`7
`
`6
`
`000H
`
`MBE 0
`
`002H
`
`MBE 0
`
`004H
`
`MBE 0
`
`006H
`
`MBE 0
`
`008H
`
`MBE 0
`
`00AH
`
`MBE 0
`
`5
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`GETI instruction reference table
`
`020H
`
`07FH
`080H
`
`7FFH
`800H
`
`FFFH
`
`16
`
`CALLF
`!faddr
`instruction
`entry
`address
`
`CALL ! addr
`instruction
`subroutine
`entry address
`
`BRCD ! caddr
`instruction
`branch address
`
`BR $addr
`instruction
`relational
`branch address
`(–15 to –1,
`+2 to +16)
`
`Branch destination
`address and
`subroutine entry
`address for
`GETI instruction
`
`Fig. 4-1 Program Memory Map (m PD75004(A))
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0016
`
`

`
`Address
`
`7
`
`6
`
`0000H
`
`MBE 0
`
`5
`
`0
`
`Internal reset start address (upper 5 bits)
`
`Internal reset start address (lower 8 bits)
`
`0
`
`0002H
`
`MBE 0
`
`0
`
`INTBT/INT4 start address (upper 5 bits)
`
`INTBT/INT4 start address (lower 8 bits)
`
`0004H
`
`MBE 0
`
`0
`
`INT0 start address (upper 5 bits)
`
`INT0 start address (lower 8 bits)
`
`0006H
`
`MBE 0
`
`0
`
`INT1 start address (upper 5 bits)
`
`INT1 start address (lower 8 bits)
`
`0008H
`
`MBE 0
`
`0
`
`INTCSI start address (upper 5 bits)
`
`INTCSI start address (lower 8 bits)
`
`000AH
`
`MBE 0
`
`0
`
`INTT0 start address (upper 5 bits)
`
`INTT0 start address (lower 8 bits)
`
`GETI instruction reference table
`
`0020H
`
`007FH
`0080H
`
`07FFH
`0800H
`
`0FFFH
`1000H
`
`177FH
`
`m PD75004(A), 75006(A), 75008(A)
`
`CALLF
`! faddr
`instruction
`entry
`address
`
`CALL ! addr
`instruction
`subroutine
`entry address
`
`BRCB
`! caddr
`instruction
`branch
`address
`
`BR ! addr
`instruction
`branch address
`
`BR $addr
`instruction
`relational
`branch address
`(–15 to –1,
`+2 to +16)
`
`Branch destination
`address and
`subroutine entry
`address for
`GETI instruction
`
`BRCB ! caddr
`instruction
`branch address
`
`Fig. 4-2 Program Memory Map (m PD75006(A))
`
`17
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0017
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`CALLF
`! faddr
`instruction
`entry
`address
`
`CALL ! addr
`instruction
`subroutine
`entry address
`
`BRCB
`! caddr
`instruction
`branch
`address
`
`BR ! addr
`instruction
`branch address
`
`BR $addr
`instruction
`relational
`branch address
`(–15 to –1,
`+2 to +16)
`
`Branch destination
`address and
`subroutine entry
`address for
`GETI instruction
`
`BRCB ! caddr
`instruction
`branch address
`
`Fig. 4-3 Program Memory Map (m PD75008(A))
`
`Address
`
`7
`
`6
`
`0000H
`
`MBE 0
`
`5
`
`0
`
`Internal reset start address (upper 5 bits)
`
`Internal reset start address (lower 8 bits)
`
`0
`
`0002H
`
`MBE 0
`
`0
`
`INTBT/INT4 start address (upper 5 bits)
`
`INTBT/INT4 start address (lower 8 bits)
`
`0004H
`
`MBE 0
`
`0
`
`INT0 start address (upper 5 bits)
`
`INT0 start address (lower 8 bits)
`
`0006H
`
`MBE 0
`
`0
`
`INT1 start address (upper 5 bits)
`
`INT1 start address (lower 8 bits)
`
`0008H
`
`MBE 0
`
`0
`
`INTCSI start address (upper 5 bits)
`
`INTCSI start address (lower 8 bits)
`
`000AH
`
`MBE 0
`
`0
`
`INTT0 start address (upper 5 bits)
`
`INTT0 start address (lower 8 bits)
`
`GETI instruction reference table
`
`0020H
`
`007FH
`0080H
`
`07FFH
`0800H
`
`0FFFH
`1000H
`
`1F7FH
`
`18
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0018
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`General-purpose
`register area
`
`Stack area
`
`Data area
`Static RAM
`(512 · 4)
`
`Peripheral hardware area
`
`Data memory
`
`Memory bank
`
`(8 · 4)
`
`256· 4
`(248 · 4)
`
`256· 4
`
`0
`
`1
`
`Not provided
`
`128· 4
`
`15
`
`000H
`
`007H
`
`008H
`
`0FFH
`
`100H
`
`1FFH
`
`F80H
`
`FFFH
`
`Fig. 4-4 Data Memory Map
`
`19
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0019
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`5. PERIPHERAL HARDWARE FUNCTIONS
`
`PORTS
`5.1
`I/O ports are classified into the following 3 kinds:
`• CMOS input (PORT0, 1)
`: 8
`• CMOS input/output (PORT2, 3, 6, 7, and 8) : 18
`• N-ch open-drain input/output (PORT4, 5)
`: 8
`Total
`
`: 34
`
`Table 5-1 Port Function
`
`Port Name
`
`Function
`
`Operation and Feature
`
`Remarks
`
`PORT0
`PORT1
`
`PORT3
`PORT6
`
`PORT2
`PORT7
`
`PORT4
`PORT5
`
`4-bit input
`
`Can be always read or tested regardless of opera-
`tion mode of multiplexed pin.
`
`Can be set in input or output mode in 1-bit units.
`
`4-bit input/output
`
`Can be set in input or output mode in 4-bit units.
`Ports 6 and 7 are used in pairs to input/output data
`in 8-bit units.
`
`4-bit input/output
`(N-ch open-drain,
`10 V)
`
`Can be set in input or output mode in 4-bit units.
`Ports 4 and 5 are used in pairs to input/output data
`in 8-bit units.
`
`Multiplexed with SO/SB0,
`SI/SB1, SCK, INT0-2, 4,
`and TIO
`
`Port 6 is multiplexed with
`KR0 to KR3.
`
`Port 2 is multiplexed with
`PTO0, PCL, and BUZ.
`
`Port 7 is multiplexed with
`KR4-KR7.
`
`Can be connected to a
`pull-up resistor in 1-bit
`units by using mask
`option.
`
`PORT8
`
`2-bit input/output
`
`Can be set input or output mode in 2-bit units.
`
`—
`
`20
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0020
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`CLOCK GENERATOR CIRCUIT
`5.2
`The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and
`system clock control register (SCC).
`This circuit can generate two types of clocks: main system clock and subsystem clock.
`In addition, it can also change the instruction execution time.
`
`• 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 MHz)
`• 122 m s (subsystem clock: 32.768 kHz)
`
`Subsystem
`clock
`oscillator
`
`f XT
`
`Watch timer
`
`· Basic interval timer (BT)
`· Timer/event counter
`· Serial interface
`· Watch timer
`· INT0 noise rejecter circuit
`· Clock output circuit
`
`Main system
`clock
`oscillator
`
`f X
`
`1/8 to 1/4096
`Frequency divider
`1/2 1/16
`
`Frequency
`divider
`1/4
`
`Selector
`
`Selector
`
`Oscillator
`disable
`signal
`
`· CPU
`· INT0 noise
` rejecter circuit
`· Clock output
` circuit
`
`Wait release
`signal from BT
`
`RESET signal
`Standby release
`signal from interrupt
`control circuit
`
`HALT F/F
`
`Q
`
`S R
`
`XT1
`
`XT2
`
`X1
`
`X2
`
`WM.3
`SCC
`SCC3
`
`SCC0
`
`PCC
`
`PCC0
`
`PCC1
`
`PCC2
`
`PCC3
`
`4
`
`HALT*
`
`STOP*
`
`Internal bus
`
`PCC2, PCC3
`clear signal
`
`STOP F/F
`Q S
`
`R
`
`*: instruction execution.
`
`Remarks 1: fX = Main system clock frequency
`2: fXT = Subsystem clock frequency
`F = CPU clock
`3:
`4: PCC: Processor clock control register
`5: SCC: System clock control register
`6: One clock cysle (tCY) of F
` is one machine cycle of an instruction. For tCY, refer to AC
`characteristics in 10. ELECTRICAL SPECIFICATIONS.
`
`Fig. 5-1 Clock Generator Block Diagram
`
`21
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0021
`
`F
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`CLOCK OUTPUT CIRCUIT
`5.3
`The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output
`clock pulses to the remote control output, peripheral LSIs, etc.
`: F
`• Clock output (PCL)
`, 524, 262, 65.5 kHz (operating at 4.19 MHz)
`• Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz, or 32.768 kHz)
`
`Fig. 5-2 shows the clock output circuit configuration.
`
`From the
`clock
`generator
`
`fX/23
`
`fX/24
`
`fX/26
`
`Selector
`
`Output
`buffer
`
`PCL/P22
`
`CLOM3 CLOM2 CLOM1 CLOM0 CLOM
`
`P22 output
`latch
`
`Port 2 input/
`output mode
`specification
`bit
`
`PORT2.2
`
`Bit 2 of PMGB
`
`4
`
`Internal bus
`
`Fig. 5-2 Clock Output Circuit Configuration
`
`Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/
`disable is taken.
`
`22
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0022
`
`F
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`BASIC INTERVAL TIMER
`5.4
`The basic interval timer has these functions:
`• Interval timer operation which generates a reference time interrupt
`• Watchdog timer application which detects a program runaway
`• Selects the wait time for releasing the standby mode and counts the wait time
`• Reads out the count value
`
`From the
`clock generator
`
`fX/25
`
`fX/27
`
`fX/29
`
`fX/212
`
`MPX
`
`3
`
`Clear
`
`Clear
`
`Basic interval timer
`(8-bit frequency divider circuit)
`
`Set
`signal
`
`BT
`interrupt
`request flag
`
`BT
`
`IRQBT
`
`Wait release signal
`for standby release
`
`Vector
`interrupt
`request
`signal
`
`BTM3
`
`BTM2
`
`BTM1
`
`BTM0
`
`BTM
`
`SET1*
`
`4
`
`8
`
`Internal bus
`
`Remarks : *: Instruction execution
`
`Fig. 5-3 Basic Interval Timer Configuration
`
`23
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0023
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`5.5 WATCH TIMER
`The m PD75008(A) has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.
`• Sets the test flag (IRQW) with 0.5 sec interval.
`The standby mode can be released by IRQW.
`• 0.5 second interval can be generated either from the main system clock or subsystem clock.
`• Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient
`for program debugging, test, etc.
`• Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock
`frequency trimming.
`• The frequency divider circuit can be cleared so that zero second watch start is possible.
`
`f W
`2 7 (256 Hz: 3.91 ms)
`
`From the
`clock
`generator
`
`f X
`128
`(32.768 kHz)
`f XT
`(32.768 kHz)
`
`Selector
`
`f W
`(32.768
` kHz)
`
`Frequency divider
`
`f W
`16
`
`(2.048
` kHz)
`
`Clear
`
`INTW
`(IRQW
`set signal)
`
`Selector
`
`f W
`2 14
`(2 Hz
`0.5 sec)
`
`Output buffer
`P23/BUZ
`
`WM
`
`WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
`
`PORT2.3
`
`Bit 2 of PMGB
`
`P23
`output
`latch
`
`Port 2
`input/output
`mode
`
`8
`
`Bit test
`instruction
`
`Internal bus
`
`( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
`
`Fig. 5-4 Watch Timer Block Diagram
`
`TIMER/EVENT COUNTER
`5.6
`The m PD75008(A) has a built-in 1-ch timer/event counter. The timer/even counter has these functions:
`• Programmable interval timer operation
`• Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.
`• Event counter operation
`• Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).
`• Supplies serial shift clock to the serial interface circuit.
`• Count condition read out function
`
`24
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0024
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`8
`
`1
`SET1*
`
`TM0
`
`8
`
`8
`
`TMOD0
`
`TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
`
`Modulo register (8)
`
`Internal bus
`
`PORT1.3
`
`Input
`buffer
`
`P13/TI0
`
`8
`
`Comparator (8)
`
`8
`
`Coinci-
`dence
`
`TOUT
`F/F
`
`Reset
`
`T0
`
`2*
`From
`the clock
`generator
`
`MPX
`
`Count register (8)
`
`CP
`
`Clear
`
`Timer operation start signal
`
`TOE0
`
`PORT2.0
`
`TO
`enable
`flag
`
`P20
`output
`latch
`
`Bit 2 of PGMB
`Port 2
`input/
`output
`mode
`To serial interface
`
`P20/PTO0
`
`Output
`buffer
`
`INTT0
`IRQT0
`set signal
`
`)
`
`(
`
`RESET
`IRQT0
`clear signal
`
`Fig. 5-5 Timer/Event Counter Block Diagram
`
`*1: SET1: Instruction execution
`*2: Refer to Fig. 5-1.
`
`25
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0025
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`SERIAL INTERFACE
`5.7
`m PD75008(A) is equipped with an 8-bit clocked serial interface, which can operate in the following three modes:
`• Three-line serial I/O mode (MSB/LSB first selectable)
`• Two-line serial I/O mode (MSB first)
`• SBI mode (MSB first)
`
`In the three-line I/O mode, the microcomputer can be connected to a microcomputer in the 75X series or 78K
`series devices, or various I/O devices. In the two-line serial mode and SBI mode, communication can be established
`with two or more devices.
`
`26
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0026
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`Internal bus
`
`8
`
`Bit manipulation
`
`Bit test
`
`8
`
`8
`
`SBIC
`
`Slave address register
`(SVA)
`
`(8)
`
`Coincidence
`signal
`Address comparator
`(8)
`
`Shift register (SIO)
`
`(8)
`
`RELT
`CMDT
`
`SO latch
`
`SET CLR
`
`D
`
`Q
`
`INTCSI
`IRQCSI
`set signal
`
`)
`
`(
`
`fX/23
`fX/24
`fX/26
`TOUT F/F
`(from timer/
`event counter)
`External SCK
`
`BSYE
`ACKE
`ACKT
`
`Busy/
`acknowledge
`output
`circuit
`
`Serial clock
`selector
`
`RELD
`CMDD
`ACKD
`
`INTCSI
`control
`circuit
`
`Bus release/
`command/
`acknowledge
`detector
`circuit
`
`Serial clock
`counter
`
`Serial clock
`control
`circuit
`
`8/4
`
`Bit
`test
`
`CSIM
`
`Selector
`
`Selector
`
`P01
`output
`latch
`
`P03/SI/SB1
`
`P02/SO/SB0
`
`P01/SCK
`
`Fig. 5-6 Serial Interface Block Diagram
`
`27
`
`Petitioner Toyota Motor Corp. Exhibit 1113
`1113.0027
`
`

`
`m PD75004(A), 75006(A), 75008(A)
`
`BIT SEQUENTIAL BUFFER .... 16 BITS
`5.8
`The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
`addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
`buffer is very useful for processing long data in bit units.
`
`Address bit
`
`FC3H
`
`FC2H
`
`FC1H
`
`FC0H
`
`3
`
`2
`
`1
`
`0
`
`3
`
`2
`
`1
`
`0
`
`3
`
`2
`
`1
`
`0
`
`3
`
`2
`
`1
`
`0
`
`Symbol
`
`BSB3
`
`BSB2
`
`BSB1
`
`BSB0
`
`L register
`
`L = F
`
`L = C L = B
`
`L = 8 L = 7
`
`L = 4 L = 3
`
`L = 0
`
`INCS L
`
`DECS L
`
`Remarks: For the pmem.@L addressing, the specification bit is shifted according to the