Paper No. __
`Filed: December 28, 2015
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.
`Petitioner
`
`v.
`
`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Patent No. 8,841,778
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,841,778
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`
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
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`TABLE OF CONTENTS
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`INTRODUCTION ........................................................................................... 1
`
`
`I.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1
`
`III.
`
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 2
`
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a) ..................... 2
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`V.
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`PRECISE RELIEF REQUESTED AND GROUNDS RAISED ..................... 3
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`VI. LEVEL OF ORDINARY SKILL IN THE ART ............................................. 4
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`VII. THE ’778 PATENT ......................................................................................... 5
`
`A.
`
`B.
`
`C.
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`Technical Background ........................................................................... 5
`
`Overview of the ’778 Patent .................................................................. 6
`
`Prosecution History of the ’778 Patent ................................................. 8
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`VIII. CLAIM CONSTRUCTION ............................................................................ 9
`
`A.
`
`B.
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`“semiconductor substrate” is “substantially flexible” ........................... 9
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`“substantially flexible circuit layer” .................................................... 13
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`IX. DETAILED EXPLANATION OF GROUNDS UNDER THE
`BROADEST REASONABLE CONSTRUCTIONS .................................... 15
`
`A. Overview of the Prior Art References ................................................. 15
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`1.
`
`2.
`
`3.
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`4.
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`5.
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`Bertin ......................................................................................... 15
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`Hsu ............................................................................................ 16
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`Poole ......................................................................................... 17
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`Leedy ’695 ................................................................................. 17
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`Kowa ......................................................................................... 19
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`-i-
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`Ground 1: Bertin and Leedy ’695 Render Obvious Claims 1 and
`14 ......................................................................................................... 19
`
`B.
`
`1.
`
`2.
`
`3.
`
`Overview of Combination and Reasons to Combine ............... 19
`
`Claim 1 ...................................................................................... 23
`
`Claim 14 .................................................................................... 27
`
`C.
`
`Ground 2: Bertin, Poole, and Leedy ’695 Render Obvious
`Claims 2, 8, 31, 32, 44, 46, 52, 53, and 54 .......................................... 32
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Overview of Combination and Reasons to Combine ............... 32
`
`Claim 2 ...................................................................................... 35
`
`Claim 8 ...................................................................................... 37
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`Claim 31 .................................................................................... 40
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`Claim 32 .................................................................................... 41
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`Claim 44 .................................................................................... 42
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`Claim 46 .................................................................................... 42
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`Claim 52 .................................................................................... 43
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`Claim 53 .................................................................................... 43
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`10. Claim 54 .................................................................................... 43
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`D. Ground 3: Hsu and Leedy ’695 Render Obvious Claims 1, 2, 8,
`14, 31, 32, 44, 46, and 52-54 ............................................................... 44
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Overview of the Combinations and Reasons to Combine ........ 44
`
`Claim 1 ...................................................................................... 47
`
`Claim 2 ...................................................................................... 50
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`Claim 8 ...................................................................................... 51
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`Claim 14 .................................................................................... 53
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`-ii-
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`Claim 31 .................................................................................... 55
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`Claim 32 .................................................................................... 55
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`Claim 44 .................................................................................... 56
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`Claim 46 .................................................................................... 56
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`6.
`
`7.
`
`8.
`
`9.
`
`10. Claim 52 .................................................................................... 56
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`11. Claim 53 .................................................................................... 56
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`12. Claim 54 .................................................................................... 57
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`X. DETAILED EXPLANATION OF GROUNDS UNDER
`ALTERNATIVE CONSTRUCTIONS ......................................................... 57
`
`A.
`
`B.
`
`Low Stress Dielectrics Terms ............................................................. 57
`
`Substantially Flexible Terms ............................................................... 58
`
`XI. THE PROPOSED GROUNDS ARE NOT REDUNDANT ......................... 59
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`XII. CONCLUSION .............................................................................................. 60
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`-iii-
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`
`LIST OF EXHIBITS1
`Ex. 1001: U.S. Patent No. 8,841,778
`
`Ex. 1002: Declaration of Dr. Paul D. Franzon
`
`Ex. 1003:
`
`Curriculum Vitae of Dr. Paul D. Franzon
`
`Ex. 1004: U.S. Patent No. 5,202,754 to Bertin et al., issued April 13, 1993
`
`Ex. 1005: U.S. Patent No. 5,162,251 to Poole et al., issued November 10, 1992
`
`Ex. 1006: U.S. Patent No. 5,354,695 to Leedy, issued October 11, 1994
`
`Ex. 1007:
`
`Japanese Patent Publication No. 3-151337 to Kowa including
`Japanese-language version, English-language translation, and
`translation certification
`
`Ex. 1008: U.S. Patent No. 5,627,106 to Hsu, issued May 6, 1997
`
`Ex. 1009:
`
`RESERVED
`
`Ex. 1010:
`
`RESERVED
`
`Ex. 1011:
`
`RESERVED
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`Ex. 1012:
`
`RESERVED
`
`Ex. 1013:
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`RESERVED
`
`Ex. 1014:
`
`RESERVED
`
`Ex. 1015:
`
`RESERVED
`
`Ex. 1016:
`
`RESERVED
`
`Ex. 1017:
`
`Prosecution History for U.S. Patent No. 8,841,778
`
`
`
` 1
`
` Citations to non-patent publications are to the original page numbers of the
`
`publication, and citations to U.S. patents are to column:line number of the patents.
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`iv
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`Prosecution History of U.S. Patent No. 8,907,499 - Office Action
`dated May 29, 2013
`
`Prosecution History of U.S. Patent No. 8,907,499 - Response to
`Office Action dated June 20, 2013
`
`Prosecution History of U.S. Patent No. 8,907,499 - As-Filed Patent
`Application
`
`Prosecution History of U.S. Patent App. No. 12/497,652 - Response
`to Office Action dated September 26, 2013
`
`Prosecution History of U.S. Patent App. No. 12/497,653 - Response
`to Office Action dated October 24, 2013
`
`Prosecution History of U.S. Patent App. No. 12/497,652 - Response
`to Office Action dated 4/5/13
`
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated April 28, 1998
`
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated September 8, 1998
`
`Prosecution History of U.S. Patent No. 8,629,542 - Response to
`Office Action dated July 30, 2012
`
`Ex. 1018:
`
`Ex. 1019:
`
`Ex. 1020:
`
`Ex. 1021:
`
`Ex. 1022:
`
`Ex. 1023:
`
`Ex. 1024:
`
`Ex. 1025:
`
`Ex. 1026:
`
`Ex. 1027:
`
`RESERVED
`
`Ex. 1028:
`
`Ex. 1029:
`
`Ex. 1030:
`
`Ex. 1031:
`
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated February 16, 2009
`
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated June 25, 2009
`
`Prosecution History of U.S. Patent No. 8,928,119 - Response to
`Office Action dated September 4, 2012
`
`Prosecution History of U.S. Patent No. 8,928,119 - Appeal Brief
`dated June 3, 2013
`
`Ex. 1032:
`
`Prosecution History of U.S. Patent No. 8,410,617 - Response to
`
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`
`Office Action dated December 14, 2010
`
`Ex. 1033:
`
`Ex. 1034:
`
`Ex. 1035:
`
`Ex. 1036:
`
`Prosecution History of U.S. Patent Application No. 12/497,652 -
`Final Office Action dated August 27, 2014
`
`Prosecution History of U.S. Patent Application No. 12/497,652 -
`Express Abandonment dated November 20, 2014
`
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Advisory Action dated August 27, 2014
`
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Express Abandonment dated November 20, 2014
`
`Ex. 1037:
`
`RESERVED
`
`Ex. 1038:
`
`RESERVED
`
`Ex. 1039:
`
`Concept One CVD System Process Specifications from Novellus
`
`Ex. 1040: Wolf et al., Processing for the VLSI Era, Volume 1 - Process
`Technology (1986).
`
`Ex. 1041: U.S. Patent No. 3,508,980 to Jackson et al., issued April 28, 1970
`
`Ex. 1042: U.S. Patent No. 3,044,909 to Shockley, issued July 17, 1962
`
`Ex. 1043:
`
`Fahey et al., Stress-induced dislocations in silicon integrated
`circuits, IBM J. Res. Develop. Vol. 36, No. 2, March 1992
`
`Ex. 1044: Hass et al., Physics of Thin Films: Advances in Research and
`Development (1966)
`EerNisse, E.P., Stress in thermal SiO2 during growth, Appl. Phys.
`Lett. 35(1), July 1, 1979
`
`Ex. 1045:
`
`Ex. 1046: Klokholm, Erik, Delamination and fracture of thin films, IBM J. Res.
`Develop., Vol. 31, No. 5, September 1987
`
`Ex. 1047: U.S. Patent No. 4,948,482 to Kobayashi et al., issued August 14,
`1990
`
`Ex. 1048:
`
`Isobe et al., Dielectric Film Influence on Stress-Migration, June 12-
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`Petition for Inter Partes Review
`Patent No. 8,841,778
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`13 IEEE VMIC Conference (1990)
`
`Ex. 1049: Van de Ven, et al., Advantages of Dual Frequency PECVD for
`Deposition of ILD and Passivation Films, June 12-13 IEEE VMIC
`Conference (1990)
`
`Ex. 1050: U.S. Patent No. 5,160,998 to Itoh et al., issued November 3, 1992
`
`Ex. 1051: Garrou, Philip, Polymer Dielectrics for Multichip Module Packaging,
`Proceedings of the IEEE, Vol. 80, No. 12, December 12, 1992
`
`Ex. 1052: Grief et al., Warpage and Mechanical Strength Studies of Ultra Thin
`150MM Wafers, IEEE/CPMT Int’l Electronics Manufacturing
`Technology Symposium (1996)
`
`Ex. 1053:
`
`Tatsuno, Sheridan, Japan’s Push into Creative Semiconductor
`Research: 3-Dimensional ICs, Solid State Technology, March 1987
`
`Ex. 1054: Akasaka, Yoichi, Three-Dimensional IC Trends, Proceedings of the
`IEEE, Vol. 74, No. 12, December 1986
`
`Ex. 1055: Hayashi, Yoshihiro, Evaluation of Cubic (Cumulatively Bonded IC)
`Devices, 9th Symposium on Future Electron Devices, November 14-
`15, 1990
`
`Ex. 1056: Williams et al., Future WSI Technology: Stacked Monolithic WSI,
`IEEE Transactions on Components, Hybrids, and Manufacturing
`Technology, Vol. 16, No. 7, November 1993
`
`Ex. 1057:
`
`Crowley et al., 3-D Multichip Packaging for Memory Modules,
`MCM ’94 Proceedings, 1994
`
`Ex. 1058: Malinak, David, Memory-Chip Stacks Send Density Skyward,
`Electronic Design, August 22, 1994
`
`Ex. 1059: Kuhn et al., Interconnect Capacitances, Crosstalk, and Signal Delay
`in Vertically Integrated Circuits, IEEE 1995
`
`
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`vii
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd.; Micron Technology, Inc.; and SK hynix, Inc.
`
`(collectively, “Petitioner”) request inter partes review (“IPR”) of claims 1, 2, 8, 14,
`
`31, 32, 44, 46, and 52-54 (“Challenged Claims”) of U.S. Patent No. 8,841,778
`
`(“’778 patent”) (Ex. 1001), assigned to Elm 3DS Innovations, LLC (“PO”). This
`
`Petition shows there is a reasonable likelihood that Petitioner will prevail as to the
`
`Challenged Claims based on prior art not before the U.S. Patent and Trademark
`
`Office (“PTO”) or not fully considered during prosecution. Accordingly, this
`
`petition should be granted on all grounds and the Challenged Claims should be
`
`cancelled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: The real parties in interest are: Samsung
`
`Electronics Co., Ltd.; Samsung Semiconductor, Inc.; Samsung Electronics
`
`America, Inc.; Samsung Austin Semiconductor, LLC; Micron Technology, Inc.;
`
`Micron Semiconductor Products, Inc.; Micron Consumer Products Group, Inc.; SK
`
`hynix Inc.; SK hynix America, Inc.; Hynix Semiconductor Manufacturing
`
`America, Inc.; and SK hynix Memory Solutions, Inc.
`
`Related Matters: PO has asserted the ’778 patent against Petitioner in Elm
`
`3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-cv-01430 (D. Del.); Elm
`
`3DS Innovations, LLC v. Micron Tech., Inc., No. 1:14-cv-01431 (D. Del.); and Elm
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`1
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`3DS Innovations, LLC v. SK hynix Inc., No. 1:14-cv-01432 (D. Del.). PO has also
`
`asserted related U.S. Patent Nos. 7,193,239; 7,474,004; 7,504,732; 8,035,233;
`
`8,410,617; 8,653,672; 8,791,581; 8,796,862; 8,629,542; 8,907,499; 8,928,119; and
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`8,933,570 in one or more of these actions. Petitioner is concurrently filing IPR
`
`petitions for some of these related patents. Petitioner is unaware of any U.S.
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`Patents or patent applications that claim priority to the ’778 patent.
`
`Counsel and Service Information: Lead counsel is Jason Engel (Reg. No.
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`51,654), K&L Gates LLP, 70 W. Madison St., Suite 3100, Chicago, IL 60602,
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`Tel.: 312.807.4236, Fax: 312.827.8145, e-mail: jason.engel.PTAB@klgates.com;
`
`and backup counsel is Naveen Modi (Reg. No. 46,224), Paul Hastings LLP, 875
`
`15th St. N.W., Washington, D.C., 20005, Tel.: 202.551.1700, Fax: 202.551.1705,
`
`email: PH-Samsung-ELM-IPR@paulhastings.com; and John Kappos (Reg. No.
`
`37,861), O’Melveny & Myers LLP, 610 Newport Center Drive, 17th Floor,
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`Newport Beach, California 92660, Tel.: 949.823.6900, Fax: 949.823.6994, email:
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`jkappos@omm.com. Petitioner consents to electronic service by email.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The required fees are submitted herewith. Petitioner authorizes the PTO to
`
`charge any additional fees to Deposit Account No. 02-1818.
`
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a)
`Petitioner certifies that the ’778 patent is available for IPR and Petitioner is
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`2
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`not barred or estopped from requesting IPR on the grounds identified herein.2
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`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED
`
`Petitioner requests IPR and cancellation of the Challenged Claims based on
`
`the grounds listed below. Part VIII explains how certain claim terms should be
`
`construed. Part IX explains in detail the following grounds, which show why the
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`prior art teaches or suggests every feature of the Challenged Claims, as construed
`
`by Petitioner: Ground 1: Claims 1 and 14 are obvious under 35 U.S.C. § 103(a)
`
`over U.S. Patent No. 5,202,754 (“Bertin”) (Ex. 1004) and U.S. Patent No.
`
`5,354,695 (“Leedy ’695”) (Ex. 1006); Ground 2: Claims 2, 8, 31, 32, 44, 46, and
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`52-54 are obvious under 35 U.S.C. § 103(a) over Bertin, Leedy ’695, and U.S.
`
`Patent No. 5,162,251 (“Poole”) (Ex. 1005); and Ground 3: The Challenged
`
`Claims are obvious under 35 U.S.C. § 103(a) over U.S. Patent No. 5,627,106
`
`(“Hsu”) (Ex. 1008) and Leedy ’695.
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`Part X explains why the Grounds in Part IX and the following additional
`
`ground render the Challenged Claims obvious under certain alternate claim
`
`constructions: Ground 4: The Challenged Claims are obvious under 35 U.S.C. §
`
`
`
` 2
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` This petition is timely filed under 35 U.S.C. § 21 because the PTO considered
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`December 22-24, 2015, to be a “Federal holiday within the District of Columbia.”
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`103(a) over Hsu in view of Japanese Pub. H3-151637 (“Kowa”) (Ex. 1007)3; and
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`Ground 5: Claims 2, 8, and 52 are obvious under 35 U.S.C. § 103(a) over Bertin
`
`in view of Leedy ’695.
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`The ’778 patent contains a priority claim to April 4, 1997, and Petitioner
`
`assumes this priority date for purposes of this proceeding only. Bertin issued on
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`April 13, 1993, Poole issued on November 10, 1992, Leedy ’695 issued on October
`
`11, 1994, and Kowa published on June 27, 1991. These references are prior art
`
`under 35 U.S.C. § 102(b). Hsu was filed on May 6, 1994, and issued on May 6,
`
`1997, and is therefore prior art at least as of May 6, 1994 under 35 U.S.C. § 102(e).
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention of
`
`the ’778 patent would have had at least a B.S. degree in electrical engineering,
`
`material science, or equivalent thereof, and at least 3-5 years of experience in the
`
`relevant field, e.g., semiconductor processing.4 Ex. 1002 at ¶¶52-53.
`
`
`
` 3
`
` Ex. 1007 is a compilation containing the Japanese-language version of Kowa (id.
`
`at 1-5), followed by an English-language translation of Kowa (id. at 6-12). The
`
`affidavit required by 37 C.F.R. §42.63(b) (in the form of a declaration as permitted
`
`by 37 C.F.R. §42.2) follows the English-language translation. Id. at 13.
`
`4 The declaration of Dr. Paul D. Franzon (Ex. 1002), an expert in the field of the
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`4
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`
`VII. THE ’778 PATENT
`A. Technical Background
`ICs are typically fabricated on a thin slice of silicon (a wafer) and
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`“singulated” into individual devices (dice). Ex. 1002 at ¶17; see also id. at ¶¶18-
`
`19. A basic two-dimensional (“2D”) integrated circuit (“IC”) has a single, active
`
`circuit layer mounted in a package in a single plane. Id. Since the IC’s creation in
`
`1958, designers have worked to improve computing power and efficiency of
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`electronic structures. Id. at ¶¶20, 56, 67-68.
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`IC designers have long thinned and polished substrates to create thin
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`electronic circuits that could fit in ever-smaller devices. Id. at ¶21. Designers have
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`also long relied on vertical interconnections to connect different vertical levels
`
`within an IC. Id. at ¶22. While reliability has always been a concern, many of the
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`processes used in the fabrication of silicon ICs impose stress on silicon substrates
`
`that unacceptably affect the yield. Id. at ¶23. Consequently, substantial efforts have
`
`been made to study and improve stress management, including the use of low
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`tensile stress materials and stress balancing. Id. at ¶¶24-37. By 1996, it was well
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`known to thin and polish wafers, use TSVs to electrically connect layers in an IC,
`
`
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`’778 patent (id. at ¶¶1-16, 74, 78, 123, 135, 152), and his CV (Ex. 1003) is
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`submitted herewith.
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`Petition for Inter Partes Review
`Patent No. 8,841,778
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`and to manage stress. Id. at ¶38; see also id. at ¶¶22-37.
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`As performance enhancement
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`through miniaturization became more
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`challenging, three-dimensional (“3D”) ICs became one way to improve efficiency.
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`Id. at ¶39. The benefits of 3D ICs have been known for over 30 years. Id. at ¶¶40-
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`43, 67. Not surprisingly, IC designers carried 2D techniques into 3D designs; these
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`techniques included thinning and polishing (id. at ¶¶44-46, 51), TSVs to connect
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`active device layers (id. at ¶¶44, 47-51), and stress management (id. at ¶51).
`
`B. Overview of the ’778 Patent
`The ’778 patent generally describes “stacked integrated circuit memory” Ex.
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`1001 at 1:7-8, 3:1-11; Ex. 1002 at ¶¶ 55-57, 67. A majority of the claims, however,
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`are not explicitly limited to memory circuits, and broadly recite “circuit layers.”
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`See, e.g., Ex. 1001 at 12:58; Ex. 1002 at ¶¶54-55, 58.
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`The ’778 patent describes “two principal fabrication methods,” referred to as
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`“Method A” and “Method B.” Ex. 100 at 7:19-11:1. These methods include
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`thinning substrates, bonding substrates to form a vertical stack, and forming
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`vertical interconnections passing through the substrates. See id.; Ex. 1002 at ¶57.
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`The primary differences between the methods are whether a transfer substrate is
`
`used for thinning and vertical interconnect processing, and whether each substrate
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`is bonded to the stack such that its topside faces down or up. Compare Ex. 1001 at
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`8:65-10:3 with id. at 10:28-67. Ex. 1002 at ¶¶60-61.
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`Regarding thinning, the ’778 patent describes a step of “[g]rind[ing] the
`
`backside or exposed surface of the second circuit substrate to a thickness of less
`
`than 50 µm and then polish[ing] or smooth[ing] the surface,” (id. at 9:5-8; see also
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`id. at 10:44; Ex. 1002 at ¶62), but explains that other well-known thinning
`
`techniques can be employed instead (Ex. 1001 at 9:9-34; see also id. at 10:44). By
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`thinning the substrate to a thickness of less than 50 μm and then polishing or
`
`smoothing the surface, “[t]he thinned substrate is now a substantially flexible
`
`substrate.” Id. at 9:5-8; see also id. at 3:5-9. Thereafter, the backside of the
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`substrate is processed using conventional techniques to form interconnections that
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`pass through the substrate. Id. at 9:35-10:3, Fig. 4. The substrates are preferably
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`bonded together using thermal diffusion metal bonding, but use of other well-
`
`known bonding methods and material is contemplated. Id. at 7:43-45; see also id.
`
`at 6:36-44, 7:60-8:35, 9:41-49. Ex 1002 at ¶¶59, 63.
`
`The ’778 patent recites the use of low tensile stress dielectrics. See, e.g., Ex.
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`1001 at 8:47-64; Ex. 1002 at ¶66. Such dielectrics, however, are admitted 35
`
`U.S.C. 102(b) prior art attributable to the named inventor:
`
`The thinned (substantially flexible) substrate circuit layers are
`preferably made with dielectrics in low stress (less than 5×108
`dynes/cm2) such as low stress silicon dioxide and silicon nitride
`dielectrics as opposed to the more commonly used higher stress
`dielectrics of silicon oxide and silicon nitride used in conventional
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`Petition for Inter Partes Review
`Patent No. 8,841,778
`memory circuit fabrication. Such low stress dielectrics are discussed
`at length in U.S. Pat. No. 5,354,695 of the present inventor,
`incorporated herein by reference.
`
`Ex. 1001 at 8:47-55; Ex. 1002 at ¶64. The ’778 patent explains alternatively “[t]he
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`use of dielectrics with conventional stress levels could be used in the assembly of”
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`the described 3D ICs, but that “if more than a few layers comprise the stacked
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`assembly, each layer in the assembly will have to be stress balanced so that the net
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`stress of the deposited films of ta layer is less than 5×108 dynes/cm2.” Ex. 1001 at
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`8:55-60; Ex. 1002 at ¶65. The claims recite low tensile stress dielectrics, but not
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`stress balancing. See, e.g., Ex. 1001 at claims 1, 2; Ex. 1002 at ¶¶64-66.
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`Prosecution History of the ’778 Patent
`
`C.
`U.S. App. No. 13/963,149 (“the ’149 application”), which became the ’778
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`patent, was filed on August 9, 2013. It claims priority through a series of
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`continuations to U.S. Application No. 08/835,190, filed on April 4, 1997.
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`After receiving a double patenting rejection in the first office action (Ex.
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`1017 at 71-76), PO filed a terminal disclaimer (id. at 133) and amended the
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`rejected claims and added nearly 100 new claims (id. at 140-60). The Examiner
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`issued another Notice of Allowance on January 30, 2014. Id. at 201-205. PO then
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`began several iterations of amending and adding claims and receiving notices of
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`allowance without substantive comment. Id. at 265-99, 304-39, 356-91, 392, 422-
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`57. PO’s last amendment did not receive consideration (id. at 465), so PO filed an
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`8
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`unexamined certificate of correction altering claim scope (id. at 478-79).
`
`VIII. CLAIM CONSTRUCTION
`An unexpired claim subject to IPR receives the “broadest reasonable
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`construction in light of the specification of the patent in which it appears.” 42
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`C.F.R. § 42.100(b).5 The Federal Circuit has advised that the “PTO should also
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`consult the patent’s prosecution history” when determining the broadest reasonable
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`construction of a claim. See, e.g., Microsoft Corp. v. Proxyconn, Inc., 789 F.3d
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`1292, 98 (Fed. Cir. 2015). Petitioner proposes the “broadest reasonable
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`construction” for the term(s) identified below. Any remaining terms should be
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`given their plain and ordinary meaning.
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`“semiconductor substrate” is “substantially flexible”
`
`A.
`The term “substantially flexible” appears in claims 2, 8, 31, 32, 44, 46, and
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`52-54 to modify “semiconductor substrate.” In light of the intrinsic record, the
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`broadest reasonable construction of “substantially flexible” when used to modify
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`“semiconductor substrate” is “a semiconductor substrate that has been thinned to a
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`
`
` 5
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` The ’778 patent may expire during this proceeding. After expiration, Petitioner
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`believes the challenged claims should be construed according to Phillips v. AWH
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`Corp. 415 3d 1303 (Fed. Cir. 2005). Under Phillips, the challenged claims are
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`unpatentable for the same reasons set forth herein.
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`9
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`thickness of less than 50 μm and subsequently polished or smoothed.”
`
`PO acted as its own lexicographer and defined a “substantially flexible”
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`“semiconductor substrate” consistent with Petitioner’s proposed construction:
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`“Grind the backside . . . of the second circuit substrate to a thickness of less than
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`50 μm and then polish or smooth the surface. The thinned substrate is now a
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`substantially flexible substrate.” Ex. 1001 at 9:5-8, 3:5-9 (emphasis added).
`
`PO confirmed this definition during prosecution of related applications.6 For
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`example, during prosecution of U.S. Patent No. 8,907,499 (“’499 patent”) the
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`Examiner objected to certain claims reciting “substantially flexible” as indefinite
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`for failing to “clearly set for[th] the metes and bounds of the patent protection
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`desired.”7 Ex. 1018 at 4. PO overcame the objection by arguing that “substantially
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`flexible” is unambiguous because it is “clearly explained in the specification”:
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`With respect to the language “substantially flexible,” the meaning of
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`
`
` 6
`
` Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1350 (Fed. Cir. 2004);
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`Teva Pharm. USA, Inc. v. Sandoz, Inc., 789 F.3d 1335, 1343-44 (Fed. Cir. 2015).
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`7 Petitioner reserves the right to challenge the validity of the challenged claims
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`under 35 U.S.C. § 112 as indefinite for “failing to inform, with reasonable
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`certainty, those skilled in the art about the scope of the invention.” Nautilus, Inc. v.
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`Biosig Instr., Inc., 134 S.Ct. 2120, 2124 (2014).
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`10
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`this phrase as used in the claims is clearly explained in the
`specification including, for example, at page 18, lines 1-3. As
`described in this passage, a semiconductor substrate is caused to be
`substantially flexible by thinning it to 50 microns or less and polishing
`or smoothing the thinned semiconductor substrate to relieve stress.
`The phrase “substantially flexible” is used in the claims consistent
`with this description, which is unambiguous.
`
`Ex. 1019 at 9; see also Ex. 1020 at 18:1-3. During prosecution of related U.S.
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`Patent App. Nos. 12/497,652 and 12/497,653, PO similarly attempted to
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`distinguish the art: “[a] substantially flexible semiconductor substrate may be
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`achieved by grinding until considerably thin, for example to a thickness of less
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`than 50 microns, and polishing the resulting surface.” Ex. 1021 at 2; Ex. 1022 at 2.
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`The patent applicant clearly and unmistakably set forth a definition of the
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`term “substantially flexible” when used to modify “semiconductor substrate” and
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`expressed an intent to define the term. See Tempo Lighting, Inc. v. Tivoli, LLC, 742
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`F.3d 973, 977-78 (Fed. Cir. 2014). These statements accordingly limit the scope of
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`the term. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d
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`1303, 1324 (Fed. Cir. 2011). The proper construction of “substantially flexible”
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`modifying “semiconductor substrate,” is “a semiconductor substrate that has been
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`thinned to a thickness of less than 50 μm and subsequently polished or smoothed.”
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`Moreover, “substantially flexible” is a term of degree that must be construed
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`11
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`to have an objective standard of measurement, because the term would otherwise
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`be indefinite, as the Examiner found during prosecution of the ’499 patent. See Ex.
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`1018 at 4; Ex. 1002 at ¶¶71, 76. The Board has consistently found similar claim
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`language to be reciting terms of degree. See, e.g., MedShape Inc. v. Cayenne Med.,
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`Inc., IPR2015-00848, 2015 WL 5453171, *5 (P.T.A.B. September 14, 2015)
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`(“substantially different”). Claims that recite a term of degree are indefinite unless
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`the patent specification “provide[s] ‘some standard for measuring that degree.’”
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`MedShape Inc., 2015 WL 5453171 at *5 (citing Seattle Box Co. v. Indust. Crate &
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`Packing, Inc., 731 F.2d 818 (Fed. Cir. 1984)). Here, the intrinsic record provides a
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`single standard for determining whether a semiconductor substrate is “substantially
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`flexible”—whether its thickness after thinning is less than 50 µm and then polished
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`or smoothed. See Ex. 1001 at 9:5-8; Ex. 1019 at 9. Petitioner’s construction should
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`be adopted because it sets forth the only reasonable standard for measuring a term
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`of degree that would otherwise render the claims indefinite.
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`Petitioner believes PO may propose an unreasonably broad construction,
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`such as (i) “a substrate that has been thinned to a thickness of less than 50 μm,” or
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`(ii) “a substrate that has been thinned to a thickness of 150 μm or less.” Part X
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`below explains why, under either construction, the Challenged Claims are obvious
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`over the prior art discussed herein, which all teaches or suggests thinning
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`semiconductor substrates to a thickness of less than 50 µm.
`
`12
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`

`
`Petition for Inter Partes Review
`Patent No. 8,841,778
`
` “substantially flexible circuit layer”
`
`B.
`The broadest reasonable construction of “substantially flexible” when used
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`to modify “circuit layer” in claims 8, 44, and 46 is “a circuit layer having a
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`semiconductor substrate that has been thinned to a thickness of less than 50 μm and
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`subsequently polished or smoothed, and where the dielectric material used in
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`processing the semiconductor substrate must have a stress of 5×108 dynes/cm2
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`tensile or less.” The specification explains that each “circuit layer is a thinned and
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`substantially flexible circuit with net low stress, less than 50 μm and typically less
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`than 10 μm in thickness” (Ex. 1001 at 4:24-27), and that “[t]he thinned
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`(substantially flexible) substrate circuit layers are preferably made with dielectrics
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`in low stress (less than 5×108 dynes/cm2)” (id. at 8:47-49).
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`PO further defined this term during prosecution of related U.S. Patent App.
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`Nos. 12/497,652 and 12/497,653, stating that a “substantially flexible” circuit layer
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`requires two features: (i) “the semiconductor material must be sufficiently thin,
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`e.g., 50 microns or less,” and (ii) “the dielectric material used in processing the
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`semiconductor material must be sufficiently low stress,” and “[a]s set forth in the
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`present specification, stress of 5x108 dynes/cm2 or less has been demonstrated to
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`satisfy this requirement.” Ex. 1023 at 28; see also Ex. 1021 at 2-3 (“a substantially
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`flexible semiconductor substrate is a necessary but not a sufficient condition for a
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`sub