IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. l6, NO. 7, NOVEMBER 1993
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`Future WSI Technology:
`Ronald Williams
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`Stacked Monolithic WSI
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`and Ogden Marsh
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`HADIATION
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`DETECTOR ARRAY
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`DETECTOR
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`S, HEADOU,
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`INDIUM BUMP
`INTERCONNECT
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`Fig. 1. Hybrid FPA. A hybrid FPA is composed of an IR detector chip
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`connected to a read-out chip via vertical indium bump interconnects at each
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`pixel (diode).
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`II.
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`Abstract— This paper describes a methodology for stacking
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`chips vertically and interconnecting them through the chips
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`to achieve a three-dimensional
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`ogy involves the integration of two technologies: indium bump
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`interconnect
`technology, historically used to fabricate hybrid
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`focal plane arrays, and the precision thinning of bonded silicon
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`wafers by a process called Acuthin. Substantial improvements
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`in computing density, power dissipation, and signal propagation
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`time can be realized. This paper describes some of the techniques
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`and benefits of this 3-D interconnect methodology.
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`1.
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`INTRODUCTION
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`AFER scale technology is advancing via the develop-
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`ment of larger dice, stacking with chip-edge intercon-
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`nections, and redundant, or fuse-link, architecture to improve
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`yield. Routing and interconnection requirements for wafer
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`scale integration are established in the literature [1], [2]. J. F.
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`McDonald described a methodology for substantially lowering
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`.7: — y propagation resistance while retaining the features of
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`negligible ;:—axis propagation inhibitors [3]. Previous work
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`the Hughes Research Laboratories (HRL)
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`provided a method of stacking wafers utilizing microbridge
`wafer interconnects.
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`A methodology to implement three-dimensional (3-D) wafer
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`scale technology is described which combines two existing
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`technologies: 1)
`indium bump interconnect technology (de-
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`veloped at the Hughes Technology Center) used to fabricate
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`hybrid focal plane arrays, and 2) the precision silicon thinning
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`technology called Acuthin (developed at Hughes Danbury Op-
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`tical Systems), which utilizes bonded silicon wafers. Circuits
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`are fabricated on bonded silicon wafers and then thinned using
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`the Acuthin process to allow through-chip interconnects to
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`be made to either side of the IC. Indium bumps allow these
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`thin device layers to be stacked vertically and electrically
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`interconnected to achieve a 3-D circuit. This methodology
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`offers the potential for power savings of orders of magnitude
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`by providing lower capacitance and inductance for drive
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`lines as well as fully depleted transistor junctions. The chip
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`and wafer stacking techniques described in this paper are
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`higher density complementary technologies to the microbridge
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`interconnects developed at the Hughes Research Laboratories.
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`INDIUM BUMP INTl:'RCONNl:‘C1‘ TECHNOLOGY
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`Indium bump interconnect technology was originally devel-
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`oped to provide a means of mating an array of IR detectors
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`to an array of amplifier circuits called a read-out (see Fig.
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`1). As shown in Fig. 1,
`the readout chip is placed below
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`the detector (relative to the incident light), and each detector
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`pixel is connected to its corresponding read-out circuit through
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`an indium bump interconnect. The resulting two-chip vertical
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`stack is referred to as a hybrid focal plane array (FPA). This
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`technology has advanced to the stage where hybrid FPA’s
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`as large as 640 X 488 pixels, requiring nearly a third of a
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`million interconnects, are being successfully fabricated. Yields
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`of perfectly connected assemblies having as many as 97 000
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`interconnects per chip pair exceed 94%.
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`Many different types of detector arrays have been connected
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`to read-outs in this 3-D arrangement, and many such hybrid
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`assemblies have been used successfully in space, missile,
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`astronomy, and airborne applications, having stringent reli-
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`ability requirements. The various detectors used operate at
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`temperatures ranging from 4K to greater than 77K. Since
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`the read-out arrays are usually fabricated in silicon and the
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`detector arrays are usually fabricated in materials other than
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`silicon (e.g., HgCdTe, lnSb), the mismatch in the coefficients
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`of thermal expansion of these dissimilar materials causes
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`mechanical stress on the indium interconnects during thermal
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`cycling. The indium interconnects must, and do, remain intact
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`and fully functional through repeated thermal cycles and the
`associated mechanical stress.
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`indium bumps are produced using wafer processing tech-
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`the wafer level. Indium is a rather unique metal,
`niques at
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`softer
`than most plastics, annealing at room temperature,
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`and able to melt without flowing. Indium bump interconnect
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`technology has exhibited one failure mode: cohesive failure
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`in the bump induced by severe mismatch of the thermal
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`expansion characteristics of the different read-out and detector
`0148-6411/93$03.00 © 1993 IEEE
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`Manuscript received April 21, 1993; revised August 6, 1993. The Work on
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`the Wafer—Scale Associative String Processor (WASP) is supported by the U.
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`5. Office of Naval Research. This paper was presented at
`the International
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`Conference on Wafer Scale Integration, San Francisco, CA, January 20-22,
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`1993.
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`The authors are with the Technology Center, Hughes Aircraft Company,
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`Carlsbad, CA 92009-1699.
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`IEEE Log Number 9212409.
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`SAMSUNG ET AL. EXHIBIT 1056
`Page 1 of 5
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`WILLIAMS AND MARSH: FUTURE WSI TECHNOLOGY: STACKED MONOLITHIC WSI
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`THERMALLY GROWN
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`Si02 1 pm THICK, ALL SURFACES
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`FUSION BOND 6 1150° C
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`LAP AND CHEM MECHANICAL
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`POLISH TOP WAFER
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`TO 2 t 0.3 um
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`FUCK
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`IIi3u"l'£‘£éE‘"“E"’
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`PLASMA
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`ELECTRODE
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`Fig. 2. Bonded silicon wafers.
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`RF SUPPLY
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`COMPUTE
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`%1
`ETCH AT 1-50 umlmin
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`PLASMA DIAMETER:
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`3 mm to >3.0 um
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`materials over many cool-down cycles (greater than 100)
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`from room temperature to 77K or colder. However, since
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`indium reanneals at room temperature, there is little concern
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`about interconnect fatigue or cohesive failure occurring for
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`chips operated in the normal military temperature range (-
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`55—125°C). Also, for chips of similar materials (e.g., silicon
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`and silicon) interconnected with indium bumps,
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`mode is eliminated regardless of thermal cycling because both
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`chips expand and contract at the same rate. In addition, while
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`indium has a tensile strength of only 9% of the more common
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`solder bumps, its creep strength for sustained loading is twice
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`These qualities make indium bump interconnect technology
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`a viable process for use in the construction of 3-D silicon lC’s.
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`Preliminary testing at 150°C for thousands of hours shows that
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`the indium bump interconnects remain reliable. The melting
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`temperature of indium is 157°C, and testing has confirmed
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`that bumps loose all strength above this temperature and chips
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`remain in contact only due to surface tension effects.
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`III. BONDED SILICON WAFER THINNING
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`To effectively stack and interconnect wafers and chips into
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`a 3-D circuit arrangement, two requirements are imposed on
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`the device layers: 1) the 2-D silicon chip or wafer must be
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`thin (<10 pm) to allow electrical contact to both sides of
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`the wafer/chip through trench vias provided in the IC design;
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`and 2) the 2-D silicon chip or wafer must be very flat (<1
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`pm total thickness variation) to permit indium interconnecting
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`over large circuit areas. These requirements are met by bonded
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`silicon wafer thinning.
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`Recent developments in preparing silicon-on-insulator (SOI)
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`material have utilized bonded silicon wafers (see Fig. 2).
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`These wafers have a buried 1-um thick silicon dioxide layer
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`below a thin single-crystal silicon layer. Bonded silicon wafers
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`are commercially available with thin silicon layer thicknesses
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`down to 2 :t0.5 um. Circuits are fabricated in the thin silicon
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`layer, and the bulk supporting wafer is then etched away to
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`begin the 3-D fabrication process. Production processes to thin
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`a processed IC wafer to 10 pm or less from the backside
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`were not available until recently with the development of the
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`Acuthin process, shown in Fig. 3.
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`son in rmcxuess comouns
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`64 x 54 MAP <80 SECONDS
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`THICKNESS
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`Fig. 3. The Acuthin process. Acuthin allows high~precision thinning of
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`The Acuthin process was initially developed for final optical
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`figuring; however,
`its application to silicon is expected to
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`become significant to the electronics industry. Fig. 4 shows
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`the measured thickness profile for the thin silicon layer of
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`a 100-mm bonded silicon wafer processed with the Acuthin
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`process. The Acuthin process removes precise, precalculated
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`amounts of material from the wafer surface by plasma-assisted
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`chemical etching. The surface is first profiled, and a computer
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`program determines the electrode movement profile to remove
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`the desired amount of material. The Acuthin process can
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`produce wafers which have thickness uniformity within a few
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`angstroms. Similarly, surface flatness of bonded silicon or
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`bulk silicon wafers can be controlled with the same degree of
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`SAMSUNG ET AL. EXHIBIT 1056
`Page 2 of 5
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`

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`IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 7, NOVEMBER 1993
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`Refer ~§'”~1‘3 Rt“
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`AVERAGE THICKNESS = 21,152 A
`sro DEV = 3,928 A
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`AVERAGE THICKNESS 3 577 A
`sro DEV .—= 20 A
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`Fig. 4.
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`Acuthin thinning of 100-mm bonded silicon wafers.
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`DRAIN
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`GATE SOURCE BODY
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`SAPPHIRE SUBSTRATE
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`EPOXY BOND
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`OVERGLASS (1.2 pm)
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`ALUMINUM (0.75 pm)
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`BPSG (0.6 pm)
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`S|LlCON Acuthinl“-THINNED (0.3 um)
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`SILICON DIOXIDE (1 pm)
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`v “K "FEEDTHRU"
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`EIACKSIDE ALUMINUM (0.75 pm)
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`SOURCE
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`BODY
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`DRAW
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`Fig. (1. Wafer incorporating Acuthin single—transfer and backside processing.
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`Bonded silicon \vafers can be processed in an identical
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`fashion to standard silicon wafers using the same design rules
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`and fabrication procedures.
`is even possible to mix the
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`bonded silicon wafers with standard bulk silicon wafers in
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`a process lot with no process compensation needed. Bonded
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`silicon wafers are somewhat expensive at this time, about four
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`times the cost of a standard bulk silicon wafer, but market
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`projections indicate that the cost of bonded silicon wafers will
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`approach that of standard bulk silicon wafers as the bonded
`silicon market matures.
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`Recent developments in via technology allow thinned wafers
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`to be electrically accessed from either side (top and bottom) for
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`electrical interconnects. This via technology requires thinned
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`silicon, usually less than 10 pm thick, so that the via holes
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`can be fabricated and insulated during normal semiconductor
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`processing using existing silicon dioxide and metal steps. The
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`thinned wafers are electrically connected with indium bumps
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`on either side of the thinned silicon circuitry. These operations
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`are performed at
`the wafer level. Hughes has developed
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`(H)
`T5233B DIE 16 DEVICE E1
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`1.000/aav
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`(b)
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`Fig. 5. Demonstration of NMOS transistor I—V characteristics after front-
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`and backside Acuthin wafer fabrication devices are on 0.3~[lI'Il
`transferred
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`silicon with backside body contact.
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`precision. As shown in Figs. 5 and 6, transistor circuits have
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`been fabricated on Acuthin material. These transistors are 0.3
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`thick and illustrate the essential Vertical-through-silicon
`/III]
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`contacts necessary for 3-D wafer scale integration.
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`SAMSUNG ET AL. EXHIBIT 1056
`Page 3 of 5
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`

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`WILLIAMS AND MARSH. FUTURE WSI Tl-1(‘llNOL0(}Y STACKED M()NOl.l'lHIC
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`WSI
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`5'3
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`UPPER WASP WAFER
`i
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`‘ g l
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`LOWER WAS? WAFER
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`|ll
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`Fig. 7. High density interconnect for WASP 3 D.
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`prototype hardware to demonstrate all key elements in this
`approach to wafer scale integration and stacking.
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`IV. STACKING WAFERS
`
`The first application of this 3-D technology is to be the wafer
`scale associative string processor (WASP), an exploratory
`computer application [6]. [7]. The associative string processor
`architecture has the important advantage of being fault-tolerant
`and able to diagnose and electrically switch around defective
`cells. Fault—handling capability is necessary in wafer scale
`projects to compensate for contemporary wafer and die yields.
`Fig. 7 shows the make-up of the high density interconnect
`layer. This wafer scale integration requires only a few thousand
`bump interconnections. Another simplification incorporated
`into this application is the use of silicon for both wafers:
`because of chip heating during operation,
`it would be very
`difficult to stabilize dissimilar materials over a 2.1 in by 2.1
`in area.
`
`The design of a 3-D logic device is an inventive process,
`because vertical partitioning is not a common element
`in
`microcircuit design. The initial selection of the associative
`string processor simplifies this somewhat. since the processor
`is composed of many identical cells. Gross modeling of the
`processor. as shown in Fig. 8,
`illustrates the necessity of
`through-chip interconnects rather than the conventional edge
`interconnect structure. The more common method of stacking
`and connecting large dice is to metallize or TAB bond edge
`pads. This method does not allow large interconnect structures,
`which have very low capacitance and inductance,
`to supply
`power and signals to the center of the wafer. Low resistance
`through-chip vias substantially improve this situation. The
`completed 2.1-in square chip stack must operate at 20 Mllz.
`As a step in the direction of a full-up WASP, we have
`fabricated a multichip module (MCM). This parallel string
`processor module. shown in Fig. 9, has only the routing,
`indium bump interconnect circuitry, and polysilicon resistors
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`Fig. 8. Comparison of gross electrical parameters for three wafer stacking
`methods,
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`7 3 9 10
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`52,
`1
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`recuwomcav (3t£NTt‘t
`2 3 C 5 6
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`Fig. 9.
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`Parallel string processor module.
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`of the full wafer scale integration device and replaces the upper
`and lower wafer with discrete dice. When the entire process is
`assembled later in this decade, the stack will be as illustrated
`as shown in Fig. 10. The WASP architecture is an ideal first
`attempt into this new technology application.
`
`V. CONCLUSION
`
`To summarize, the elements of a successful 3-D wafer scale
`integration product will he:
`0
`fault-tolerant circuitry;
`0
`total control of the silicon thickness and flatness;
`0 reliable multithousand bump interconnections.
`The benefits of a successful 3-D wafer scale integration
`product will be:
`- higher speed:
`- lower power;
`-
`lower production cost.
`The principal market
`inhibitor will be the availability of
`proper design tools to establish a product which efficiently uses
`the shorter chip-to-chip interconnects to improve performance
`and lower costs.
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`SAMSUNG ET AL. EXHIBIT 1056
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`Page 4 of 5
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`

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`IEEE TRANSACTIONS ON COMPONENTS. IIYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, N0. 7, NOVEMBER 1993
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`SILICON DIOXIDE
`0.1-0.4rm OF SILICON
`POLYSILICON GATE
`SILICON DIOXIDE
`ALUMINUM
`
`In INTERCONNECT
`BOND MATERIAL
`SILICON DIOXIDE
`0.1-0.4mm OF SILICON
`POLVSILICON GATE
`SILICON DIOXIDE
`
`In INTERCONNECT
`BOND MATERIAL
`SILICON DIOXIDE
`0.2-0.4:-n OF SILICON
`POLVSILICON GATE
`SILICON DIOXIDE
`
`BOND MATERIAL
`In INTERCONNECT
`
`POLYSILICON GATE
`SILICON DIOXIDE
`0.1-0.4m OF SILICON
`SILICON DIOXIDE
`
`mp.
`SILICON SUBSTRATE
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`Fig. 10.
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`3-D S01 wafer scale lC’s.
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`REFERENCES
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`K. C. Kcezcr and V. K. Jain, “Design and evaluation of wafer scale clock
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`
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`distribution," in Proc. Int. Can)‘. an Wafer-Scale Integration, 1992, pp.
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`16&175.
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`D. C. Keezer and V. K. Jain, “Clock distribution strategies for WSI:
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`A critical survey,” in Prac. Int. Conf on Wafer-Scale Integration, 1991,
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`pp. 277—283.
`
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`J. F. McDonald, “An overview and analysis of 3D WSI,” in Proc. Int.
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`Conf. on Wafer-Scale Integration, 1991, pp. 223-235.
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`M. W. Yung and M. J. Little, “A new approach to implement a defect
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`tolerant power distribution network in WSI circuits," in Proc. Int. Conf
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`on Wafer—Scale Integration, 1991, pp. 215—222.
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`M. J. Little and J. Grinberg, “The 3—D computer: An integrated stack of
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`WSI wafers,” in Wafer Scale Integration. E. Swartzlander, ed. Boston,
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`
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`MA: Kluwer Academic, 1989.
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`I. P. Jalowiecki, S. 1. Hedge, and R. Williams, “The development of the
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`WASP 3 processor,” in Prue. Fifth Arm. IEEE Int. Canfl on Wafer Scale
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`Integration, 1993, pp. 20—~29.
`
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`R. M. Lca, “Comparing monolithic and hybrid WSI massively par-
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`allel processing modules for cost—el‘fective real—time signal and data
`
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`
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`processing,” in Proc. Int. Conf on Wafer Scale Integration, 1991, pp.
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`199A206.
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`Ronald Williams received the BS. degree in
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`physics from the University of California at Los
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`Angeles. He took part
`in graduate studies
`in
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`metallurgical, electrical, and materials engineering.
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`several years experience in applied
`He has
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`vacuum technology and crystal polishing and
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`lapping. Currently, he is a Laboratory Scientist
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`with the Engineering Laboratory, Hughes Aircraft
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`Company Technology Center, where he has made
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`major contributions to the Center's highly successful
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`indium bump hybridization techniques. He has 22
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`years experience in vacuum deposition, component and process design, and
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`the design and fabrication of specialized machinery,
`including six years
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`experience as Manager of HTC’s Assembly Laboratory. He currently provides
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`technical leadership and management of groups responsible for production of
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`precision quartz resonators, flexible printed wiring, and miniaturized electronic
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`assemblies. He currently holds 5 patents.
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`Ogden Marsh received the B.S.E.E. degree from
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`the University of Connecticut and the M.S.E.E.
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`degree from the University of California at Los
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`Angeles.
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`is currently a Chief Scientist with the
`He
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`Hughes Aircraft Company Technology Center. He
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`is presently investigating the applications of new
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`materials and processes to device structures for
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`flat«panel
`and projection displays,
`focal plane
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`arrays, signal processing circuitry, high temperature
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`electronic circuitry, and radiation hard nonvolatile
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`involved in developing bonded silicon wafer
`(BSW)
`memories. He is
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`technology for application to silicon-on-insulator
`(SDI) high speed and
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`radiation hardened integrated circuits. Ile is also involved in the development
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`of a new high frequency liquid crystal light valve (LCLV) and is heading a
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`team developing this light valve for high density television projection systems.
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`He is also involved in developing the silicon molecular beam epitaxy (MBE)
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`process at the Hughes Research Laboratories and its applications to new device
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`structures, such as Si/SiGe heterojunction bipolar transistors. In addition, he
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`has managed infrared detector programs as well as several projects involving
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`crystal growth and evaluation of semi-insulating GaAs and Si crystals for
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`LWIR detectors and S01 materials for VHSIC. He has been involved in
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`experimental research on space charge-limited current in semi—insulators and
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`its applications. He was one of the first
`investigators of ion implantation
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`in semiconductors and semi-insulators. He is currently a Visiting Associate
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`with the Division of Engineering and Applied Science, California Institute of
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`Technology. He currently holds 15 patents.
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`Mr. Marsh is a member of APS, AVS, the Electrochemcial Society, and
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`MRS.
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`SAMSUNG ET AL. EXHIBIT 1056
`Page 5 of 5