April 28. 1970
`.M.JACKSON.JR_ EIAL
`3,508,980
`§n1ETfi1'JI) OF‘ FA . CATING AN IN
`RA‘l‘E.‘D CIRCUIT STRUCTURE
`WITH DIEL
`TR
`ISOLAT.
`ION
`Filed
`‘ 3 26. 1967
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`LNVENTORS
`Bernard W! Bolano‘
`. Don M. Jackson Jr
`
`SAMSUNG ET AL. EXHIBIT "I041
`
`Page 1 of 4
`
`

`
`United States Patent Ofice
`3,508,980
`Patented Apr. 28, 1970
`
`1
`
`2
`
`3,508,930
`METHOD OF FABRICATING AN INTEGRATED
`CIRCUIT STRUCTURE WITH DIELECTRIC
`ISOLATION
`Don M. Jackson, Jr., and Bernard W. Boland, Scottsdale,
`Ariz., assignors to Motorola, Inc., Franklin Park, III.,
`a corporation of Illinois
`Filed July 26, I967, Ser. No. 656,215
`Int. Cl. HOII 7/36, 7/50
`U.S. Cl. l48—1’r'S
`
`1 Claim
`
`
`
`ABSTRACT OF THE DISCLOSURE
`An integrated circuit structure with dielectric isola-
`tion is madc by a process which involves the bonding of
`a “handle wafer" to a protected epitaxial film grown on
`a low resistivity substrate of the same conductivity type.
`The back side of the srrl-rstrate is then thinned to about
`one mil, preferably by chemical etching. Isolated scint-
`conductor islands or mesas are fornred by selectively etch-
`ing through the remaining substrate and epitaxial layer,
`followed by impurity diffusion or mctallization to form
`highly conductive channels for surface collector contacts.
`The islands are then isolated by the formation of an oxide
`film and a “back—filt" of polycrystalline silicon, high tem-
`perature glass, or other ceramic material. The handle
`wafer is removed whereby the epitaxial portions of the
`semiconductor islands are exposed and prepared for de-
`vice fabrication by light mechanical polishing to remove
`any surface damage.
`
`BACKG ROUND
`
`This invention relates to the fabrication of semicon-
`ductor structures and particularly to integrated circuits
`comprising an array of semiconductor islands separated
`by dielectric isolation.
`Monolithic integrated circuits generally consist of a
`number of active devices such as transistors and diodes
`formed in a single semiconductor crystal element.
`in
`combination with passive devices such as resistors anti
`capacitors also formed in or on the same semiconductor
`element. These devices are interconnected into a circuit
`by a metallization pattern formed on an insulating film
`covering the surface of the semiconductor element. In
`order to avoid or minimize the undesirable interaction of
`the devices with one another it is necessary to provide
`isolation between the active regions or islands of the
`structure.
`
`The most common means of electrically separating one
`region front another is known as p—n junction isolation,
`achieved by providing two oppositely oriented isolation
`junctions between each pair of active regions. When one
`junction is biased in the forward direction the other will
`be biased in the reverse direction. Thus, one of the junc-
`tions will be reverse biased under any given operating
`condition. Since El. reverse biased junction has a very high
`DC. resistance,
`interaction between adjacent devices is
`minimized except at very high frequencies.
`More recent] y various methods have been proposed for
`the fabrication of integrated circuits wherein the semi-
`conductor islands are isolated from each other by a grid-
`like pattern of dielectric insulation. Due to the physical
`proximity of elements in one conglomerate block,
`the
`ability to interconnect all of the devices with thin lilnr
`wiring is preserved. Also preserved are the inherent ad-
`vantages of batch fabrication techniques
`to produce
`identical circuits in large quantities,
`thereby providing
`the lowest per unit cost. and potentially thc highest order
`of rcliabih'ty. Dielectric isolation provides the additional
`
`advantage of reduced parasitic capacitance and higher
`frequency operation.
`Various dilfictlllios have been encountered, however, in
`the development of processes for integrated circuit fabri-
`cation with dielectric isolation. In addition to the sub-
`stantially increased costs resulting from an increased
`number of processing steps, principal difficulties have in-
`volved the need for critically precise lapping and polish-
`ing as a means of achieving uniform thickness across the
`entire surface of a wafer, and the dilficulty of achieving
`optimum transistor collector profiles.
`THE INVENTION
`
`is a primary object of the present in-
`it
`Accordingly,
`vention to eliminate the need for precise mechanical shap-
`ing in the manufacture of integrated circuits having di-
`electric isolation. It is a further object of the invention
`to provide a method of optimizing collector i rnpurity pro-
`files in the manufacture of integrated circuits with di-
`electric isolation.
`
`It is a feature of the invention that the critically uni-
`form thickness required from island to island is provided
`by epitaxial growth. which is inherently more amentlable
`to precise control than is possible with mcthanical shap-
`ing techniques.
`An additional feature of the invention is the deposi-
`tion of a silicon carbide layer to protect the epitaxial
`film. The silicon carbide also serves to interrupt a sub-
`sequent etching step at the proper depth. The SIC can be
`easily removed later by heating the wafer in an oxidizing
`ambient. The SiC will be converted to Si02.
`An additional feature of the invention is the bonding of
`a dummy substrate or “handle wafer” to the epitaxial
`layer which ultimately forms the critical region of the
`semiconductor islands. This can be a. ceramic, single or
`polycrystalline silicon or a metal vrafc1‘—0r even a suit-
`able plastic.
`An additional feature involves the provision of low
`series resistance collector contacts at the same surface
`with the emitter and base contacts, by forming highly
`conductive regions completely surrounding each semi-
`conductor island and extending to the surface where con-
`tact means are provided. The highly conductive channel
`may be formed by diffusion of a suitable impurity, or by
`a metallization technique, preferably chromium deposi-
`tion. The etched rcgions surrounding the semiconductor
`islands are then baclofilled to provide dielectric isola-
`tion with a suitable glass, a ceramic and glass cement, or
`other ceramic insulation material. Polycrystalline silicon
`may also be deposited, in accordance with known tech-
`niques.
`A method is provided which includes in combination
`the steps of selectively etching the back side of an epi-
`taxial wafer to form discrete semiconductor islands or
`mesas, followed by impurity diffusion or metallization to
`form highly conductive channels for surface ohmic con-
`tacts with transistor collector regions. A pyrolytic oxide is
`deposited over the mesal surface, followed by isolation
`of the semiconductor islands by back-filling with poly-
`crystalline silicon, high temperature glass, or other ce-
`ramic material.
`The invention is embodied in a process for the fabrica-
`tion of a semiconductor structure to be used in the manu-
`facture of
`integrated circuits, comprising the steps of
`growing an epitaxial semiconductor film at least % mi»
`chon thick on a low resistivity monocrystalline semicon-
`ductor substrate, forming a protective layer on said
`epitaxial film, bordiug a dummy substrate to the pro-
`tected epitaxial surface,
`thinning the original substrate
`by removing a substantial portion thereof from its back-
`side, selectively etching a grid-like pattern in said sub-
`strate to form an array of semiconductor islands, fortn-
`
`5
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`
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`20
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`SAMSUNG ET AL. EXHIBIT "I041
`
`Page 2 of 4
`
`

`
`3,508,980
`
`3
`ing highly conductive channels along the sides of said
`islands to provide for top collector contact means, coat-
`ing the conductive channel with Si0-_», back—filling the
`etched pattern with a dielectric material, then removing
`said dummy substrate to expose the epitaxial regions of
`said serniconductor islands for the fabrication therein of
`semiconductor devices.
`in accordance with an alternate
`It
`is also feasible,
`embodiment of the invention, to complete the diffusion of
`impurities to form diodes,
`transistor base regions and
`emitter regions, and to form diffused resistors, etc., in the
`epitaxial film before the step of forming a protective layer
`thcrcon. Otherwise, the above sequence of steps remains
`unchanged.
`In all subsequent processing steps ol
`this
`embodiment, however,
`it
`is essential
`to avoid tempera-
`tures in excess of about 825° C., in order not to redis-
`tribute impurity profiles.
`In accordance with ti. preferred embodiment the proc-
`ess includes,
`in addition to the above steps, the pyrolytic
`deposition of silicon carbide on the epitaxial layer prior
`to the bonding thereto of a dummy substrate. For ex-
`ample, the silicon carbide layer may be Formed by ex-
`posing the substrate to the mixed vapors of silane and
`propane diluted with a carrier gas, or by other known
`techniques. The carbide layer serves to protect.
`the epi-
`taxial film surface and to interrupt the subsequent etching
`process at the proper depth. As little as 300 angstroms
`of silicon carbide is generally suflicient; however, best
`results are obtained by depositing a silicon carbide layer
`at least 500 ang.-stroms thick.
`In accordance with a further embodiment, the back-
`fill step is interrupted soon after the semiconductor is-
`lands are covered, and the back-fill material is mechani-
`cally lapped and polished to provide a planar surface, to
`which a second dummy substrate is bonded. The first
`dummy substrate is then removed, along with the silicon
`carbide layer, if present, to expose the epitaxial regions
`wherein the active circuit. devices are to be or have been
`fabricated. The Rcond dummy wafer thus becomes a
`permanent part of the structure, providing only the me-
`chanical strength necessary to prevent breakage.
`DRAWINGS
`
`JD
`
`30
`
`'10
`
`FIGS. 1-8 are enlarged cross—sectional views illustrat-
`ing a sequence of steps used in the fabrication of a semi-
`conductor strucrure in accordance with the method of
`the invention.
`In FIG. 1 a passivated epitaxial semiconductor is rep-
`resented. In a particular embodiment, substrate 11 is a
`low resistivity monocrystalline silicon wafer of N—type
`conductivity as produced by heavy doping with a donor
`impurity such as arsenic, for example. A substrate thick-
`ness of about 10 mils is generally suitable, although a
`thickness in the range of T to 20 mils or more may be
`used. A substrate resistivity from .001 to .03 ohrn-ocn-
`timeters is suitable with .005 to .01 being preferrcrl.
`Inadvertent nonuniformilies in the thickness or taper
`of the substrate do not critically aifect the device yield,
`as is true of some prior methods for the fabrication of
`integrated circuits with dielectric isolation. Uniform
`thickness is essential
`in epitaxial
`layer 12; however,
`thickness control during epitaxial growth is far more
`readily achieved than in the preparation of a substrate.
`Protective layer 13 may consist of a thermal oxide, or
`an oxide formed by vapor deposition. Preferably,
`the
`epitaxial layer is protected by the pyrolytic deposition of
`silicon carbide.
`FIG. 2 illustrates the attachment of a dummy substrate
`15 to epitaxial film 12 by means of bonding layer 14
`which is preferably a glass or ceramic which softens at
`an appropriate temperature depending on when the dif-
`fusions arc to be made. The dummy substrate may be
`Scrap silicon or any conveniently available substance
`having at least approximately the same coefficienl of ther-
`mal expansion as the semiconductor wafer. The sole flinc-
`
`en Us
`
`60
`
`65
`
`"F5
`
`4
`tion of substrate 15 is to serve as a “handle" for tern-
`nporarily holding the semiconductor islands in place dur-
`ing intcrmccliatc processing steps. Substrate 15 is ulti-
`mately removed and discarded. or reused in subsequent
`processing runs. Bonding layer 14 is a suitable glass,
`ceramic, or plastic. If diffusion is to follow island forma-
`tion, the glass or ceramic. should soften pnelerahly above
`1200“ C.
`in order that softening will not occur during
`the subsequent diffusion steps. Germanium temperatures
`are correspondingly lower.
`FIG. 3 represents the same structure as shown in FIG.
`2 but in an inverted position. The shaded area of substrate
`11 is then removed by any known procedure, preferably
`by chemical etching. The unshaded area of layer 11 which
`remains has a thickness of preferably about 15 microns.
`A thickness within the range of about 5 microns to 25
`microns is suitable.
`In FIG. 4 oxide layer 16 is formed on the etched sur-
`face of substrate 11. Again, this oxide layer may be formed
`by thermal oxidation or by vapor deposition, By selec-
`tive etching, a grid—like pattern is cut in layer 16 leaving
`oxide patterns in the positions where semiconductor is-
`lands are to remain. The semiconductor islands are then
`formed by etching a moat pattern corresponding to the
`pattern cut
`from oxide layer 16. The moat etching is
`carried out in accordance with known procedures includ-
`ing, for example, contact with I-IF-IINO3 mixtures in the
`case of silicon. The etching step is interrupted by pro-
`tective layer 13. If layer 13 is silicon carbide, as in the
`preferred ernbodirnent,
`the moat etchant will be more
`effectively stopped. Crystallographic orientation of the
`semiconductor and type of etchant will determine the
`side-wall io;‘.og1'aphy of the islands.
`In FIG. 6 chromium or other suitable metal layer 17
`formed by any known technique, such as vacuum
`is
`evaporation deposition. The chromium layer serves as a
`highly conductive region for the purpose of providing a
`low ohmic contact at the final island surface for the col-
`lector regions of transistors subsequently to be fabricated
`in the epitaxial
`layers of the semiconductor islands. or
`which have previously been formed.
`As an alternative to chromium deposition or other
`metallizalion, the semiconductor islands may be subjected
`to high concentration diffusion with a suitable impurity,
`preferably the same impurity as was employed in doping
`substrate 11. Thus the periphery of the epitaxial portion
`of each semiconductor island is convened to a highly
`conductive region for establishing surface collector con-
`tacts. Oxide laycr 18 is then formed to isolate the semi-
`conductor islands. Oxide layer 18 may be former ther-
`mally in the event conductive channels 1'! are formed by
`impurity diffusion. The oxide layer may also be formed
`by vapor deposition, the latter being required in the event
`conductive channels 17 are formed by metallization.
`As shown in FIG. 7, the remaining grid—like pattern
`surrounding the semiconductor islands is back-filled to
`form glass, plastic, or other ceramic pattern 19. Region
`19 may be fabricated to a suflicient thickness to provide
`all the necessary strength required of a permanent base
`structure. In the embodiment shown, however, growth of
`glass pattern 19 is interrupted as soon as the moat pattern
`is substantially filled. A substantially planar surface is
`then formed and :1 second dummy water of a suitable
`material is bonded to substrate 20 to form a permanent
`base for the integrated circuit structure.
`The structure is then rcinverted and is shown in FIG.
`8 after removal of dummy substrate 15 along with bond-
`ing loycr 14 and passivalion layer 13, whereby the epi-
`taxial porlions ‘[2 of the semiconductor island are exposed
`for
`the purpose of fabricating semiconductor devices
`therein, or to complete the circuit through metal inter-
`connections.
`Although it particular embodiment has been described
`in which silicon is the semiconductor material, germanium
`devices may also be constructed in accordance with the
`
`SAMSUNG ET AL. EXHIBIT "I041
`
`Page 3 of4
`
`

`
`3,508,980
`
`5
`invention, as well as IE4.’ compound semiconductor de-
`vices. It will also be apparent that a semiconductor of
`P-type conductivity may be substituted for substrate 11,
`and that p+p structures may be fabricated in accordance
`with the invention. A combination of both 31+ and 11+
`structures is also possible.
`We claim:
`1. A method for the fabrication of a semiconductor
`structure comprising the steps of:
`(:1) growing an epitaxial semiconductor film on a mono-
`crystalline semiconductor substrate,
`(b) forming a layer of silicon carbide having a thick-
`ness of about 500 angstroms on said epitaxial film,
`(c) bonding a dummy substrate to the silicon carbide
`layer,
`(cl) thinning the original substrate by removing a sub»
`stantial portion thereof from its backside,
`(e) selectively etching a grid-like pattern in said sub
`strate to form an array of semiconductor islands,
`(f) forming channels having a high conductivity rela-
`tive to said substrate and epitaxial film along the
`sides of said islands to provide for top surface col-
`lector contact means,
`(g) backfitling the etched pattern with a dielectric ma-
`terial, and then
`
`6
`(in) removing said dummy substrate and silicon carbide
`layer to expose the epitaxial regions of said semi-
`conductor islands.
`
`References Cited
`
`UNITED STATES PATENTS
`
`10
`
`I5
`
`12/ 1966 Chang.
`3,290,745
`4/1967 Osafune et al.
`3,316,128
`3/1967 Last.
`3,313,013
`5/1967 Buie.
`3,320,485
`7/ I967 Kenney ____________., 29—-S77
`3,33 2,137
`9/ 1967 Donovan __________ __ 29-572
`3,343,255
`3,381,182 M1968 Thornton _____ _- 31'.-'—101 XR
`3,386,864
`6/1963 Silvestri et al. .... __ 148-—l75
`3,391,023
`7/I968 Frescura __________ __ 1 11-212
`3,397,448
`8/ 1968 Tucker ____________ _ - 29—S?7
`3,401,450
`9/ 1968 Godejahn _________ __ 29-580
`
`20 L. DEWAYNF. RUTLEDGE, Primary Examiner
`R. A. LESIER, Assistant Examiner
`
`US. Cl. KR.
`
`25
`
`29—572, 578; 1l7‘—201; 143—174; 3l7——235
`
`SAMSUNG ET AL. EXHIBIT "I041
`
`Page 4 of 4