UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Oifice
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
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`APPLICATION NO.
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`FILING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`CONFIRMATION NO.
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`12/497,653
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`30232
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`07/04/2009
`
`Glenn .1. Leedy
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`0907043I)SCMP.U S
`
`6945
`
`7590
`
`08/27/2014
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`USEFUL ARTS IP
`MICHAEL J. URE
`10518 PHIL PLACE
`
`CUFERTINO, CA 95014
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`EXAMINER
`Joy, mmvm
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`PAPER “WEEK
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`MAIL DATE
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`08/27/2014
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`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`PTOL—90A (Rev. 04/07)
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`SAMSUNG ET AL. EXHIBIT 1035
`Page 1 of 6
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`

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`Application/Control Number: 12/497,653
`Art Unit: 2896
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`Response to Arguments
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`Applicant's arguments filed 07/22/2014 have been fully considered but they are
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`not persuasive.
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`(i) In regards to the applicant’s arguments that the rejection is unjustifiably
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`speculative, the examiner respectfully disagrees. In particular, just because the
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`applicant alleges that the flexibility of Leedy's circuit layers are related to conformance,
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`does not mean that modifying Bertin with the low stress dielectric of Leedy would not be
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`desired or lead to an improved device. The applicant defines that the flexibility of their
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`device is based on a thin wafer and the inclusion of a low stress dielectric layer.
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`Therefore including a low stress dielectric layer within the device as taught by Bertin
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`would lead to a flexible device. Furthermore, Leedy specifically states that the inclusion
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`of low stress dielectrics in devices provide advantages to lower the cost and complexity
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`of circuit fabrication and will enhance the performance of the circuit operation. Lastly,
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`rather than using the oxidation process of forming the insulation layers which could
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`perhaps damage the device through the thermal processes, forming the dielectric as
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`taught by Leedyis shown to be an alternative method that would not require the thermal
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`process and would lead to a device that will have enhanced performance characteristics
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`as taught.
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`(ii) In response to applicant's argument that the examiner's conclusion of
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`obviousness is based upon improper hindsight reasoning, it must be recognized that
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`any judgment on obviousness is in a sense necessarily a reconstruction based upon
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`Page 2 of 6
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`

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`Application/Control Number: 12/497,653
`Art Unit: 2896
`
`Page 3
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`hindsight reasoning. But so long as it takes into account only knowledge which was
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`within the level of ordinary skill at the time the claimed invention was made, and does
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`not include knowledge gleaned only from the applicant's disclosure, such a
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`reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA
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`1971). In particular, as shown the rejection does most definitely identify motivation to
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`combine the references within the references themselves (see above). Furthermore, it is
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`common knowledge that insulation layers and more specifically silicon oxide layers
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`maybe be formed from other methods than oxidation. Leedy teaches and shows a valid
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`alternative as well as clearly lays out benefits for using said low stress silicon oxide
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`layer in a similar device.
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`(iii) In regards to the applicant’s arguments that Bertin does not teach forming
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`dielectric layer through oxidation the examiner respectfully disagrees. In particular,
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`Bertin clearly teaches that the dielectric layers are formed by oxidation (Col. 4, lines 30-
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`40) and the applicant even admitted as such in the arguments filed on 04/05/2013 in
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`related application 12/497,652 (Page 28). In said arguments, the applicant admitted that
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`the oxide is formed of thermally grown oxide which is known to be high stress and 5 to
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`10 times the level of stress than the oxides taught in the applicant’s specification.
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`Therefore, the examiner's rational that said low stress dielectrics as taught by Leedy
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`would lead to a dielectric with much lower stress than the dielectric as taught by Bertin
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`is accurate. And the examiner maintains that one would want a device with dielectrics of
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`much lower stress for, at the very least, the reasons mentioned above.
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`SAMSUNG ET AL. EXHIBIT 1035
`Page 3 of 6
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`

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`Application/Control Number: 12/497,653
`Art Unit: 2896
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`(iv) In regards to the applicant’s question on why a lower stress dielectric would
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`be desirable in Bertin, the examiner responds by asking: why would one of ordinary skill
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`and creativity in the art not look to known and available art to improve the device of
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`Bertin? Since Leedy provided the motivation to include low stress dielectric as
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`mentioned above why would one not look to said teachings of Leedy and modify the
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`device of Bertin to improve it?
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`(v) In regards to the applicant’s arguments that the CTE matching of Leedy is not
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`required in Bertin, the examiner acknowledges that while this may be true it does not
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`mean that it wouldn’t be desirable. Leedy teaches that the CTE matching would help to
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`minimize the extrinsic overall stress of the circuit layers. Since, Bertin teaches forming
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`circuit layers why would one having ordinary skill in the art not modify Bertin with the
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`teachings of Leedy to help minimize stress regardless of whether Bertin teaches free-
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`standing circuit membranes.
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`(vi) In regards to the applicant's arguments that using the technique of Leedy
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`rather than Bertin would not lower the cost or enhance the performance, the examiner
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`respectfully disagrees. Leedy specifically states that using layers that are formed by the
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`methods as taught in interconnect structures provide those advantages and that
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`dielectric layers formed by oxidation lead to strongly compressive films while dielectrics
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`formed by the method of Leedy have tensile stress that is low and lead to more flexible
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`Application/Control Number: 12/497,653
`Art Unit: 2896
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`layers that won't fracture. This is clearly more desirable and would enhance
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`performance and would lead to lower cost and flexibility. These benefits would be
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`desirable to one of ordinary skill in the art and not just Leedy.
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`(vii) In regards to the applicant’s arguments that it would not have been obvious
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`to combine the teachings of Berfin and Kato as suggested, the examiner respectfully
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`disagrees. In particular, as stated Bertin already teaches etching said circuit layers to
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`expose the signal paths but fails to carry out an extra step of polishing surface after
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`etching. Kato is relied upon to teach the method of polishing and not relied upon to
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`teach polishing in a certain area such as a backside or frontside since Bertin already
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`teaches thinning the substrate in the desired area as claimed, but merely is relied upon
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`to teach that polishing is known and that it would be desirable to carry out as it would
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`provide a smooth flat surface for bonding. Such a surface is desirable for bonding or
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`forming additional elements in the art since a surface after rough etching can leave it
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`uneven and not preferable for subsequent process steps. This is yet another
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`modification that one of ordinary skill in the art would look to make as it can improve the
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`quality of subsequent process steps such as deposition and bonding.
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`Advisorwcfion
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`Application No.
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`Applicant(s)
`
`Before the Filing Of an Appeal Brief
`
`Examiner
`
`Art Unit
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`AIA (First Inventor to File) Status
`
`--The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`THE REPLY FILED 22 July 2014 FAILS TO PLACE THIS APPLICATION IN CONDITION FOR ALLOWANCE.
`NO NOTICE OF APPEAL FILED
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`1. E The reply was filed after a final rejection. No Notice of Appeal has been filed. To avoid abandonment of this application, applicant must timely file
`one of the following replies: (1) an amendment, affidavit, or other evidence, which places the application in condition for allowance;
`(2) a Notice of Appeal (with appeal fee) in compliance with 37 CFR 41.31; or (3) a Request for Continued Examination (RCE) in compliance with
`37 CFR 1.114 if this is a utility or plant application. Note that RCEs are not permitted in design applications. The reply must be filed within one of
`the following time periods:
`a) E The period for reply expires gmonths from the mailing date of the final rejection.
`b) [I The period for reply expires on: (1) the mailing date of this Advisory Action; or (2) the date set forth in the final rejection, whichever is later.
`In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of the final rejection.
`C) [I A prior Advisory Action was mailed more than 3 months after the mailing date of the final rejection in response to a first after-final reply filed
`within 2 months of the mailing date of the final rejection. The current period for reply expires
`months from the mailing date of
`the prior Advisory Action or SIX MONTHS from the mailing date of the final rejection, whichever is earlier.
`Examiner Note: If box 1
`is checked, check either box (
`), (b) or (c). ONLY CHECK BOX (b) WHEN THIS ADVISORY ACTION IS THE
`FIRST RESPONSE TO APPL|CANT‘S FIRST AFTER-FINAL REPLY WHICH WAS FILED WITHIN TWO MONTHS OF THE FINAL
`REJECTION. ONLY CHECK BOX (c) IN THE LIMITED SITUATION SET FORTH UNDER BOX (c). See MPEP 706.07(f).
`Extensions of time may be obtained under 37 CFR 1.136(a). The date on which the petition under 37 CFR 1.136(a) and the appropriate
`extension fee have been filed is the date for purposes of determining the period of extension and the corresponding amount of the fee. The
`appropriate extension fee under 37 CFR 1.17(a) is calculated from: (1) the expiration date of the shortened statutory period for reply originally
`set in the final Office action; or (2) as set forth in (b) or (c) above. if checked. Any reply received by the Office later than three months after the
`mailing date of the final rejection, even if timely filed, may reduce any earned patent term adjustment. See 37 CFR 1.704(b).
`NOTICE OF APPEAL
`
`. A brief in compliance with 37 CFR 41.37 must be filed within two months of the date of filing the
`2. D The Notice of Appeal was filed on
`Notice of Appeal (37 CFR 41 .37(a)), or any extension thereof (37 CFR 41 .37(e)), to avoid dismissal of the appeal. Since a Notice of
`Appeal has been filed, any reply must be filed within the time period set forth in 37 CFR 41 .37(a).
`AMENDMENTS
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`3. D The proposed amendments filed after a final rejection, but prior to the date of filing a brief, will n_ot be entered because
`a) I] They raise new issues that would require further consideration and/or search (see NOTE below);
`b) I] They raise the issue of new matter (see NOTE below);
`c) I] They are not deemed to place the application in better form for appeal by materially reducing or simplifying the issues for
`appeal; and/or
`d) [I They present additional claims without canceling a corresponding number of finally rejected claims.
`NOTE:
`. (See 37 CFR 1.116 and 41 .33(
`)).
`4. D The amendments are not in compliance with 37 CFR 1.121. See attached Notice of Non—Comp|iant Amendment (PTOL—324).
`5. D App|icant’s reply has overcome the following rejection(s): j
`6. D Newly proposed or amended c|aim(s) j would be allowable if submitted in a separate, timely filed amendment canceling the non-
`allowable Claim(s).
`7. D For purposes of appeal, the proposed amendment(s): (a) El will not be entered, or (b) I:I will be entered, and an explanation of how the
`new or amended claims would be rejected is provided below or appended.
`AFFIDAVIT OR OTHER EVIDENCE
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`8. D A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`9. U The affidavit or other evidence filed after final action, but before or on the date of filing a Notice of Appeal will n_ot be entered because
`applicant failed to provide a showing of good and sufficient reasons why the affidavit or other evidence is necessary and was not earlier
`presented. See 37 CFR 1.116(e).
`10. [I The affidavit or other evidence filed after the date of filing the Notice of Appeal, but prior to the date of filing a brief, will n_ot be entered
`because the affidavit or other evidence failed to overcome a_H rejections under appeal and/or appellant fails to provide a showing of good
`and sufficient reasons why it is necessary and was not earlier presented. See 37 CFR 41 .33(d)( ).
`11. El The affidavit or other evidence is entered. An explanation of the status of the claims after entry is below or attached.
`REQUEST FOR RECONSIDERATION/OTHER
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`12. XI The request for reconsideration has been considered but does NOT place the application in condition for allowance because:
`See Continuation Sheet.
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`13. El Note the attached Information Disclosure Stafemenz‘(s). (PTO/SB/O8) Paper No(s).
`14. El Other:
`.
`STATUS OF CLAIMS
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`15. The status of the Claim(s) is (or will be) as follows:
`Claim(s) allowed:
`.
`Claim(s) objected to:
`Claim(s) rejected: 1-13, 18-58, 60-63, 69-71, 73, 76-116 and 118-130.
`Claim(s) withdrawn from consideration:
`
`/JEFIEMYJOW
`Examiner, Art Unit 2896
`U.S. Patent and Trademark Office
`PTOL-303 (Rev. 08-2013)
`
`/CHEUNG LEE/
`Primary Examiner, Art Unit 2896
`
`Advisory Action Before the Filing of an Appeal Brief
`
`Part of Paper No. 20140821
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`SAMSUNG ET AL. EXHIBIT 1035
`Page 6 of 6