l91§Z2.z2§
`.é.2p1iC4ti2:!1:1>l111:1t22£:.
`
`
`
`
`
`09-26-2003
`Filing or 371 (C) Date:
`
`
`
`Application Type:
`Utility
`
`
`
`LEWIS, MONICA
`Examiner Name:
`
`
`
`
`Group Art Unit:
`Confirmation Number:
`
`
`
`
`
`
`
`ELM-2 CONT. 4
`Attorney Docket Number:
`
`438/238
`Class / Subclass:
`
`
`.\\\\A\A\AV:\1:\1:\V:\\\\\\\\\\\\\\\\\\\\\x\x\x\x\\\\\\\\\\\\\\\A\A\AV:\V:\V:\!:\\\\\\\\\\\\\\\\\\\\\x\x\x\x\\\\\
`\\\\\\\\A\A\A1:\V:\1:\V:\\\\\\\\\\\\\\\\“
`
`
`
`First Named Inventor:
`Glenn Leedy , Saline, MI
`
`
`
`2822
`9439
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Three dimensional multi layer memory and control logic
`
`
`
`integrated circuit structure
`
`
`
`Commissioner for Patents
`
`
`
`
`
`P.O. Box 1450
`
`
`
`
`
`
`
`
`
`Alexandria, VA 223l 3-1450
`
`Sir:
`
`
`RESPONSE
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Responsive to the Office Action of 04/24/2009, please amend this application as
`
`follows.
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 1 of 15
`
`

`
`IN THE CLAIMS
`
`
`
`
`
`l-87. (Canceled)
`
`
`
`
`88.
`
`
`
`
`
`
`
`(Currently Amended) An integrated circuit structure comprising:
`
`
`
`
`
`
`
`
`
`
`
`a first substrate comprising a first surface having interconnect contacts
`
`and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a thinned second substrate comprising a first surface and El second stirlitce
`
`
`
`
`
`
`
`
`
`
`
`
`
`each having interconnect contacts . wherein the second surti-tee is o. 3t‘i.‘.\‘tlc
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the lirst surface and wherein the second surface ofthe second substrate is .<:»Iished; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`' onductive paths between the
`
`
`
`
`
`
`
`
`
`
`
`
`
`interconnect contacts of the first surfaces of the first substrate and said one (‘>l'l‘l1C first
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`surface ottlie second suhstrmt: and the second st.trt'n<:.e ol"the sccontl substratesrwheteie
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wherein the lirst stirtacc ofthe lirst substrate and one ol’thc tirst surliicc of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the second substrate and the second surface of the second substrate are bonded, the first
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` substrate overlapping at leasta majority of the firstsurtaeeeflthe
`<fi<l=5$S€COl1d substrate.
`
`
`
`
`89.
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 88, wherein the second
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrate is one of a thinned monocrystalline semiconductor substrate and a thinned
`
`
`
`polycrystalline semiconductor substrate.
`
`
`
`
`90.
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 88, wherein the circuitry
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`formed on the second substrate is one of active circuitry and passive circuitry.
`
`
`
`
`91.
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 88, wherein the circuitry
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`formed on the second substrate consists of both active circuitry and passive circuitry.
`
`
`
`
`92.
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 88, wherein the first substrate
`
`
`
`
`
`
`
`
`
`
`is a substrate having circuitry fomted thereon.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 2 of 15
`
`

`
`
`93.
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 92, wherein the circuitry of
`
`
`
`
`
`
`
`
`
`
`
`
`
`the first substrate is one of active circuitry and passive circuitry.
`
`
`
`
`94.
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 92, wherein the circuitry of
`
`
`
`
`
`
`
`
`
`
`
`
`
`the first substrate comprises both active circuitry and passive circuitry.
`
`
`95.
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure ofclaim 88, further
`
`
`comprising:
`
`
`
`
`
`
`
`
`
`
`
`at least one additional thinned substrate having circuitry formed thereon;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a first of said at least one additional thinned substrate being bonded to the
`
`
`
`
`
`
`
`
`
`
`
`
`
`second substrate and any additional thinned substrates being bonded to the directly
`
`
`
`
`
`
`adjacent additional thinned substrate; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`conductive paths formed between said first of said at least one additional '
`thinned substrate and at least one of said first and second substrates and also between
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`each additional thinned substrate and at least one of said substrates of the integrated
`circuit structure.
`
`
`
`
`
`96.
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, wherein at least two ofthe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`first, the second and the at least one additional thinned substrates are formed using a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`different process technology, wherein the different process technology is selected from
`
`
`
`
`
`
`
`
`
`
`
`
`the group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and
`
`
`
`
`Giant Magneto Resistance.
`
`
`97.
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 95, wherein at least one ofthe
`
`
`
`
`
`
`
`
`
`
`
`
`
`first, the second and the at least one additional thinned substrates comprises a
`
`
`
`
`microprocessor.
`
`
`98.
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 95, wherein:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`at least one substrate of the first, the second and the at least one additional
`
`
`
`
`
`
`
`
`
`thinned substrates has memory circuitry formed thereon; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`at least one substrate of the first, the second and the at least one additional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`thinned substrates has logic circuitry formed thereon that performs tests on the at least
`
`
`
`
`
`
`
`
`one substrate that has memory circuitry formed thereon.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 3 of 15
`
`

`
`
`99.
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 95, wherein at least one
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrate of the first, the second and the at least one additional thinned substrates has
`
`
`
`
`
`
`
`
`
`
`
`
`
`memory eircuitry formed thereon, the memory circuitry having a plurality ofmemory
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`locations, wherein at least one memory location of the plurality of memory locations is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`used for sparing and wherein data from the at least one memory location on the at least
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`one substrate having memory circuitry formed thereon is used instead of data from a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`defective memory location on the at least one substrate that has memory circuitry formed
`
`thereon.
`
`
`
`
`I00.
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, wherein:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`at least one substrate of the first, the second and the at least one additional
`
`
`
`
`
`
`
`
`
`thinned substrates has memory circuitry formed thereon; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`at least one substrate ofthe first, the second and the at least one additional
`
`
`
`
`
`
`
`
`
`
`
`
`thinned substrates has logic circuitry formed thereon that performs programmable gate
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`line address assignment with respect to the at least one substrate having memory circuitry
`formed thereon.
`
`
`
`
`lOl.
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, further comprising a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plurality of interior vertical interconnections that traverse at least one of the first, the
`second and the at least one additional thinned substrates.
`
`
`
`
`
`
`
`
`
`
`
`I02.
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, wherein information
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`processing is performed on data routed between the circuitry of at least two of the first,
`the second and the at least one additional thinned substrates.
`
`
`
`
`
`
`
`
`
`
`
`
`103.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, wherein at least one ofthe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`first, the second and the at least one additional thinned substrates has reconfiguration
`
`
`circuitry.
`
`
`
`104.
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, wherein at least one ofthe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`first, the second, and the at least one additional thinned substrates has logic circuitry
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`formed thereon for performing at least one function from the group consisting of: virtual
`
`
`
`
`
`
`
`
`
`memory management, ECC, indirect addressing, content addressing, data compression,
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 4 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`data decompression, graphics acceleration, audio encoding, audio decoding, video
`
`
`
`
`
`
`
`
`
`encoding, video decoding, voice recognition, handwriting recognition, power
`
`
`
`
`
`management and database processing.
`
`105.
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus ofclaim 95, further comprising:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a memory array having a plurality of memory storage cells, a plurality of
`data lines, and a plurality ofgate lines, each memory storage cell stores a data value and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`has circuitry for coupling the data value to one ofthe plurality ofdata lines in response to
`
`
`
`
`
`
`
`
`
`
`
`
`
`receiving a gate control signal from one ofthe plurality ofgate lines;
`
`
`
`
`
`
`
`
`
`
`
`
`
`circuitry that generates the gate control signal in response to receiving an
`
`
`
`
`
`
`
`
`
`
`
`address, including means for mapping addresses to gate lines; and
`
`
`
`
`
`
`
`
`
`
`
`
`a controller that determines ifone ofthe plurality of memory cells is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`defective and alters said mapping to remove references to the one of the plurality of
`
`
`
`
`
`memory cells that is defective.
`
`
`
`106.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 95, further
`
`
`comprising:
`
`
`substrate;
`
`
`
`
`
`
`
`
`
`
`
`at least one controller substrate having logic circuitry formed thereon;
`
`
`
`
`
`
`
`
`
`
`
`at least one memory substrate having memory circuitry formed thereon;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a plurality ofdata lines and a plurality of gate lines on each memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`an array of memory cells on each memory substrate, each memory cell
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`stores a data value and has circuitry that couples the data value to one of the plurality of
`
`
`
`
`
`
`
`
`
`
`
`
`
`data lines in response to selecting one of the plurality ofgate lines;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a gate line selection circuit that enables a gate line for a memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`operation, wherein the gate line selection circuit has programmable gates to receive
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`address assignments for at least one gate line of the plurality ofgate lines and wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`address assignments for determining which ofthe plurality ofgate lines is selected for
`
`
`
`
`
`each programmed address assignment; and
`
`
`
`
`
`
`
`
`
`
`
`
`controller substrate logic that determines if one memory cell of the array
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of memory cells is defective and alters the address assignments of the plurality of gate
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 5 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`lines to remove references to the gate line that causes the defective memory cell to couple
`
`
`
`
`
`
`
`
`
`
`
`
`a data value to one ofthe plurality of data lines.
`
`
`
`
`
`controller substrate logic:
`
`107.
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 106, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`tests the array of memory cells periodically to detennine if one of the
`
`
`
`
`
`
`
`
`
`
`array ofmemory cells is defective; and
`
`V
`
`removes references in the address assignments to gate lines that cause
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`detected defective memory cells to couple data values to the plurality of data lines.
`
`108.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 106, further
`
`
`comprising:
`
`
`
`
`
`
`
`
`
`
`
`
`
`programmable logic to prevent the use of data values from the plurality of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`data lines when gate lines cause detected defective memory cells to couple data values to
`
`
`
`
`
`the plurality ofdata lines.
`
`
`
`109.
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure ofclaim 106, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`array of memory cells are arranged within physical space in a physical order and are
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`arranged within an address space in a logical order and wherein the physical order of at
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`least one memory cell is different than the logical order ofthe at least one memory cell.
`
`
`
`1 10.
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 106, wherein:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the logic circuitry of the at least one controller substrate is tested by an
`
`
`
`
`external means; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the array of memory cells of the at least one memory substrate are tested
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`by the logic circuitry ofthe at least one controller substrate, wherein the testing achieves '
`
`
`
`
`
`
`
`
`
`
`
`
`
`a functional testing ofa substantial portion ofthe array of memory cells.
`
`I
`
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure ofclaim lQ6, wherein the
`l 1.
`
`
`
`
`
`
`
`
`
`
`
`
`
`logic circuitry ofthe at least one controller substrate performs functional testing ofa
`
`
`
`
`
`
`
`substantial portion ofthe array of memory cells.
`
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure ofclaim I06, wherein the
`I I2.
`
`
`
`
`
`
`
`controller substrate logic is further configured to:
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 6 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`prevent the use of at least one defective gate line; and
`
`
`
`
`
`
`
`
`
`
`
`
`replace references to memory cells addressed using the defective gate line
`
`
`
`
`
`
`
`
`
`
`
`
`with references to spare memory cells addressed using a spare gate line.
`
`
`1 13.
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 106, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`controller substrate logic is further configured to prevent the use of at least one defective
`
`
`
`gate line.
`
`
`
`
`
`
`
`
`
`
`
`
`(Currently amended) The structure ofclaim I06, wherein the logic
`
`
`
`
`
`
`
`
`
`
`
`
`
`circuitry of the at least one controller substrate [:)t*;"Frl«'t:)F§)1réég,‘_‘5ll_i_jQ‘<».‘%l:,l:(3,I:l4_Wll, all functional testing
`
`I 14.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of the array of memory cells of the at least one memory substrate.
`
`
`is a non-semiconductor material.
`
`
`
`
`
`115.
`
`
`
`
`
`
`
`
`
`
`(Withdrawn) The apparatus of claim 88, wherein the first substrate
`
`
`
`(Currently Amended) An integrated circuit structure comprising:
`I 16.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a first substrate having topside and bottomside surfaces, wherein the
`
`
`
`
`
`
`
`
`
`
`
`topside surface of the first substrate has interconnect contacts ;
`
`
`
`
`
`
`
`
`
`
`
`
`a thinned second substrate having topside and bottomside surfaces,
`
`
`
`
`
`
`
`
`
`
`wherein the to )siclc surfiice and the bottomside surface of the.second substrate
`interconnect contacts . and wherein the bottomside surface ofthe second
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.~::ubstratc is mlishecl;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wherein a major portion ol't-he
`
`
`
`
`
`
`
`
`
`
`
`
`
`‘ the topside surface of the first substrate
`
`
`and one nt‘l.hc to aside siirlizicc <;»l'1,l1c scctinicl suhs;lr::1te and the ‘4)<)‘i‘y(‘)|“,]Itl:i(:‘t‘ sLnr'I‘acc of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`sctzond stlbstrate are honcled tonctlmcr; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`conductive paths lemwdbetween the interconnect contacts on the topside
`
`
`
`
`
`
`
`
`
`
`
`
`
`surface ofthe first substrate and ._.s__z_1_i_d__onc <;il"tl1c to aside surl’:-ice oltlic scconcl sirhslratc
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and the bottomside stlrlhcc of the second substrate, the conductive paths providing
`
`
`
`
`
`
`
`
`
`
`
`
`electrical connections between the first substrate and the second substrate
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wherein the
`
`
`
`
`
`'.
`
`
`
`
`
`
`uver|u11§_at leastamajority of the 1
`
`
`
`
`
`2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3 4* ‘
`
`
`
`
`
`7
`
`'_
`
`
`
`i‘
`
`
`
`'firstsubstrate
`
`
`
`
`” second substrate.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 7 of 15
`
`

`
`1 l7.
`
`
`
`
`
`
`
`
`
`
`
`
`(Currently Amended) The integrated circuit structure of claim 116,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wherein selected ones of said interconnect contacts said topside surface of said first
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrate are in electrical contact with selected ones of the interconnect contacts mg‘
`said bottomside surface of said second substrate so as to form said electrical connections.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`I l8.
`
`
`
`
`
`
`
`
`
`
`(Currently Amended) An integrated circuit structure comprising:
`
`
`
`
`
`
`
`
`
`a first substrate having a first and second surface;
`
`
`
`
`
`
`
`
`
`
`
`
`a second substrate having a first and second surface, wherein said second
`
`
`
`
`
`
`
`
`
`
`
`
`
`surfaces of the first and second substrates are opposite to said first surfaces;
`\\«'ht:rein at ltzast one of the first substmte and the second stibstiate is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`,lV_i,l,'lVt_tl'it’3(l to l_'orm at least one t_liii_im-gd 5Lll3_:3l,[;gL§_.
`
`
`
`
`
`
`
`
`
`tl_l],§L\_fl_l_t§i‘§:Qj,lf}Mlh§g_$§§§fl1(,LSUI‘litC€ ofthe at
`
`
`
`
`
`least one thinned substrntt-2
`
`
`
`
`
`polished:
`
`
`
`
`
`
`
`
`
`
`
`
`
`wherein the first surface of the first
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrate and a maior portion ofonc oi" the first surface ofthe second substrate and the
`second surface ofthe second substrate are bonded by at least one bond. wlierein the at
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`least one bond secures :1 major portion of the second substrate to the lirst substrate; and
`
`
`
`
`
`
`
`
`
`
`
`
`conductive paths f9m+ed—eisl3etween at least two ol'the first surfaces of the
`
`
`
`
`
`
`
`
`
`
`
`
`first substrate and the first and second sttrfaces oi’ the second substrates,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`, wliercin the first
`
`
`
`
`
`
`
`
`
`
`seeeneksubstrate ovei'|zip. 5 at least a majority of the ’”
`second substrate.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1 19.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim I 16, further
`
`
`comprising:
`
`
`
`
`
`
`
`
`
`
`
`at least one additional thinned substrate having circuitry formed thereon;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a first of said at least one additional thinned substrate being bonded to the
`
`
`
`
`
`
`
`
`
`
`
`
`second substrate and any additional thinned substrates being bonded to the directly
`
`
`
`
`
`
`adjacent additional thinned substrate; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`conductive paths formed between said first of said at least one additional
`thinned substrate and at least one of said first and second substrates and also between
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 8 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`each additional thinned substrate and at least one of said substrates of the integrated
`circuit structure.
`
`
`
`I20.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure ofclaim I 19, further
`
`
`comprising:
`
`
`substrate;
`
`
`
`
`
`
`
`
`
`
`
`at least one controller substrate having logic circuitry formed thereon;
`
`
`
`
`
`
`
`
`
`
`
`at least one memory substrate having memory circuitry fonned thereon;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a plurality ofdata lines and a plurality ofgate lines on each memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`an array of memory cells on each memory substrate, each memory cell
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`stores a data value and has circuitry that couples the data value to one of the plurality of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`data lines in response to selecting one ofthe plurality of gate lines;
`
`
`
`
`
`
`
`
`
`
`
`
`a gate line selection circuit that enables a gate line for a memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`operation, wherein the gate line selection circuit has programmable gates to receive
`address assignments for at least one gate line of the plurality of gate lines and wherein the.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`address assignments for determining which of the plurality ofgate lines is selected for
`
`
`
`
`
`each programmed address assignment; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`controller substrate logic that determines ifone memory cell ofthe array
`
`
`
`
`
`
`
`
`
`
`
`
`
`of memory cells is defective and alters the address assignments ofthe plurality ofgate
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`lines to remove references to the gate line that causes the defective memory cell to couple
`
`
`
`
`
`
`
`
`
`
`
`
`a data value to one of the plurality of data lines.
`
`121.
`
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, wherein the
`
`
`
`
`controller substrate logic:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tests the array ofmemory cells periodically to determine ifone of the
`
`
`
`
`
`
`
`
`array ofmemory cells is defective; and
`
`
`
`
`
`
`
`
`
`
`
`
`removes references in the address assignments to gate lines that cause
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`detected defective memory cells to couple data values to the plurality ofdata lines.
`
`122.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, further
`
`
`comprising:
`
`
`
`
`
`
`
`
`
`
`
`
`
`programmable logic to prevent the use of data values from the plurality of
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 9 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`data lines when gate lines cause detected defective memory cells to couple data values to
`
`
`
`
`
`
`the plurality of data lines.
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`array of memory cells are arranged within physical space in a physical order and are
`
`l23.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`arranged within an address space in a logical order and wherein the physical order of at
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`least one memory cell is different than the logical order of the at least one memory cell.
`
`124.
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, wherein:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the logic circuitry of the at least one controller substrate is tested by an
`
`
`
`
`external means; and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the array of memory cells of the at least one memory substrate are tested
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
`
`
`
`
`
`
`
`
`
`
`
`
`
`a functional testing ofa substantial portion ofthe array of memory cells.
`
`
`
`125.
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`logic circuitry ofthe at least one controller substrate performs functional testing ofa
`substantial portion ofthe array ofmemory cells.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim I20, wherein the
`
`
`
`
`
`
`
`controller substrate logic is further configured to:
`
`126.
`
`
`
`
`
`
`
`
`
`
`
`prevent the use of at least one defective gate line; and
`
`
`
`
`
`
`
`
`
`
`
`replace references to memory cells addressed using the defective gate line
`
`
`
`
`
`
`
`
`
`
`
`
`
`with references to spare memory cells addressed using a spare gate line.
`
`127.
`
`
`
`
`
`
`
`
`
`
`
`
`(Previously Presented) The structure of claim 120, wherein the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`controller substrate logic is further configured to prevent the use of at least one defective
`
`
`
`gate line.
`
`128.
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Currently amended) The structure ofclaim I20, wherein the logic
`
`
`
`
`
`
`
`
`
`circuitry of the at least one controller substrate C€lll
`
`
`
`
`
`
`
`
`
`
`of the array of memory cells of the at least one memory substrate.
`
`
`
`
`
`
`
`
`perform all functional testing
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 10 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`
`(New) The structure ofclaim 88, wherein the second substrate is
`129.
`thinned to about 50 microns or less.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(New) The structure of claim 1 16, wherein the second substrate is
`130.
`thinned to about 50 microns or less.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(New) The structure of claim I 18, wherein the second substrate is
`thinned to about 50 microns or less.
`
`
`
`
`
`
`
`
`131.
`
`
`132.
`
`
`
`
`
`
`
`
`
`
`
`
`
`(New) The structure of claim 88, wherein the first substrate and the
`
`
`
`
`
`
`
`
`
`
`
`second substrate are the same size or overlap each other completely.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(New) The structure of claim 1 16, wherein the first substrate and
`
`
`
`
`
`
`
`
`
`
`
`the second substrate are the same size or overlap each other completely.
`
`
`I33.
`
`
`
`134.
`
`
`(New) The structure of claim 1 18, wherein the first substrate and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the second substrate are the same size or overlap each other completely.
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 11 of 15
`
`

`
`REMARKS
`
`
`
`
`
`
`
`
`
`
`
`The Office Action of 04/24/2009 has been carefully considered.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Claims 110 and 124 were indicated as containing allowable subject matter, which
`
`
`
`
`
`
`indication is appreciatively acknowledged.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Claims 88, 95 and 116-119 were rejected as being unpatentable over Sugiyama in
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`View of Watanabe (newly cited) and further in view of Leedy. (Although page 3 of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`rejection refers only to Sugiyama and Watanabe, page 4 of the rejection refers also to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Leedy. The omission from Leedy in the initial statement of the rejection is therefore
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`believed to be in error.) Claims 106-108, 111-114, 120-122 and 125-128 were rejected as
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`being unpatentable over the same base combination further in View of F aris and Sakui.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Claims 109 and 123 were rejected as being unpatentable over the prior combination
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`further in view of Daberko. The claims have been amended to more clearly distinguish
`
`
`
`
`
`
`
`
`
`
`
`
`
`over the cited references. Dependent claims 129-134 have been newly added.
`
`
`
`
`
`
`Reconsideration is respectfully requested.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`More particularly, independent claims 88, 116, and 118 have been amended to
`
`
`
`
`
`
`
`
`
`
`
`recite in part a thinned substrate having a polished surface. Surface polishing achieves
`
`
`
`
`
`
`
`
`
`
`
`
`
`stress relief and provides a smooth surface for the formation of interconnect
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`metallization. None of the cited references is believed to teach or suggest such surface
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`polishing with respect to a thinned substrate. All of the claims are therefore believed to be
`
`
`
`
`
`
`
`
`
`
`
`
`allowable over the prior art for at least this reason.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`With respect to the prior obviousness rejection, although this rejection is believed
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to be no longer applicable, it is also believed to be significantly flawed, as set forth
`
`below.
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 12 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Reiection of Claims 88, 95 and 116-119 as Ungatentable Over Sugiyama in View of
`
`
`
`
`
`Watanabe Further in View of Leedy
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In the prior Office Action, the claims were rejected as being unpatentable over
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Sugiyama in view of Leedy. The purported motivation for combining the teachings of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Sugiyama and Leedy was “to provide structural integrity.” In the prior Response,
`
`
`
`
`
`
`
`
`
`
`
`
`
`Applicant disputed this motivation as lacking technical merit. This argument was
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`apparently found to be persuasive, resulting in the present Office Action in which the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`claims are rejected as being unpatentable over Sugiyama in View of Watanabe fL1I‘tl161‘ in
`
`
`
`
`
`view of Leedy.
`
`
`
`
`
`
`
`
`
`
`
`
`
`However, the same supposed motivation for combining the teachings of Leedy
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`with those of Sugiyama and Watanabe is citcd—“to provide structural integrity.” This
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`motivation is believed to be technically unsound for the reasons set forth in the prior
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`reply. That is, the substrates of Sugiyama are, to all indications, of ordinary thickness
`
`
`
`
`
`
`
`
`
`
`
`
`
`(e.g., 300-500 microns).The structural integrity of substrates of such ordinary thickness
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`without the need of any further measures is well-established and demonstrated. Hence,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`contrary to the rejection, Sugiyama has no need of the techniques of Leedy for ensuring
`
`
`
`
`
`
`
`
`
`
`structural integrity of a thinned substrate or IC membrane.
`
`
`
`
`
`
`
`
`
`
`
`
`
`Furthermore, the problem of proper motivation to combine has only been
`
`
`
`
`
`
`
`
`
`
`
`
`
`compounded with the proposed additional combination of Watanabe. Watanabe teaches a
`
`
`
`
`
`
`
`
`
`
`
`
`
`technique for making an IC assembly having two ICs made of dissimilar semiconductor
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`materials, namely silicon and gallium arsenide. The silicon wafer is thinned and adhered
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to a sapphire wafer. Following dicing, a relatively small gallium arsenide IC is bonded to
`
`
`
`
`
`
`
`
`
`the silicon IC. The sapphire substrate provides thermal matching.
`
`
`
`
`
`
`
`
`
`
`
`
`The Watanabe technique is wholly inapplicable to Sugiyama. Sugiyama teaches
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the face—to—face bonding of two IC wafers. There is no opportunity for the bonding of a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`further IC subsequent to dicing—the surfaces that might otherwise be bonded to are
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`internal to the Sugiyama structure. Without such subsequent bonding, there would be no
`
`
`
`
`
`
`
`
`
`
`need for the thermal matching substrate, ie, the sapphire substrate.
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 13 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`As no reasonable motivation has been identified for combining the teachings of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the references in the manner indicated, the cited references are not believed to teach or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`suggest the invention of claim 88, particularly as it has now been amended to recite in
`
`
`
`
`
`
`
`
`part a thinned substrate having a polished surface.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The same argument applies equally to claims 116 and 119. Hence, it may be seen
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`that the cited references do not teach or suggest the invention of claims 88, l 16 or l 19.
`
`
`
`
`
`
`
`
`
`Withdrawal of the rejection is respectfully requested.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The various combinations of references used to reject the dependent claims do
`
`
`
`
`
`
`
`
`
`
`
`
`
`nothing to address the teachings absent from the base combination as noted above.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Therefore, the dependent claims are believed to be allowable as depending on an
`
`
`
`allowable base claim.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Applicant further reiterates that motivation to combine is not supplied merely by
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`two references being from the same field of endeavor (e.g., two integrated circuits). Ifa
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`proposed combination would make no reasonable sense to a person of ordinary skill in
`
`
`
`
`
`
`
`
`
`
`the art, motivation to combine is necessarily lacking.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`As there has been ample opportunity during prosecution of the present application
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`for a case of obviousness to be established (if the prior art will indeed support such a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`finding), and since no primafacie ease of obviousness is believed to have been
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`established, allowance of the present application is believed to be in order and is
`
`
`
`
`respectfully requested.
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 14 of 15
`
`

`
`
`
`
`
`
`
`
`
`
`
`
`Withdrawal of the rejections and allowance of claims 88, 95, 106-109, ll 1-ll4,
`
`
`
`
`
`
`
`
`l 16- l 23 and l25-l 34 is respectfully requested.
`
`
`
`
`Respectfully submitted,
`
`
`
`/Michael J. Ure/
`
`
`
`
`
`
`
`
`
`Michael J. Ure, Reg. 33,089
`
`
`
`
`
`Dated: 6/'25/2009
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1029
`Page 15 of 15