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`I HEREBY CERTIFY THAT THIS CORRESPONDENCE TS RFITNG F‘A(‘.STMTI'.T-'2 WHANSMITTED TO THE
`PATENT AND TRADEMARK OFFICE ON THE DATE SHOWN BELOW.
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`Name of peraon signing certification:
`Sharon E. Ryan
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`Date:
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`Signature:__,_V_§'¢-4-‘_-9'--'
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`Attorney's Docket No. 9933525251
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`In re Pa rem Application of
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`Application No.: 08/835,190
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`Filed: April 4. 1997
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`For: THREE DIMENSIONAL
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`STRUCTURE MEMORY
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`\.l\J\_/\_IN.J‘\—’\-udfi-—P\ud'\_f
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`Group Art Unit: 1104
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`Examiner: Collins. D.
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`BEfl
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`oaaaswo
`05/20/1995 csmamr eoeoooos oawoo
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`143_o01gfisistant Commissioner for Patents
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`41.00\fi&-.-shingtun, D.C. 20231
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`Sir:
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`Responsive to the Office Action of January 28, 1998, please amend this application as
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`follows:
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`LDSIOSIIMG JPRIIITOR 00000011 025800
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`55. N CH
`M runs
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`1. (Amended) A method of forming a re.ndom—acccss memory, comprising the steps of:
`fabricating a memory circuit on a first substmtc;
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`00635190
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`fabricating a memory wntrullcr circuit on a second substrate; [and]
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`bonding the firs: and second substrates to form interconnects betwcen the
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`39:1! an; 86~90—Aki:-I Mueduloo
`:.Iaqu1nN xeg
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`4;;
`sets/9
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`:safied
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`(pepaaoang wang) we/x3 pengaoaa
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`SAMSUNG ET AL. EXHIBIT 1024
`Page 1 of 13
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 2
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`memory circuit and the memory comroller circuit, neither the first substrate alone nor
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`the second substrate alone being sufficient to provide random aoeess data storage,
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`"l%(An1ended) The method of Claim 1, [wherein said bonding is thermal diffusion
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`bonding of the first substrate to the second substrate to form a stacked IC structure, the
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`method] comprising the further steps of:
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`fabricating at least one additional memory circuit on at least one additional
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`substrate; and
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`bonding the at least one additional substrate to the stacked IC substrate and
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`forming interconnects between the at least one additional memory circuit and the
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`memory controller circuit. wherein at least some of the interconnects pass through a
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`substrate on which a memory circuit is formed.
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`;(A1-mended) The method of [Claim 14, further comprising the step of:
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`:adKJ_
`zmafqns
`uapuas
`ieulll.
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`ESIH Elfll. 88-90-NH :&ueduJo3
`:.IaqumN xed
`:seBed
`33190
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`tr],
`BGIQIQ
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`(papaaoons iuang) iuana panyaoea
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`SAMSUNG ET AL. EXHIBIT 1024
`Page 2 of 13
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`Application Serial}-To. D8}835,190
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`Attorney's Docket No. 0084-42-05?
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`thinning substrates on which tnemory_circuit.s are formed to form thinned
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`substrates. facilitating formation of said interconnects]
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`(Amended) A method of bonding together multiple substrates each having
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`integrated circuits formed thereon to form interconnections between the integrated circuits, the
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`method comprising the steps of:
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`processing 8. mating surface on each of first and second substrates to achieve
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`substantial planarity of the mating surfaces;
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`forming mating. fne-grain interconnect patterns on the mating surfaces; [and]
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`petformirtg fine—grairi, planar thermal diffusion bonding of the mating
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`surfa.ces[.];;13Q
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`Z—i‘. (Amended) The method of Claimg: [further comprising the step of:
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`fliinning substrates on which memory circuits are formed to form thinned
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`subsuates, facilitating formation of said interconnects]
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`:adAi
`uoafqns
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`uapuas
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`I/\|d 51752
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`29:11 am, 88-90—A9N Muedwoo
`uaqumu X95
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`1;],
`8619/9
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`:safie¢|
`19190
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`(papaaaons 1uaA3) 3U9A3 pa/uaaaa
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`SAMSUNG ET AL. EXHIBIT 1024
`Page 3 of 13
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`Appiication Serial No. 08/835,190
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`Attorney‘; Docket No. 008442-057
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`Page 4
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`Please add the fonowing new Claims:
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`include interconnect metallimtion and non-interconnect metallization;
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`whereby thermal diffusion bonding simultaneously achieves electrical
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`interconnection through said interconnect metallization and mechanical bonding through
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`said non-interconnect metallization.
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`6?
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`/95 The method of claim)2’ wherein. prior to said thermal diffusion bonding, at lent
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`one of the surfaces to be bonded is planarized using chemical/mechanical polishing.
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`(A
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`34? The method of claim)3’, whcrcin both of the suxfaces to be bonded an: planarizcd
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`using chemical/mechanical polishing.
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`957 The method of claim 1, wherein said substrates are semiconductor wafers.
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`wafer into individual stacked ICs.
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`6f’
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`9?’. The method of claim 1, wherein said memory controller circuit and said. memory
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`circuit are formed using low-stress dielectric.
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`:BdKJ_
`zzoafqns
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`uapuas
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`mun
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`Wcl svrz
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`179! [1 EM. 86-90-AUH IKUWLUOO
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`17L
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`96/919
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`men
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`(papaaoons iuana) iuang pangaoau
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`SAMSUNG ET AL. EXHIBIT 1024
`Page 4 of 13
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`Attorney's Docket No. 008442-057
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`Page 5
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`/‘lb’. The method of cIaim..i4/,’comprlsing the further Step of, during backside processing
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`of a final substrate to form part of said random-access memory. forming bond pads on the
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`backside of the final substrate.
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`2.‘?
`(» 9
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`/99'. The method of Clairnjiéf wherein surfaces bonded by thermal diffusion bonding
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`include interconnect metallization and non—inix:rconnect mezailization;
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`whereby thermal diffusion bonding simultaneously achieves electrical
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`interconnection through said interconnect metallization and mechanical bonding through
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`L90. The method of claim fl,/wherein, prior to said thermal diffusion bonding, at least
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`one of tin: surfaces to be bonded is planarized using chemical/meciianical polishing.
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`/1491’. The method of claim , wherein both of the surfaces to be bonded are planarizecl
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`using cheniicaifmechanical polishing.
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`}92’. The method of claim 532‘, wherein said subsnates are semiconductor wafers.
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`J33’. The method of claim 1/Oilfcomprising the further step of dicing a resulting
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`i?9=II Elli 86-90-AW IKUPCHUOO
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`SAMSUNG ET AL. EXHIBIT 1024
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`Application Serial NO. 08/835.190
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`Atbo1'ney's Docket No. 008442-057
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`Z‘?
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`_1.0{,=l-'. The method of claim,62, wherein said integrated circuits are formed using low-
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`}_.95. The method of cIai1n)9,/comprising the funlter step of, during backside
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`on the backside of the final substrate.
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`mory structure comprising:
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`a first substrate; at
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`a second substrate bond
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`to
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`substrate to form conductive paths
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`EEMA1SK§
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`The Office Action of January 28, 1998 has been carefully considered.
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`In response
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`thereto, the claims have been amended as set forth above, Withdrawal of the rejection and
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`allowance of the present application in view of the foregoing amendments and the following
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`remarks is respectfully requested.
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`3°dKJ.
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`:;oa.fqns
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`5°“*LL
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`99: II Hfll 88-S0-AU“ =KUBdl1l0O
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`vi,
`8619/9
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`(papaaoons many) tuang pangeoay
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`Page 6 of 13
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Claims 1 and 62 were rejcctetl as being anticipated by Yasumoto et al. Claims 2-30 and
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`63-91 were rejected as being unpatentahic over Yasumoto et al. in view of various secondary
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`references, including Grcenwald et al., Val. Goosscn. Naktamishi et a1.. Sanders and Thomas
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`et a1. Claims 1 and 62 have been amended to more clearly define over the cited references.
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`Reconsideration is respectfully requested.
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`More particularly, Claim 1 has been amended to recite forming a stacked IC structure
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`by thermal diffusion bonding of a memory circuit on a first substrate and a memory controller
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`circuit on a second substrate. including thinning and processing the backside of one of the
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`substrates to form interconnections that pass through the substrate and to form contacts on the
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`backside of the substrate. No such features are taught or suggested by the cited references.
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`The bonding and interconnect methods, especially, of the invention of Claim 1 are far
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`different from those of the prior art. In accordance with the invention, bonding occurs by
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`thermal diffusion bonding. As described in the specification, various metals commonly used in
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`semiconductor processing are particularly amenable to thermal diffusion bonding in which
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`cornplementany surfaces are bonded together through the application of heat and pressure. A
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`requirement for thermal diffusion bonding is that the complementary surfaces be highly planar.
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`This degree of plaruu-ity is achieved using a semiconductor processing technique of only recent
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`origin known as Chemical Mechanical Polishing, or CMP. The materials and methods used to
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`perform thermal diffusion bonding as described and claimed are fully compatible with existing
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`semiconductor processing techniques. Hence, a bonding step may be followed by further
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`H/90 ‘d
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`i3¢MJ.
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`:1oa_rqn3
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`99111 30.1. 88-SD-AUH 35U?dW°9
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`1:1,
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`86/99
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`:.IaqtunN X23
`:safied
`29190
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`(popaaoons iuena) luang paniaoaa
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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`semiconductor processing, which may in turned be followed by a further bonding step. etc. A
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`three-cllrnensiorlal device stack having a large number of device layers may thereby be
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`produced. Furthermore. three-dimensional processing is performed at the wafer level as
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`opposed to at the chip level. The number of work pieces to be handled is therefore greatly
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`reduced, typically several hundred-fold. as compared to three-dimensional processing
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`techniques performed at the chip level.
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`Yasumoto performs bonding together offinished chips to form three-dimensional
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`structures. (Yasumoto. col. 10, lines 6-17; col. 13, lines 38-40.) Further conventional
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`semiconductor processing steps (which are invariably performed in wafer form) are not
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`contemplated, but rather are precluded. In Yasumoto, bonding depends upon an adhesive resin
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`layer. This layer is intended to address the planarity problem, which could not have been
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`addressed by CMP, since thereferencc predates by nearly a decade the advent of CMP. (The
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`use of such adhesive resin layers would, by itself, be likely to preclude further conventional
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`semiconductor processing of a threetlirnensional structure in that such layers cannot, in
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`general, tolerate the high levels of heat associated with typical semiconductor processes.)
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`Also in accordance with the invention, interconnects are formed that pass entirely
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`through whole substrates. This interconnect structure is referred to in the specification as fine-
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`grajn vertical interconnect. As mnher descrflaed in the specification. such fine grain vertical
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`interconnects are formed by thinning and backside processing of a preceding substrate and
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`complementary frantside processing of a succeeding substrate.
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`(Specification, page 15, step
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`991! I Hill. 86-S0-AW MUBGWOO
`:Jaqu1nN xeg
`:-safied
`331*‘-‘Cl
`
`pt
`86lS/9
`
`(papaaoons iuang) iut-mg panacea
`
`SAMSUNG ET AL. EXHIBIT 1024
`Page 8 of 13
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`

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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 9
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`3), followed by bonding of the backside and complementary frontside. This sequence may be
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`repeated an arbitrary number of times to produce 9. stacked IC of 10 layers, 20 layers or more.
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`None of the references teach or suggests an interconnect that passes through a substrate.
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`Accordingly, all of the references are limited to two circuit layers where those circuit Iayers
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`are formed within a substrate. Yasutnoto (col. 12, lines 60-64) alludes to the possibility of a
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`three-dimensional semiconductor structure having four or more multilayer structure portions
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`obtained when two or more of the multilayer structural portions 118 are provided between two
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`outer multilayer structural portions 24 and 24'. The intermediate circuit layers of such :1
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`stmcture, however, are not fonnetl within a substrate but rather are thin-film transistor layers
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`formed an a substrate with the substrate being subsequently removed. (Yasumoto, Figure 7 and
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`8. Interconnects 112 and 134 pass through 21 TFT device layer but do not pass through a
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`substrate. the substrate having been removed.) Only in the case of the two outer multilayer
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`structure] portions 24 and 24' is the circuit layer formed within the substrate.
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`The following table identifies for each figure in Yasumoto the substrates shown in that
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`figure.
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`In no instance does an interconnect pass through the substrate.
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`bl/UI ‘d
`
`zadtt
`uaelqns
`IJBPIIBS
`=9l"!J.
`
`99:11 in 88-S0-AW rfluedwoo
`:1aqu.InN X33
`:safied
`:91!‘-‘CI
`
`vt
`86.“;/9
`
`(pepaaoons ruang) ruang paageoeu
`
`SAMSUNG ET AL. EXHIBIT 1024
`Page 9 of 13
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`

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`Application Serial N0. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 10
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`12. 12'
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`,
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`84 (multilayer structure not shown:
`col. 11. lines 6-7)
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`TABLE I
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`YASUMO no-URE
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`Fi re1(f}
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`F
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`s
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`The same analysis applies equally to each of the secondary references.
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`A fine-grain interconnect structure passing through a substrate can only be formed if
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`the substrate is very thin. A small hole (less then 1 um) might be formed in a conventional
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`thick substrate, but the aspcct ratio of the hole would be so large (e.g., 75:1 to 350: 1) as to
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`make filling the hole with metal impossible using known techniques. Of the cited references.
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`Sanders was cited as disclosing a multiple chip package with thinned semiconductor chips
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`using a grinding disk to remove material. Sanders, however, teaches backside circuit thinning
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`(in die form, not wafer form) for the purpose of cooling. None of the references teaches or
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`suggests the formation of a fi.nc—grain vcrtical interconnect through a substratc in the manner of
`claim 1.
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`The technique of Yasumoto, besides being limited to only two device—bearing
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`substrates, is limited in various other important respects. Referring to Figure 4 and 5 of
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`Yasumoto, for example. the only way to provide for connection to a three-dimensional
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`structure of the type disclosed in Yasumoto is for one layer to have a largcr extent than another
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`171/31 ‘:1
`
`IBCMJ.
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`uaefqns
`
`uapues
`=°lU!.I.
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`86/9/9
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`26130
`
`(papaaaons JLIQAQ) JUOAQ POMBOSH
`
`SAMSUNG ET AL. EXHIBIT 1024
`Page 10 of 13
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`

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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 11
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`layer. A portion of the surface of the larger layer therefore remains exposed, allowing bond
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`pads to be formed thereon. The hand pads may he wire bonded to leads of an MCM (multi-
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`chip module) package, for example. In the ease of the present invention. as recited in claim
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`96, bond pads are formed on the backside of a final thinned substrate. The resulting multilayer
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`structure is therefore comparable, in size and bond pad layout, to a single conventional
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`integrated circuit, compatible with existing single-chip packages.
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`Another problem not discussed in Yasumoto is that of film stress. Semiconductor films
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`are not stress-free but exhibit certain stress levels depending on many factors including
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`material, deposition techrlique, etc. A thick film exhibits proportionally greater stress than a
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`thin film. Stress is relieved either by bending or cracking — i.e_, either the substrate gives or
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`the film gives. Using conveniional higher-stress dielectric films of silicon dioxide and silicon
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`nitride (commonly used in conventional memory circuit fabrication), the technique of
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`Yasurnoto would likely be limited to no more than three layers as shown in Figure 8.
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`Additional layers would be likely to cause peeling apart of the layers at the adhesive interface.
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`In the case of the present invention. on the other hand, Iow«sr.ress dielectrics (less than
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`5 x 10‘ dynes (cm’) are used as described on page 14 of the present specification and further
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`described in US. Parenr 5,354,695 of the present inventor. Stress buildup and consequent
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`bending or cracking is therefore avoided. The number of layers is not stress-limited.
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`A summary of some of the most salient differences between Yasumomo and the present
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`invention, together with an indication of where that difference is reflected in the claims, is
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`presented in the following table:
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`DI/21 ‘d
`
`236151.
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`
`SAMSUNG ET AL. EXHIBIT 1024
`Page 11 of 13
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`

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`Application Serial No. 08/835,190
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`Attorney's Docket No. 008442-057
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`Page 12
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`PRESENT INVENTION
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`Begin with wafer fabricated
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`using low-stress dielectrics
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`Bond additional wafer
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`(fabricated using low-stress
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`dielectrics) to previous wafer
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`by thermal diffusion bonding,
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`e.g.. metal thermal diffusion
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`bonding.
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`Thin backside of additional
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`wafer, process backside to
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`form contacts
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`Repeat bonding and thinning
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`steps for as many wafers as
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`desired.
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`Form bond pads on backside of
`final wafer.
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`RELEVANT CLAIM
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`LANGUAGE
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`...wherein said substrates are
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`semiconductor wafers...
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`(claims 95, 102); ...fcrmed
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`using low-stress dielectric...
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`(claims 97, 104)
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`_. .said bonding is thermal
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`diffusion bonding of the final.
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`substrate to the secnnd
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`substrate... (claims 1, 62)
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`...the backside of one cf said
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`substrates is thinned and then
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`processed to form
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`iI1.lBl.'COllI1ECti0l'lS that pass
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`through said substrate and to
`form contacts on the backside
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`of said substrate... (claims 1,
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`G2)
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`...bonding at least one
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`additional substrate to the
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`stacked IC substrate... (claims
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`14 and 55)
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`...forming bond pads on the
`backside of the final
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`substrate... (claims 98. 105)
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`Begin with chip (die) having
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`topmost adhesive layer, with
`contacts through adhesive
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`layer.
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`Prepare additional chip (die)
`having adhesive layer, device
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`layer, then substrate, with
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`contacts through adhesive layer
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`and device layer: bond together
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`with previous chip, adhesive
`layer first.
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`Remove substrate
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`Repeat preparing, bonding and
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`removing steps for as many
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`chips as technology constraints
`(stress, adhesive degradation
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`from heat) allow.
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`Bond additional chip (die),
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`leave substrate; either first chip
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`or last chip must have larger
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`area. to allow for band pads.
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`Dice wafer stack into 3D chips.
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`...dicing 2 resulting stacked
`wafer into individual stacked
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`ICs... (claims 95, 103)
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`:ad)i_]_
`noafqns
`uapuas
`:aLuu_
`
`89:11 am. 86-90-AUN Muedwoo
`:.laql..llI"IN xe:|
`
`Vl-
`
`86/919
`
`:sa5ed
`:a12a
`
`(pepaaoons tuana) zue/\;| pemaoau
`
`SAMSUNG ET AL. EXHIBIT 1024
`Page 12 of 13
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`

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`Page 13
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`Claim 62 has been amended to recite thinning substrates on which integrated circuits
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`are formed to form thinned substrates, facilitating formation of interconnects, and performing
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`backside processing of the substrates. Thinning of a substrate is technically very different
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`from removing a substrate. As recited in claim 75, in the preferred embodiment of the present
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`invention, a substrate is thinned such that a thin device layer remains. Deviw-‘:3 within this
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`device layer are formed within a portion of the substrate. which may be nionocrystalline
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`silicon, for example. High-quality transistors result. Where devices are formed on (not within)
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`a substrate which is later removed, as in Yasurnoto, the device layer, because it is not part of
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`the substrate, remains when the substrate is removed. However, the quality of the transistors
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`that may be formed in such a layer suffers. While the quality of such transistors may suffice
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`for purposes of an LCD display, for example, the quality does not generally sutfice for
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`realizing a memory or memory controller.
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`Again. none of the prior art references teaches or suggests the combination of features
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`of claim 62. New claims 92-104 have been added drawn to various other significant features of
`the invention.
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`Accordingly, Claimsl and 62 are believed to patentably define over the cited
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`references, as is newly-added independent claim 106. Claims 2-30 and 63-103 are also
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`believed to add novel and patentable subject matter to their respective independent claims.
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`Withdrawal of the rejection and allowance of Claims 1-30 and 62-106 is therefore respectfully
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`requested.
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`Post Office Box 1404
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`Alexandria, Virginia 22313-1404
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`(650) 854~7400
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`Date: Apri128. 1998
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`Respectfully submitted,
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`BURNS, DOANE, SWECKER & MATI-IIS, LLP
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`
`
`
`By:
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`Michael I.
`Registration No. 33,089
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`39:11 am. es—9o5¢yii,w°3 ‘
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`86/919
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`19190
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`(PSPGOOOHS JUBAQ) IUOAQ pa/lgaoag
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`SAMSUNG ET AL. EXHIBIT 1024
`Page 13 of 13