THREE DIMENSION STRUCTURE MEMORY
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to stacked integrated circuit memory.
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`2. State of the Art
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`Manufacturing methods for increasing the performance and decreasing the cost of electronic
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`circuits, nearly without exception, are methods that increase the integration of the circuit and
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`decrease its physical size per equivalent number of circuit devices such as transistors or
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`capacitors. These methods have produced as of 1996 microprocessors capable of over 100
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`million operations per second that cost less than $1,000 and 64 Mbit DRAM circuits that access
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`data in less than 50 ns and cost less than $50. The physical size of such circuits is less than 2
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`cm2. Such manufacturing methods support to a large degree the economic standard of living in
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`the major industrialized countries and will most certainly continue to have significant
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`consequences in the daily lives of people all over the world.
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`Circuit manufacturing methods take two primary forms: process integration and assembly
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`integration. Historically the line between these two manufacturing disciplines has been clear, but
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`recently with the rise in the use of MCMs (Multi-Chip Modules) and flip-chip die attach, this
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`clear separation may soon disappear. (The predominate use of the term Integrated Circuit (IC)
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`herein is in reference to an Integrated Circuit in singulated die form as sawed from a circuit
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`substrate such as s semiconductor wafer versus, for example, an Integrated Circuit in packaged
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`form.) The majority of ICs when in initial die form are presently individually packaged,
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`however, there is an increasing use of MCMs. Die in an MCM are normally attached to a circuit
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 1 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 1 of 36
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`substrate in a planar fashion with conventional IC die I/O interconnect bonding methods such as
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`wire bonding, DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).
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`Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM, Ferroelectric,
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`GMR (Giant MagnetoResistance), etc. have the common architectural or structural characteristic
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`of being monolithic with the control circuitry integrated on the same die with the memory array
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`circuitry. This established (standard or conventional) architecture or circuit layout structure
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`creates a design trade-off constraint between control circuitry and memory array circuitry for
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`large memory circuits. Reductions in the fabrication geometries of memory cell circuitry has
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`resulted in denser and denser memory ICs, however, these higher memory densities have
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`resulted in more sophisticated control circuitry at the expense of increased area of the IC.
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`Increased IC area means at least higher fabrication costs per IC (fewer ICs per wafer) and lower
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`IC yields (fewer working ICs per wafer), and in the worst case, an IC design that cannot be
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`manufactured due to its non-competitive cost or unreliable operation.
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`As memory density increases and the individual memory cell size decreases more control
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`circuitry is required. The control circuitry of a memory IC as a percentage of IC area in some
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`cases such as DRAMs approaches or exceeds 40%. One portion of the control circuitry is the
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`sense amp which senses the state, potential or charge of a memory cell in the memory array
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`circuitry during a read operation. The sense amp circuitry is a significant portion of the control
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`circuitry and it is a constant challenge to the IC memory designer to improve sense amp
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`sensitivity in order to sense ever smaller memory cells while preventing the area used by the
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`sense amp from becoming too large.
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 2 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 2 of 36
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`If this design constraint or trade-off between control and memory circuits did not exist, the
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`control circuitry could be made to perform numerous additional functions, such as sensing
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`multiple storage states per memory cell, faster memory access through larger more sensitive
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`sense amps, caching, refresh, address translation, etc. But this trade-off is the physical and
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`economic reality for memory ICs as they are presently made by all manufacturers.
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`The capacity of DRAM circuits increases by a factor of four from one generation to the next; e. g.
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`l bit, 4 bit, l6 Mbit and 64 Mbit DRAMs. This four times increase in circuit memory capacity
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`per generation has resulted in larger and larger DRAM circuit areas. Upon introduction of a new
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`DRAM generation the circuit yields are too low and, therefore, not cost effective for high
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`volume manufacture. It is normally several years between the date prototype samples of a new
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`DRAM generation are shown and the date such circuits are in volume production.
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`Assembling die in a stacked or three dimensional (3D) manner is disclosed in U.S. Pat. No.
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`5,354,695 of the present inventor, incorporated herein by reference. Furthermore, assembling die
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`in a 3D manner has been attempted with regard to memory. Texas Instruments of Dallas Tex.,
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`Irvine Sensors of Costa Mesa Calif and Cubic Memory Corporation of Scotts Valley Calif have
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`all attempted to produce stacked or 3D DRAM products. In all three cases, conventional DRAM
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`circuits in die form were stacked and the interconnect between each DRAM in the stack was
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`formed along the outside surface of the circuit stack. These products have been available for the
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`past several years and have proved to be too expensive for commercial applications, but have
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`found some use in space and military applications due to their small physical size or footprint.
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 3 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 3 of 36
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`The DRAM circuit type is referred to and often used as an example in this specification,
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`however, this invention is clearly not limited to the DRAM type of circuit. Undoubtedly memory
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`cell types such as EEPROMs (Electrically Erasable Programmable Read Only Memories), flash
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`EPROM, Ferroelectric, GMR Giant Magneto Resistance or combinations (intra or inter) of such
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`memory cells can also be used with the present Three Dimensional Structure (3DS) methods to
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`form 3DS memory devices.
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`The present invention furthers, among others, the following objectives:
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`1. Several-fold lower fabrication cost per megabyte of memory than circuits conventionally
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`made solely with monolithic circuit integration methods.
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`2. Several-fold higher performance than conventionally made memory circuits.
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`3. Many-fold higher memory density per IC than conventionally made memory circuits.
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`4. Greater designer control of circuit area size, and therefore, cost.
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`5. Circuit dynamic and static self-test of memory cells by an internal controller.
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`6. Dynamic error recovery and reconfiguration.
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`7. Multi-level storage per memory cell.
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`8. Virtual address translation, address windowing, various address functions such as indirect
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`addressing or content addressing, analog circuit functions and various graphics acceleration and
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`microprocessor functions.
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`SUMMARY OF THE INVENTION
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`The present 3DS memory technology is a stacked or 3D circuit assembly technology. Features
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`include:
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 4 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 4 of 36
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`1. Physical separation of the memory circuits and the control logic circuit onto different layers;
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`2. The use of one control logic circuit for several memory circuits;
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`3. Thinning of the memory circuit to less than about 50 microns in thickness forming a
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`substantially flexible substrate with planar processed bond surfaces and bonding the circuit to the
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`circuit stack while still in wafer substrate form; and
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`4. The use of fine-grain high density inter layer vertical bus connections.
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`The 3DS memory manufacturing method enables several performance and physical size
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`efficiencies, and is implemented with established semiconductor processing techniques. Using
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`the DRAM circuit as an example, a 64 Mbit DRAM made with a 0.25 microns process could
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`have a die size of 84 mmz, a memory area to die size ratio of 40% and a access time of about 50
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`ns for 8 Mbytes of storage; a 3DS DRAM IC made with the same 0.25 microns process would
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`have a die size of l8.6 mmz, use l7 DRAM array circuit layers, a memory area to die size ratio
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`of 94.4% and an expected access time of less than 10 ns for 64 Mbytes of storage.
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`The 3DS DRAM IC manufacturing method represents a scalable, many-fold reduction in the cost
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`per megabyte versus that of conventional DRAM IC manufacturing methods. In other words,
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`the 3DS memory manufacturing method represents, at the infrastructure level, a fundamental
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`cost savings that is independent of the process fabrication technology used.
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`BRIEF DESCRIPTION OF THE DRAWING
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`The present invention may be further understood from the following description in conjunction
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`with the appended drawing. In the drawing:
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 5 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 5 of 36
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`FIG. la is a pictorial View of a 3DS DRAM IC manufactured with Method A or Method B and
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`demonstrating the same physical appearance of I/O bond pads as a conventional IC die;
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`FIG. lb is a cross-sectional view of a 3DS memory IC showing the metal bonding interconnect
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`between several thinned circuit layers;
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`FIG. 1c is a pictorial view of a 3DS DRAM IC stack bonded and interconnected face-down onto
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`a larger conventional IC or another 3DS IC;
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`FIG. 2a is a diagram showing the physical layout of a 3DS DRAM array circuit block with one
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`data-line set of bus lines, i.e. one port;
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`FIG. 2b is a diagram showing the physical layout of a 3DS DRAM array circuit block with two
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`sets of data-line bus lines, i.e. two ports;
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`FIG. 2c is a diagram showing the physical layout of a portion of an exemplary memory
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`controller circuit;
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`FIG. 3 is a diagram showing the physical layout of a 3DS DRAM array circuit showing
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`partitions for sixty-four (64) 3DS DRAM array blocks;
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`FIG. 4 is a cross-sectional view of a generic 3DS vertical interconnection or feed-through in a
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 6 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
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`FIG. 5 is a diagram showing the layout of a 3DS memory multiplexer for down-selecting gate-
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`line read or write selection.
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`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
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`Referring to FIG. 1a and FIG. 1b, the 3DS (Three Dimensional Structure) memory device 100 is
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`a stack of integrated circuit layers with fine-grain vertical interconnect between all circuit layers.
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`The term fine-grain inter-layer vertical interconnect is used to mean electrical conductors that
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`pass through a circuit layer with or without an intervening device element and have a pitch of
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`nominally less than 100 microns and more typically less than 10 microns, but not limited to a
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`pitch of less than 2 microns, as best seen in FIG. 2a and FIG. 2b. The fine-grain inter-layer
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`vertical interconnect also functions to bond together the various circuit layers. As shown in FIG.
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`1b, although the bond and interconnect layers 105a, 105b, etc., are preferably metal, other
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`material may also be used as described more fully hereinafter.
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`The pattern 107a, 107b, etc. in the bond and interconnect layers 105a, 105b, etc. defines the
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`vertical interconnect contacts between the integrated circuit layers and serves to electrically
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`isolate these contacts from each other and the remaining bond material; this pattern takes the
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`form of either voids or dielectric filled spaces in the bond layers.
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`The 3DS memory stack is typically organized as a controller circuit 101 and some number of
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`memory array circuit layers 103, typically between nine (9) and thirty-two (32), but there is no
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`particular limit to the number of layers. The controller circuit is of nominal circuit thickness
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 7 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 7 of 36
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`(typically 0.5 mm or greater), but each memory array circuit layer is a thinned and substantially
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`flexible circuit with net low stress, less than 50 microns and typically less than 10 microns in
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`thickness. Conventional I/O bond pads are formed on a final memory array circuit layer for use
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`with conventional packaging methods. Other metal patterns may be used such as insertion
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`interconnection (disclosed in U.S. Pat. Nos. 5,323,035 and 5,453,404 of the present inventor),
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`DCA (Direct Chip Attach) or FCA (Flip-Chip Attach) methods.
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`Further, the fine grain inter-layer vertical interconnect can be used for direct singulated die
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`bonding between a 3DS memory die and a conventional die (wherein the conventional die could
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`be the controller circuit as shown in FIG. lc) or a 3DS memory die and another 3DS memory
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`die; it should be assumed that the areas (sizes) of the respective dice to be bonded together can
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`vary and need not be the same. Referring more particularly to FIG. lc, a 3DS DRAM IC stack
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`100 is bonded and interconnected face-down onto a larger conventional IC or another 3DS IC
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`107. Optionally the 3DS stack 100 can be composed of only DRAM array circuits with the
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`DRAM controller circuitry as part of the larger die. If the DRAM controller circuitry is part of
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`the larger die, then fine-grain vertical bus interconnect would be required (at the face 109 of
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`the 3DS DRAM IC stack 100) to connect the 3DS DRAM array circuit to the DRAM controller,
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`otherwise larger grain conventional interconnection could be incorporated (patterned) into the
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`planarized bond layer.
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`As shown in FIG. 3, each memory array circuit layer includes a memory array circuit 300
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`composed of memory array blocks 301 (nominally less than 5 mm2 in area) and each block is
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`composed of memory cells (in much the same manner as the cell array of a DRAM or EEPROM
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 8 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 8 of 36
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`circuit), busing electrodes, and--at the option of the designer--enabling gates for selection of
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`specific rows or columns of the memory array. The controller circuit is composed of sense amps,
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`address, control and drive logic that would normally be found at the periphery of a typical
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`memory circuit of monolithic design such as in a conventional DRAM.
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`Fine-grain busing vertically connects the controller independently to each memory array layer
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`such that the controller can provide drive (power) or enable signals to any one layer without
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`affecting the state of any of the other layers. This allows the controller to test, read or write
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`independently each of the memory circuit layers.
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`FIG. 2a and FIG. 2b show examples of layouts of possible blocks of a memory array such as the
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`block 301 of FIG. 3. Although only a portion of the block is shown, in the illustrated
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`embodiment, the blocks exhibit bilateral symmetry such that the layout of the complete block
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`may be ascertained from the illustrated portion. Abbreviations "T", "L", and "TL" are used
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`following various reference numerals to indicate "Top", "Left" and "Top-Left," respectively,
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`implying corresponding elements not shown in the figure. Referring to FIG. 2a, a core portion
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`200 of the block is composed of a "sea" of memory cells. Logically, the aggregation of memory
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`cells may be subdivided into "macrocells" 201 each containing some number of memory cells,
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`e.g. an 8 x 8 array of 64 memory cells. At the periphery of the core is formed fine-grain vertical
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`interconnect comprising inter-layer bond and bus contact metallizations 400, described in greater
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`detail hereinafter with reference to FIG. 4. The fine-grain vertical interconnect includes I/O
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`power and ground bus lines 203TL, memory circuit layer selects 205T, memory macro cell
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`column selects 207T, data lines 209L, and gate-line multiplexer ("mux") selects 209TL. Gate-
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 9 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 9 of 36
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`line multiplexers 211T are, in the illustrated embodiment, 4:1 multiplexers used to select one of
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`four columns within an eight-wide memory macro cell column. Corresponding bottom-side 4:1
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`multiplexers combine with the topside multiplexers 211T to form equivalent 8:1 multiplexers for
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`selecting a single gate-line from an eight-gate-line-wide memory macro cell column.
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`One implementation of a 4:1 gate-line bus muliplexer 500 is shown in FIG. 5. Gate-line enables
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`209TL' (formed in a Metal-1 layer, for example) control transistors 501a through 501d,
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`respectively. Coupled to the transistors are respective gate lines 503a through 503d. Also partly
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`visible are gate-lines 505a through 505d which are coupled to a corresponding 4:1 multiplexer
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`(not shown). When one of the gate-line enables is active, the corresponding gate-line is coupled
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`to an output line 507 of the multiplexer (formed in a Metal-2 layer, for example). The output line
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`is connected to one or more vertical bus connects through a line 509 (formed in a Metal-3 layer
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`and corresponding to metal contact 400 of vertical bus interconnect, for example) and tungsten
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`plugs 511 and 513. The tungsten plug 513 joins the line 509 to a vertical interconnect (not
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`shown).
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`Referring again to FIG. 2a, in the case of a memory circuit layer, the layer may also include
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`output line enables (gates) from controller layer enable signals 205T, for which I/O enables
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`(gates) 213 may be provided.
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`Note that at the memory layer level, each memory block 301 is electrically isolated from every
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`other memory block 301. Accordingly, the yield probability for each memory block is
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`independent.
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`10
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 10 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 10 of 36
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`Additional read/write ports can be added as can additional gate-line vertical interconnections;
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`additional vertical interconnection can be used in a redundant manner to improve vertical
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`interconnect yield. The 3DS memory circuit can be designed to have one or more data read and
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`write bus port interconnections. Referring to FIG. 2b, a memory block 301' is shown as having a
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`port P0, (209L) and a further port Pl (209L'). The only limitation on the number of vertical
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`interconnections is the overhead such vertical interconnections impose on the cost of the circuit.
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`The fine-grain vertical interconnect method allows thousands of interconnects per block at an
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`increase in die area of only a few percent.
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`As an example, the overhead of the vertical interconnect shown in FIG. 2b for a DRAM memory
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`block of 4 bits with two read/write ports and implemented in 0.35 microns or 0.15 microns
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`design rules consists of approximately 5,000 connections and is less than 6% of the total area of
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`the memory array block. Therefore, the vertical interconnect overhead for each memory array
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`circuit layer in the 3DS DRAM circuit is less than 6%. This is significantly less than that
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`presently experienced in monolithic DRAM circuit designs where the percentage of non-memory
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`cell area can exceed 40%. In a completed 3DS DRAM circuit the percentage of non-memory cell
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`area is typically less than l0% of the total area of all circuits in the stacked structure.
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`The 3DS memory device decouples control functions that normally would be found adjacent the
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`memory cells of monolithic memory circuits and segregates them to the controller circuit. The
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`control functions, rather than occurring on each memory array layer as in conventional memory
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`ICs, occur only once in the controller circuit. This creates an economy by which several memory
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`11
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 11 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 11 of 36
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`array layers share the same controller logic, and therefore, lowers the net cost per memory cell
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`by as much as a factor of two versus conventional memory design.
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`The segregation of the control functions to a separate controller circuit allows more area for such
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`functions (i.e., an area equal to the area one or several of the memory array blocks). This
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`physical segregation by function also allows fabrication process segregation of the two very
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`different fabrication technologies used for the control logic and the memory array, again
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`realizing additional fabrication cost savings versus the more complicated combined
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`logic/memory fabrication process used for conventional memory. The memory array can also be
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`fabricated in a process technology without consideration of the process requirements of control
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`logic functions. This results in the ability to design higher performance controller functions at
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`lower cost than is the case with present memory circuits. Furthermore, the memory array circuit
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`can also be fabricated with fewer process steps and nominally reduce memory circuit fabrication
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`costs by 30% to 40% (e.g., in the case of a DRAM array, the process technology can be limited
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`to NMOS or PMOS transistors versus CMOS).
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`Hence, although bonding of sufficiently planar surfaces of a memory controller substrate and a
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`memory array substrate using thermal diffusion metal bonding is preferred, in the broader
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`aspects of the present invention, the invention contemplates bonding of separate memory
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`controller and memory array substrates by any of various conventional surface bonding methods,
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`such as anisotropically conductive epoxy adhesive, to form interconnects between the two to
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`provide random access data storage.
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 12 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 12 of 36
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`Referring to FIG. 2c, the layout of a portion of an exemplary memory controller circuit is shown.
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`The inter-layer bond and bus contact metallization has the same pattern as previously described
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`in relation to FIG. 2a. Instead of a sea of memory cells, however, there is provided memory
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`controller circuitry including, for example, sense amps and data line buffers 215. Because of the
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`increased availability of die area, multi-level logic may be provided in conjunction with the
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`sense amps and data line buffers 215. Also shown are address decode, gate-line and DRAM layer
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`select logic 217, refresh and self-test logic 219, ECC logic 221, windowing logic 223, etc. Note
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`that self-test logic, ECC logic, and windowing logic are provided in addition to functions
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`normally found within a DRAM memory controller circuit. Depending on die size or the number
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`of controller circuit layers used, any of numerous other functions may also be provided
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`including, for example, virtual memory management, address functions such as indirect
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`addressing or content addressing, data compression, data decompression, audio encoding, audio
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`decoding, video encoding, video decoding, voice recognition, handwriting recognition, power
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`management, database processing, graphics acceleration functions, microprocessor functions
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`(including adding a microprocessor substrate), etc.
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`The size of the 3DS memory circuit die is not dependent on the present constraint of containing
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`the necessary number of memory cells and control function logic on one monolithic layer. This
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`allows the circuit designer to reduce the 3DS circuit die size or choose a die size that is more
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`optimal for the yield of the circuit. 3DSmemory circuit die size is primarily a function of the size
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`and number of memory array blocks and the number of memory array layers used to fabricate the
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`final 3DSmemory circuit. (The yield of a nineteen (19) layer, 0.25 microns process 3DS DRAM
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`memory circuit may be shown to be greater than 90% as described below.) This advantage of
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`13
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`SAMSUNG ET AL. EXHIBIT 1020
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`Page 13 of 36
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`SAMSUNG ET AL. EXHIBIT 1020
`Page 13 of 36
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`selecting the 3DS circuit die size enables an earlier first production use of a more advanced
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`process technology than would normally be possible for conventional monolithic circuit designs.
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`This, of course, implies additional cost reductions and greater performance over the conventional
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`memory circuits.
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`3DS Memory Device Fabrication Methods
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`There are two principal fabrication methods for 3DS memory circuits. The two 3DS memory
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`fabrication methods, however, have a common objective which is the thermal diffusion metal
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`bonding (also referred to as thermal compression bonding) of a number of circuit substrates onto
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`a rigid supporting or common substrate which itself may optionally also be a circuit component
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`layer.
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`The supporting or common substrate can be a standard semiconductor wafer, a quartz wafer or a
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`substrate of any material composition that is compatible with the processing steps of
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`the 3DS circuit, the operation of the circuit and the processing equipment used. The size and
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`shape of the supporting substrate is a choice that best optimizes available manufacturing
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`equipment and methods. Circuit substrates are bonded to the supporting substrate and then
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`thinned through various methods. Circuit substrates may be formed on standard single crystal
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`semiconductor substrates or as polysilicon circuits formed on an appropriate substrate such as
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`silicon or quartz. Polysilicon transistor circuits have the important cost saving option of
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