llllllllllllllllllllllllllllllllllllllllllllllllllllIllllllllllllllllllllll
`USO0S202754A
`.
`5,202,754
`[11] Patent Number:
`[19]
`United States Patent
`Bertin et al.
`[45] Date of Patent:
`Apr. 13, 1993
`
`
`5/1990 European Pet 05- -
`0374971
`3/1983 Fed. Rep. of Germany .
`3233195
`3/1983 Japan .
`58-43554
`5/1985 Japan .
`60-79763
`I/1986 Japan .
`61-22660
`1326758 8/1973 United Kingdom .
`
`OTHER PUBLICATIONS
`Lasky, J. B., "Wafer Bonding for Silicon-on-Insulator
`Technologies,” Appl. Phys. Lett., vol. 48, No. 1, pp.
`78-80, Jan., 1986.
`Lineback, J. Robert, “3D 1C Packaging Moves Closer
`to Commercial Use," Electronic World News, pp. 15 &
`18, May 21, 1990.
`
`Primary Examirier-—Eugcne R. Lakoche
`"*“"""’“ E‘‘’”’’’'‘’‘‘.‘’''’‘ Q N.3“Y°“
`""°"""”’ "3"" °’ ”‘""“H°“‘“ “‘ R°“"“"°’3
`[57]
`ABSTRACT
`A fabrication method and resultant ‘mcedimmsionfl
`inultichip package having a densely stacked array of
`semiconductor chips interconnected at least partially by
`means of a plurality of metallized trenches are dis-
`closed. The fabrication method includes providing on
`integrated circuit chip having high aspect ratio metal-
`lized trenches therein extending from a first surface to 1:
`-
`-
`second surface thereof. An etch stop layer is provided
`pl'OX.lIIlRtC l-I116 t¢l'Il'lln8.t.lOfl P0511110!) Of thC IDCt&ul1€d
`trenches with the semiconductor =I1bStrate- Next the
`integrated circuit device is affixed to a carrier such that
`the surface of the supporting substrate is exposed and
`substrate is thinned from the integrated circuit device
`until exposing at least some of the plurality of metallized
`trenches thew E‘°°"“."*‘ com cam t!ms*>.= made to
`the active layer of the integrated circuit chip via the
`exposed metallizcd trcncheS- Specific details of the fab-
`rication method and the resultant multichip package are
`f rth.
`3“ °
`
`[54] THREE-DIMENSIONAL MULTICHIP
`PACKAGES AND METHODS OF
`FABRICATION
`
`[75]
`
`Inventors: Claude L. Bertin; Paul A. Farrar, Sr.,
`both of South Burlington; Howard L.
`Kalter, Colchester; Gordon A. Kelley,
`Jr., Essex Junction; Willem B. van
`der Hoeveu, Jericho; Francis R.
`White, Essex, all of Vt.
`
`[73] Assignee:
`
`International Business Machines
`Corporation’ Amonk, NY.
`
`[21] App]. No.2 760,041
`
`Sep. 13, 1991
`[22] Filed:
`51
`In c1.s ......................... HOIL 29
`a-1344c 1 22
`iszi u.§.c1. ............................... 25'/36,84; 257/7/77;
`
`251/723; 257/725
`[58] Field of Search ....................... 357/75, 30, 74, 11,
`357/72
`
`References Cited
`U3’ PATENT D_0CUMENTs
`3,564,358
`2/1971 Hahnlein ............................. 317/235
`3'679’941
`7/1972 L‘°°mb° °‘ *1‘
`'
`357/75
`4,525,921
`7/1985 Carson et al.
`29/577 C
`
`4,612,083
`9/1986 Yuummo at ‘L
`‘ 156/633
`£546,627 3/1987 Abernathey ct
`29/571
`4,717,443
`1/1933 Cox et .1.
`.............
`.. 156/643
`4,807,021
`2/1989 Okuinura ......
`357/75
`4,829,018 5/I989 Wahlsti-om
`437/51
`4.937.659
`6/1990 Chhll. -in ------
`357/75
`$939-553
`7/1990 K“° °‘ 31'
`357/75
`1:321:23? £1333 %f§:’..;;;;;':::........
`.::: 233%
`4,957,393 lo/1990 Yokoyma CH1.
`365/I35
`4,989,063
`1/1991 Kolesar. Jr. .......
`1.. 357/75
`s,o91,7e2 2/1992 Watanabe .............................. 357/75
`FOREIGN PATENT DOCUMENTS
`
`
`
`‘
`
`[56]
`
`0314437
`
`3/1989 European Fat. 011'.
`
`.
`
`6 Claims, 8 Drawing Sheets
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`58
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`
`
`
`
`73
`
`68
`
`
`
`
`70
`
`
`
`SAMSUNG ET AL. EXHIBIT 1004
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 2 of 3
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`SAMSUNG ET AL. EXHIBIT 1004
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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 3 of 3
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
`Page 4 of 14
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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 4 of 8
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`5,202,754
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`SAMSUNG ET AL. EXHIBI
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`54
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`68
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`70
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`SAMSUNG ET AL. EXHIBIT 1004
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`U.S. Patent
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`Apr. 13, 1993
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`Sheet 5 of 8
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`SAMSUNG ET AL. EXHIBIT 1004
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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 6 of 8
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`SAMSUNG ET AL. EXHIBIT 1004
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`

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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 7 of 3
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`U.S. Patent
`
`Apr. 13, 1993
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`Sheet 8 of 8
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`5,202,754
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`SAMSUNG ET AL. EXHIBIT 1004
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`

`
`1
`
`5,202,754
`
`THREE-DIMENSIONAL MULTICHIP PACKAGES
`AND METHODS OF FABRICATION
`
`BACKGROUND OF THE INVENTION
`1. Technical Field
`
`The present invention relates in general to high den-
`sity electronic packaging which permits optimization of
`the number of circuit elements to be included in a given
`volume. More particular, the present invention relates
`to a method for fabricating a three-dimensional multi-
`chip package having a densely stacked array of semi-
`conductor chips interconnected at least partially by
`means of a plurality of metallized trenches in the semi-
`conductor chips.
`2. Description of the Prior Art
`Since the development of integrated circuit technol-
`ogy, computers and computer storage devices have
`been made from wafers of semiconductor material com-
`prising a plurality of integrated circuits. After a wafer is
`made, the circuits are typically separated from each
`other by dicing the wafer into small chips. Thereafter,
`the chips are bonded to carriers of various types, inter-
`connected by wires and packaged. Along with being
`time consuming, costly and unreliable, the process of
`physically attaching wires to interconnect chips often
`produces undesirable signal delays, especially as the
`frequency of device operation increases.
`As an improvement over this traditional technology,
`stack or packages of multiple semiconductor chips have
`become popular, e.g., reference U.S. Pat. No. 4,525,921,
`entitled “High-Density Electronic Processing Package
`- Structure and Fabrication." FIG. 1 depicts a typical
`semiconductor chip stack, generally denoted 10, con-
`sisting of multiple integrated circuit chips 12 which are
`adhesively secured together. A metallization pattern 14
`is provided on one or more sides of stack 10 for chip
`interconnections and for electrical connection to cir-
`cuitry external to the stack. Metallization pattern 14
`includes both individual contacts 16 and bussed
`contacts 18. Stack 10, with metallization 14 thereon, is
`positioned on the upper surface 2] of a substrate 20
`which has its own metallization pattern 22 thereon.
`Although superior to the more conventional technique
`of individually placing chips on a board, substrate or
`multichip carrier, both in terms of reliability and circuit
`performance, this multichip stack approach is still sus-
`ceptible to improvement in terms of density and reduc-
`Iion in the length of chip wiring. Obviously, any im-
`provements in such package characteristics will pro-
`duce a lower cost, lower power higher density, reliabil-
`ity and thereby providing better performing device.
`SUMMARY OF THE INVENTION
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`Briefly described, the present invention comprises in
`one aspect a multichip packaging method which in-
`cludes the initial step of providing an integrated circuit
`device having a first, upper surface and a second, lower
`surface in substantially parallel opposing relation. The
`device, which may comprise a semiconductor chip or
`wafer, has an active layer adjacent to the first surface
`and a substrate adjacent to the second surface. The
`device further
`includes
`a plurality of metallized
`trenches therein which extend from the first surface
`through the active layer and partially into the substrate.
`At least some of the plurality of metallized trenches are
`in electrical contact with the active layer of the inte-
`grated circuit device. The packaging method further
`
`55
`
`60
`
`65
`
`2
`includes affixing this integrated circuit device to a car-
`rier such that the second surface thereof is exposed,
`allowing the thinning of the substrate of the integrated
`circuit device until exposing at least some of the plural-
`ity of metallized trenches therein. Electrical contact can
`thus be made to the active layer of the integrated circuit
`device via the exposed metallized trenches. Additional
`integrated circuit devices are preferably added to the
`stack in a similar manner. As each layer of circuit de-
`vices is added electrical contact to at least some of the
`exposed metallized trenches of the previous layer is
`made. In another aspect of the present invention, a
`novel multichip package system, resulting from applica-
`tion of the above processing method, is provided. Spe-
`cific details of the method and the resultant package are
`described in detail and claimed herein.
`
`The present invention advantageously produces a
`multichip package having high integrated circuit den-
`sity. Wiring solutions are presented for very dense
`packaging I/O connects, and three-dimensional vertical
`and horizontal wiring is discussed. Further, techniques
`to limit the power dissipation of particular functions in
`a dense multichip package are provided. In accordance
`with the processing approach of the present invention,
`a multiple chip package can be created in the same
`space previously required for a single integrated circuit
`chip. Further, fabrication of the individual wafers/chips
`to be assembled into the multichip package remains
`consistent with high volume wafer manufacturing.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The subject matter which is regarded as the present
`invention is particularly pointed out and distinctly
`claimed in the concluding portion of the specification.
`The invention, however, both as to organization and
`method of practice, together with further objects and
`advantages thereof, may best be understood by refer-
`ence to the following detailed description taken in con-
`junction with the accompanying drawings in which:
`FIG. 1 is an exploded perspective view of a basic
`prior art multichip package;
`FIGS. 2a & 2b illustrate the difference in packaging
`density between a multichip package fabricated in ac-
`cordance with existing techniques (FIG. 2a) and a mul-
`tichip package fabricated pursuant to the present inven-
`tion (FIG. 2b);
`FIGS. 3a—3t' are partial cross-sectional elevational
`depictions or structures obtained at various processing
`steps in accordance with one multichip package fabrica-
`tion embodiment pursuant to the present invention;
`FIGS. 4a-dd depict various electrical lead wiring
`options from or through an integrated circuit device
`pursuant to the present invention;
`FIGS. 5a & 5b illustrate the different requirements in
`access surface wiring for DRAM and SRAM configu-
`rations for a multichip package constructed in accor-
`dance with existing techniques (FIG. 5a) and for a mul-
`tichip package constructed in accordance with the pres-
`ent invention (FIG. Sb); and
`FIG. 6 graphically depicts an example of the different
`integrated circuit packaging densities obtainable using
`Small Outline J Lead (SOJ), Cube (FIG. 1) and that
`produced in the present
`invention packaging tech-
`niques.
`
`SAMSUNG ET AL. EXHIBIT 1004
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`

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`3
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`5,202,754
`
`I0
`
`15
`
`25
`
`Broadly stated, the present invention comprises a
`method for improving the circuit density in a multichip
`package, such as stack 10 depicted in FIG. 1. FIG. 2a
`depicts a conventional multichip stack 30 having two
`chips, chip I and chip 2. Each chip has an active layer
`32 which extends within the chip a distance "x”, and an
`overall thickness “y" from an upper surface 31 to a
`lower surface 33 thereof. Chip thickness “y" is at least
`an order of magnitude greater than active layer thick-
`ness “x”. For example, typically thickness “x" is within
`the range of 5-20 micrometers, while thickness "y” is
`more conventionally in the range of 750-850 microme-
`ters (30 mils). However, recently the practice is to re-
`duce thickness “y” by mechanical thinning of the sub-
`strate in each chip to approximately 375-425 microme-
`ters (l5 mils) prior to assembly of the package. Notwith-
`standing this mechanical reduction. the volume of the
`useful active silicon, e.g., active layers 32, remains much
`less than that of the total silicon. This is because the
`silicon substrate still continues to be used for mechani-
`cal support of layer 32 of the chip during processing.
`In comparison with the package of FIG. 2a, the semi-
`conductor chips in a package processed pursuant to the
`present invention have only a thin layer of substrate for
`support of the active layer, which is illustrated in FIG.
`2b wherein two thin semiconductor chips, chip 1 and
`chip 2, are shown. These chips are stacked in a package
`40. The active layer 42 of each chip in package 40 has a
`thickness “x”' which, as shown, is a significant portion
`of the chip thickness “y"’. This is in contrast to the large
`size disparity between thickness “x” and thickness “y”
`for the conventional package of FIG. 2a. By way of 35
`example, thickness “x”’ may be in the 5-20 micrometers
`range, while the overall thickness “y"’ of each device
`may be only 20 micrometers or less. This means that
`when the chips are combined in a stack configuration a
`significantly denser electronic package is produced than
`is possible using previous stacking techniques for sepa-
`rate integrated circuit chips. In essence, processing in
`accordance with the present invention advantageously
`elirriinates most of the excess silicon substrate in a sili-
`con device after bonding of the device to a growing
`multichip package.
`One example of a package fabrication process pursu-
`ant to the present invention is described below with
`reference to FIGS. 3a-31'.
`Referring first to FIG. 3a, processing begins with a
`semiconductor device 50 (preferably comprising a wa-
`fer) having a substrate 52 and an active layer 54, which
`is typically positioned at least partially therein. (Layer
`54 may be totally or partially defused into substrate 52
`and/or partially or totally built up from substrate 52
`using conventional semiconductor processing tech-
`niques known to those skilled in the art.) Layer 54 is
`adjacent to a first. upper planar surface 56 or device 50.
`A second, lower planar surface 58 or device 50 is posi-
`tioned substantially parallel to first planar surface 56. A
`dielectric layer 60, for example, SiO2, is grown over
`active layer 54 of device 50. Although variable, sub-
`strate 52 thickness will
`typically be approximately
`750-800 micrometers (l5 mils) prior to creation of a
`multichip package. In comparison,
`the thickness of 65
`active layer 54 may be in the range of 4-6 micrometers,
`while the thickness of insulating layer 60 will vary, e.g.,
`with the number or metallization levels already built
`
`45
`
`55
`
`4
`upon active layer 54. Layer 54 may comprise any con-
`ventional bipolar, CMOS, NMOS, PMOS, etc., cir-
`cuitry.
`Pursuant to the invention, a standard wafer is modi-
`fied during manufacture by placing a burred etch stop
`53 below the surface of the substrate. The etch stop can
`comprise an N+ layer 53 in a P substrate 52 or a P+
`layer 53 in an N substrate 52, both of which can be
`fabricated by any one of several means known to those
`skilled in the art.
`Shown in exaggerated size in FIG. 3b are thin. deep
`trenches 62 defined in integrated circuit device 50.
`Trenches 62 are configured to extend slightly through
`etch stop layer 53 into substrate 52. In a preferred em-
`bodiment, deep trenches 62 will each have a high aspect
`ratio of approximately 20:1, which means, for example,
`that thin trenches 62 will preferably have a width of l
`micrometer for a 20 micrometer deep trench. (As de-
`scribed below, the high aspect ratio trenches 62 will
`ultimately advantageously serve to define very small
`interconnect dimensions.) Trenches 62 can be fabri-
`cated pursuant to the techniques described in U.S. Pat.
`No. 4,7l7,448, entitled: “Reactive Ion Etch Chemistry
`for Providing Deep Vertical Trenches in Semiconduc-
`tor Substrates,” which is hereby incorporated herein by
`reference. Deep trenches 62 are positioned in the inte-
`grated circuit device 50 where electrical through con-
`nections between devices are desired once the multichip
`package is assembled.
`The trench sidewalls are oxidized to provide isolation
`from the bulk silicon (such that the trenches can be used
`for wiring without shorting the devices), with doped
`polysilicon or other conductor 64 (see FIG. 3c). The
`device, including wiring levels, can next be completed
`using standard processing techniques, with the layout of
`the devices (circuits) being modified so that the area 61
`(see FIG. 3d) where polysilicon filled trenches are posi-
`tioned remains clear of circuitry and wiring embedded
`within completed oxidation/connecting metallization
`layer 63.
`Referring to FIG. 3e, deep trenches 62 are next
`reetched to remove polysilicon plugs 64, using tech-
`niques known in the art. The trenches 62 are then filled
`with an appropriate metal 66, e.g., tungsten Au, Cu,
`aluminum or other suitable metal, by a chemical vapor
`deposition CVD process, plating or other appropriate
`means. Metallized trenches 66 will extend at
`least
`slightly through etch stop layer 53. Contact pads 68 of
`gold, copper or other appropriate metal are then depos-
`ited so that they will interconnect the appropriate wir-
`ing (not shown) on the chip to the vertically disposed
`wiring 66 in trenches 62. The integrated circuit chips
`are then tested, the wafers diced and the good chips are
`selected. Alternatively, the wafers may be left undiced
`depending upon the processing path chosen. If suffi-
`cient redundancy is built into the structure so as to
`produce essentially a 100% yield or good chips, then
`the wafers will remain undiced. Whether the wafers are
`to be diced or remain undiced, however, they are pref-
`erably first mechanically thinned, for example, to at
`least 375-400 micrometers (15 mils) i.e., if not already
`accomplished.
`Assuming that the chips are separated, the first inte-
`grated circuit chip 50 to be incorporated into the multi-
`chip package is flipped over and bonded to a suitable
`carrier 70 such that the protective surface 63 of chip 50
`is disposed adjacent the upper surface 71 of carrier 70
`(see FIG. 3}). Chip 50 is adhesively bonded to carrier 70
`
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`5
`by use of a suitable adhesive material 73, such as a poly-
`imide. (As an alternative to carrier 70, chip 50 could be
`bonded to a base integrated circuit chip (not shown)
`which would have contacts mirroring the positions of
`pads 68 of device 50 and a thickness sufficient to sup-
`port the package, at least during assembly joining of
`integrated circuit chip 50 to such a base chip could be
`by Au to An thermal compression bonding or other
`suitable means.)
`Next, the exposed second surface 58 of chip 50 (FIG.
`3/) is etched in a suitable selective chemical etch such as
`ethylenediamine, pyrocatechol, water solution, or 20021
`nitric acid/I-IF solution. See co-pending U.S. patent
`application entitled “Three Dimensional Semiconduc-
`tor Structure Formed from Planar Layers,” Ser. No.
`656,902, filed Feb. 15, I99], continuation of Ser. No.
`427,679, filed Oct. 26, 1989. The chemical etch is selec-
`tive so that etching ceases when etch stop layer 53 is
`reached (FIG. 33). Further, the etchant is selected so as
`not to etch metal 66 deposited within deep trenches 62.
`The chemical etch removes only the silicon wafer down
`to etch stop 53 (see FIG. 3g). As shown in FIG. 3h, an
`appropriate photo-definable polyimide 80 or other
`bonding compound is then applied and etched to par-
`tially reveal the metallized trenches 66 in chip 50. Prior
`to complete curing of the polymer, Au is plated electro-
`lessly and selectively on the metallized trench connec-
`tions to form pads 82. If aluminum is used to metallize
`the trenches, a suitable diffusion barrier (not shown),
`such as Cr, is plated on the Al prior to Au plating. The
`stacking process is repeated by the respective addition
`of integrated circuit devices (see, e.g., FIG. 31‘) one on
`top of the other, each having its active layer positioned
`adjacent to the last thinned exposed surface of the stack
`with contact pads 68 contacting at least some of the
`exposed metallized trenches 66 therein. Bonding of each
`chip layer is such that the polymer and Au to Au bond-
`ing preferably take place simultaneously.
`Should full wafer stacking be used, the process is
`essentially the same. The wafers are subsequently diced
`into separate multichip packages at an appropriate point
`in the process, either when the package is complete or
`when the cumulative yield is such as to make further
`stacking uneconomical.
`It will be observed that a significant advantage is
`attained pursuant to the fabrication process set forth,
`i.e., the elimination of excess silicon substrate material
`from the separately constructed integrated circuit de-
`vices as the multichip package is assembled, without
`interfering with the active silicon layers thereon. The
`removed silicon is single crystal silicon and the fabrica-
`tion of individual integrated circuit devices remains
`consistent with high volume semiconductor wafer man-
`ufacturing. As described below, multichip packages
`constructed pursuant
`to this processing technique
`achieve the greatest possible silicon volumetric density
`for separately fabricated integrated circuit devices. The
`device thicknesses are adjusted to more closely reflect
`the active surface and depth actually used so that pack-
`age density is more closely linked to feature depth.
`FIGS. 4a-Id depict several examples of integrated
`circuit chip connection options for a multichip package
`constructed pursuant to the present invention. In FIG.
`4a, horizontal connecting leads 92 extend to a planar
`side surface 94 of chip 90 to provide electrical connec-
`tion between side surface 94 and selected pads 96 on the
`surface of chip 90. Once multiple chips are assembled in
`a stack, at least some of which may include horizontal
`
`5.
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`extending leads 92, a pattern of metallization can be
`deposited on the edge surface of the stack to define
`connects to individual electrical pads in the chip, and-
`/or multiple selected electrical pads located on one or
`more of the integrated circuit chips.
`By utilizing the metallized trench approach of the
`present invention, multiple layers of integrated circuit
`chips, such as chip 90, can be vertically interconnected
`via metallized trenches, e.g., trenches 98 in FIG. 46.
`Trenches 98, constructed as described above in connec-
`tion with FIGS. 3a—3i, are positioned to extend through
`the respective chip 90. Alternatively, a mixture of verti-
`cally and horizontally extending interconnecting leads
`can be used. In such a mixed interconnecting circuitry
`application. the horizontal leads 92 can extend to one or
`more edge surfaces 94 of the chip 90 (FIG. 4c), and/or
`only extend between selected pads in a single chip
`(FIG. Id). The scale of wirability between integrated
`circuit chips in the multichip package is believed to
`comprise a significant improvement over state of art
`package wiring. The dimensions of the vertical inter-
`connections between integrated circuit chips are at least
`an order of magnitude smaller than any prior “gross"
`vertical connection wiring technique.
`One factor to consider in devising a horizontal/verti-
`cal interconnection scheme is the amount of space that
`will be available on the edge surfaces of the completed
`multichip package. FIG. 5a partially depicts several
`semiconductor chips 100 arranged in a conventional
`multichip package. Each chip 100 has several electrical
`leads 102 extending therefrom to at least one side sur-
`face of the package. Traditionally, T-shaped electrical
`junctions are formed in the access plane (i.e., at least one
`planar side surface of the multichip package having the
`pattern of chip interconnecting metallization thereon
`(not shown)), to provide good electrical junctions with
`the leads brought out to that side surface from the re-
`spective integrated circuit chips l00. This is accom-
`plished by depositing conductor pads 104 of uniform
`size on top of the access plane so that each pad inter-
`sects with an end of an electrical lead 102 brought out
`from the respective integrated circuit chips 100.
`In many applications, planar side wiring is in the form
`of stripes (or buses) 105 extending perpendicular to the
`planes of the chips. Each stripe 105 crosses the junctions
`between a plurality of chips where it makes electrical
`contact with the T-shaped junctions on the chips. In
`many other applications, unique I/O junctions 106 are
`required for making individual contacts on separate
`integrated circuit chips 100. In the multichip DRAM,
`SRAM, EPROM. or other integrate circuits or combi-
`nation thereof package of FIG. 5a, sufficient space is
`available on the chips for readily providing these I/0
`contacts 106 within the access plane. For example, typi-
`cal spacing between adjacent T-junctions of the same
`integrated circuit chip is approximately 0.05 millimeters
`(2 mils), while T-junction spacing between adjacent
`chips is approximately 0.375 millimeters (15 mils).
`Examples of access plane sizing for both DRAM and
`SRAM multichip packages assembled pursuant to the
`present invention are depicted in FIG. 5b. As shown,
`the spacing between electrical leads 110 brought out
`from adjacent
`integrated circuit chips 112 in both
`DRAM and SRAM configurations is significantly re-
`duced from the spacing between these leads in FIG. 5a.
`For example, in a DRAM application, such spacing
`may be approximately 20 micrometers (0.02 millime-
`ters) and for a SRAM application, spacing may drop
`
`SAMSUNG ET AL. EXHIBIT 1004
`
`Page 12 of 14
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`SAMSUNG ET AL. EXHIBIT 1004
`Page 12 of 14
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`

`
`7
`down to 10 micrometers (0.01 millimeters). In order to
`form discrete I/O contact pads 114, therefore, it is nec-
`essary to spread out laterally the T-shaped electrical
`junctions to allow room for the unique 1/0 contacts.
`This in turn limits the number of stripes (or buses) 116
`which can extend perpendicular to the planes of the
`integrated circuit chips.
`The invention overcomes this problem by utilizing
`the metallized trenches for bussing. That is, in addition
`to forming simple chip-to-chip interconnections, the
`trenches can be arranged to provide bussing between
`non-adjacent chips. In effect, we have added an addi-
`tional wiring plane that reduces the constraints imposed
`by the thinness of the chips on chip edge wiring. In
`designing chips for the cube of the invention, circuit
`placement etc. must be optimized for through-chip
`wireability. However, the resulting decrease in circuit
`density is more that compensated by introducing an
`entirely new wiring plane. The invention will actually
`enhance performance, because now each circuit can be
`only 30 pm (the thickness of the chip) distant from
`interdependent circuitry arranged on an abutting chip,
`as opposed to up to 3000 um distant from interdepen-
`dent circuitry on the same chip. So, instead of designing
`each chip independently, circuits can be placed on dif-
`ferent chips to reduce transmission delays by the stack-
`ing and through-chip wiring techniques of the inven-
`tion.
`Table l and FIG. 6 set forth an example of the signifi-
`cant density advantages obtained by constructing a
`multichip module in accordance with the present inven-
`tion.
`
`TABLE 1
`
`Package
`Type
`so:
`Gabe
`Invention
`
`DRAM
`Density
`(Mbits/in’)
`128
`2,434
`46,620
`
`SRAM
`Density
`(Mbits/in’)
`24
`427
`15,993
`
`Ra-
`tio
`i
`19
`364
`
`Ra-
`tio
`I
`is
`666
`
`DRAM/SRAM
`Ratio
`Storage
`Density
`5.3/l
`5.8/l
`2.9/i
`
`10
`
`25
`
`35
`
`In this example, the first package comprises DRAM
`or SRAM chips assembled with SOJ technology. the
`second package comprises DRAM or SRAM chips
`mounted in a “Cube” using technology such as that
`described in U.S. Pat. No. 4,525,921, entitled “High-
`Density Electronic Processing Package - Structure and
`Fabrication," and the third package comprises DRAM
`or SRAM chips mounted in an assembly pursuant to the
`present invention. The configurations used were a 4
`MBit DRAM scaled from 0.8-0.6 micrometer Ground
`Rules (GK) and a 1 Mbit SRAM in 0.6 micrometer
`G.R. For both DRAMs and SRAMs, the Cube packag-
`ing produced a density improvement of more than an
`order of magnitude over the SOJ package, while the
`present invention improved storage density by more
`than two orders of magnitude over the SOJ package.
`For the present invention the active surface depth
`effects the final packaging leverage. A DRAM package
`with a 10 micrometer depth for ‘metallized trenches plus
`the surrounding region, requires 20 micrometers with a
`guardband. in comparison, a SRAM package, with 1-2
`micrometers for devices, is assumed to need no more
`than 10 micrometers in total depth. The storage density
`of SRAM packages improves significantly for present
`invention technology in comparison with that obtain-
`able with SOJ or Cube approaches. This is an indication
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`that the ultimate silicon density is being approached
`using the present invention.
`Another measure of storage density leverage is to
`estimate the storage density for packages of approxi-
`mately the same height. Assuming a package height
`equal to the package width, then for a DRAM that is
`8.98 millimeters, a two chip high SOJ is 7.12 millime-
`ters. Further assuming that both the Cube and Present
`invention packages will be approximately square, then
`the following functional comparison (as shown in Table
`2) for 4M DRAMs can be obtained:
`TABLE 2
`
`Package Type
`2 Chip (SOJ)
`31 chip (cube)
`512 chip (Invention)
`
`Storage
`Density
`IM Byte
`16M Byte
`256M byte
`
`One further consideration to be addressed in connec-
`tion with the present invention is that the power dissipa-
`tion per unit volume increases with packaging density.
`Clearly, a multichip package fabricated pursuant to the
`present invention will have a greater power density
`than most previous multichip packages. Also, since not
`all chips are selected at a given time, standby power is
`extremely important. For example, in a DRAM pack-
`age, perhaps only 1/16 or 1/32 chips may be selected
`for particular applications. Therefore, reducing standby
`power can be very significant.
`One possible technique to lowering power dissipation
`is to improve retention time and reduce refresh require-
`ments. Also, with high densities, Flash-EPROM chips
`can be added to the stack so that address locations
`which change infrequently can have zero power dissi-
`pation data stored in Flash-EPROM cells.
`Lastly, a multichip package constructed pursuant to
`the present invention is compact and a good thermal
`conductor. The package could be cooled with a cold tip
`and should be consistent with low temperature opera-
`tion, e.g., in liquid nitrogen.
`_
`While the invention has been described in detail
`herein in accordance with certain preferred embodi-
`ments thereof, many modifications and changes therein
`may be effected by those skilled in the art. Accordingly,
`it is intended by the appended claims to cover all such
`modifications and changes as fall within the true spirit
`and scope of the invention.
`What is claimed is:
`1. A multichip package comprising:
`a carrier having an upper surface;
`a first integrated circuit device having a first surface
`and a second surface in substantially parallel oppos-
`ing relation, said integrated circuit device having
`an active layer adjacent said fnst surface and a
`substrate adjacent said second surface, the thick-
`ness of said first device from said first surface to
`said second surface being less than thirty microme-
`ters, said first device further including a plurality of
`metallized trenches therein extending from said
`first surface to said second surface thereof, each ofa
`said metallized trenches hav