US008841778B2
`
`(12) United States Patent
`Leedy
`
`(10) Patent No.:
`
`(45) Date of Patent:
`
`US 8,841,778 B2
`*Sep. 23, 2014
`
`(54) THREE DIMENSIONAL MEMORY
`STRUCTURE
`
`(71) Applicant: Glenn J Leedy, Carmel, CA (US)
`
`(72)
`
`Inventor: Glenn J Leedy, Carmel, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`438/977 (2013.01); HOIL 2224/8384 (2013.01);
`H01L 27/10897 (2013.01)
`USPC .......... .. 257/777; 257/778; 257/685; 438/977
`(58) Field of Classification Search
`USPC ........ .. 257/777-778, 685-686; 438/455, 977,
`438/107-108; 365/63, 51, 230.06
`See application file for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(21) Appl. No.: 13/963,149
`
`(22)
`
`(65)
`
`Filed:
`
`Aug. 9, 2013
`
`Prior Publication Data
`
`US 2013/0320563 A1
`
`Dec. 5,2013
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 12/788,618, filed on
`May 27, 2010, which is a continuation of application
`No. 10/143,200,
`filed on May 13, 2002, now
`abandoned, which is a continuation of application No.
`09/607,363, filed on Jun. 30, 2000, now Pat. No.
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`
`(51)
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`Int. Cl.
`H01L 23/48
`H01L 25/065
`H01L 27/06
`GIIC 5/02
`H01L 23/522
`GIIC 5/06
`H01L 21/768
`H01L 27/108
`(52) U.S. Cl.
`CPC ............ .. GIIC 5/02 (2013.01), H01L 25/0657
`(2013.01); H01L 27/0688 (2013.01); HOIL
`2924/01079 (2013.01); H01L 23/481 (2013.01);
`H01L 23/5226 (2013.01); GIIC 5/06
`(2013.01); H01L 21/76898 (2013.01); YIOS
`
`2,915,722 A
`3,202,948 A
`
`12/1959 Foster
`8/1965 Farrand
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`DE
`EP
`
`3233195
`189976
`
`3/1983
`8/1986
`
`(Continued)
`OTHER PUBLICATIONS
`
`Bollmann et a1., Three Dimensional Metallization for Vertically Inte-
`grated Circuits, Materials for Advanced Metallization, 1997, Euro-
`pean Workshop; Date of Conference: Mar. 16-19, 1997.
`
`(Continued)
`
`Primary Examiner — David Lam
`(74) Attorney, Agent, or Firm — Useful Arts IP
`
`ABSTRACT
`(57)
`A Three-Dimensional Structure (3DS) Memory allows for
`physical separation of the memory circuits and the control
`logic circuit onto different layers such that each layer may be
`separately optimized. One control logic circuit sufiices for
`several memory circuits, reducing cost. Fabrication of 3DS
`memory involves thinning of the memory circuit to less than
`50 microns in thickness and bonding the circuit to a circuit
`stack while still in wafer substrate form. Fine-grain high
`density inter-layer vertical bus connections are used. The 3DS
`memory manufacturing method enables several performance
`and physical size efiiciencies, and is implemented with estab-
`lished semiconductor processing techniques.
`
`138 Claims, 9 Drawing Sheets
`
`103!)
`
`105C
`
`NV ’llll’l"A
`
`VIIIIIJ
`IIIIIIJ TIIIIIIIIIA.
`
`
`
`
` VIIIIIIA
`VIIIIIJ
`
`
`B
`
`1051)
`
`1035
`1053
`
`101
`
`SAMSUNG ET AL. EXHIBIT 1001
`
`Page 1 of31
`
`
`
`TIIIIIA
`VIIIIIIIIIIIIIIJ.
`TIIIIIA VIIIIIIIIIIIIIIA
`
`VIIIIIIIIIIIIIIJ
`VIIIIIIIIIIIIIIJ
`M:1072:
`
`
`SAMSUNG ET AL. EXHIBIT 1001
`Page 1 of 31
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`RE34,893 E
`
`>>>>>>>>>>D>D>>>>>>>>>>>>D>>>>>>D>>>>>>D>>>>D>D>D>D>D>D>D>D>D>D>>D>>D>D>D>>D>D>D>D>D>>D>D>D>D>D>>>D>D>D>D>>>D>D>D>
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`>D>>>>>D>>>>>>D>>>>>>D>>>>>>D>>>>>>>>>>>>D>D>>D>>D>D>D>>D>D>D>D>D>>D>D>D>D>D>>>D>D>D>D>>>D>D>D>D>D>D>D>D>D>D>D>
`
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`5,847,929
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`5,870,176
`5,880,010
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`5,892,271
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`6,002,268
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`6,027,958
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`6,045,625
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`6,300,935
`6,301,653
`6,320,593
`6,335,491
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`6,392,304
`6,417,027
`6,445,006
`6,511,857
`6,518,073
`6,551,857
`6,563,224
`6,617,671
`6,632,706
`6,682,981
`6,707,160
`6,713,327
`6,714,625
`
`>>>>>D>D>>>>>F1'1>>>>>>D>>>>>>>>>>D>D>D>>D>D>D>D>D>>D>D>D>D>D>D>>D>D>D>D>>
`
`B1
`B1
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`_.-- 100
`
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`
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`Sheet 2 of9
`
`US 8,841,778 B2
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`US 8,841,778 B2
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`100
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`U.S. Patent
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`U.S. Patent
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`Sheet 6 of9
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`US 8,841,778 B2
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`
`1
`THREE DIMENSIONAL MEMORY
`STRUCTURE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to stacked integrated circuit
`memory.
`2. State of the Art
`
`Manufacturing methods for increasing the performance
`and decreasing the cost of electronic circuits, nearly without
`exception, are methods that increase the integration of the
`circuit and decrease its physical size per equivalent number of
`circuit devices such as transistors or capacitors. These meth-
`ods have produced as of 1996 microprocessors capable of
`over 100 million operations per second that cost less than
`$1,000 and 64 Mbit DRAM circuits that access data in less
`than 50 ns and cost less than $50. The physical size of such
`circuits is less than 2 cm2. Such manufacturing methods
`support to a large degree the economic standard of living in
`the major industrialized countries and will most certainly
`continue to have significant consequences in the daily lives of
`people all over the world.
`Circuit manufacturing methods take two primary forms:
`process integration and assembly integration. Historically the
`line between these two manufacturing disciplines has been
`clear, but recently with the rise in the use of MCMs (Multi-
`Chip Modules) and flip-chip die attach, this clear separation
`may soon disappear. (The predominate use of the term Inte-
`grated Circuit (IC) herein is in reference to an Integrated
`Circuit in singulated die form as sawed from a circuit sub-
`strate such as s semiconductor wafer versus, for example, an
`Integrated Circuit in packaged form.) The majority of ICs
`when in initial die form are presently individually packaged,
`however, there is an increasing use of MCMs. Die in an MCM
`are normally attached to a circuit substrate in a planar fashion
`with conventional IC die I/O interconnect bonding methods
`such as wire bonding, DCA (Direct Chip Attach) or FCA
`(Flip -Chip Attach).
`Integrated circuit memory such as DRAM, SRAM, flash
`EPROM, EEPROM, Ferroelectric, GMR (Giant MagnetoRe-
`sistance), etc. have the common architectural or structural
`characteristic of being monolithic with the control circuitry
`integrated on the same die with the memory array circuitry.
`This established (standard or conventional) architecture or
`circuit layout structure creates a design trade-off constraint
`between control circuitry and memory array circuitry for
`large memory circuits. Reductions in the fabrication geom-
`etries of memory cell circuitry has resulted in denser and
`denser memory ICs, however, these higher memory densities
`have resulted in more sophisticated control circuitry at the
`expense of increased area of the IC. Increased IC area means
`at least higher fabrication costs per IC (fewer ICs per wafer)
`and lower IC yields (fewer working ICs per wafer), and in the
`worst case, an IC design that carmot be manufactured due to
`its non-competitive cost or unreliable operation.
`As memory density increases and the individual memory
`cell size decreases more control circuitry is required. The
`control circuitry of a memory IC as a percentage of IC area in
`some cases such as DRAMs approaches or exceeds 40%. One
`portion of the control circuitry is the sense amp which senses
`the state, potential or charge of a memory cell in the memory
`array circuitry during a read operation. The sense amp cir-
`cuitry is a significant portion of the control circuitry and it is
`a constant challenge to the IC memory designer to improve
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`sense amp sensitivity in order to sense ever smaller memory
`cells while preventing the area used by the sense amp from
`becoming too large.
`If this design constraint or trade-off between control and
`memory circuits did not exist, the control circuitry could be
`made to perform numerous additional functions, such as sens-
`ing multiple storage states per memory cell, faster memory
`access through larger more sensitive sense amps, caching,
`refresh, address translation, etc. But this trade-off is the
`physical and economic reality for memory ICs as they are
`presently made by all manufacturers.
`The capacity of DRAM circuits increases by a factor of
`four from one generation to the next; e.g. 1 bit, 4 bit, 16 Mbit
`and 64 Mbit DRAMs. This four times increase in circuit
`memory capacity per generation has resulted in larger and
`larger DRAM circuit areas. Upon introduction of a new
`DRAM generation the circuit yields are too low and, there-
`fore, not cost effective for high volume manufacture. It is
`normally several years between the date prototype samples of
`a new DRAM generation are shown and the date such circuits
`are in volume production.
`Assembling die in a stacked or three dimensional (3D)
`manner is disclosed in U.S. Pat. No. 5,354,695 ofthe present
`inventor,
`incorporated herein by reference. Furthermore,
`assembling die in a 3D manner has been attempted with
`regard to memory. Texas Instruments of Dallas Tex., Irvine
`Sensors ofCosta Mesa Calif. and Cubic Memory Corporation
`of Scotts Valley Calif. have all attempted to produce stacked
`or 3D DRAM products. In all three cases, conventional
`DRAM circuits in die form were stacked and the interconnect
`between each DRAM in the stack was formed along the
`outside surface of the circuit stack. These products have been
`available for the past several years and have proved to be too
`expensive for commercial applications, but have found some
`use in space and military applications due to their small
`physical size or footprint.
`The DRAM circuit type is referred to and often used as an
`example in this specification, however,
`this invention is
`clearly not limited to the DRAM type of circuit. Undoubtedly
`memory cell types such as EEPROMs (Electrically Erasable
`Programmable Read Only Memories), flash EPROM, Ferro-
`electric, GMR Giant Magneto Resistance or combinations
`(intra or inter) of such memory cells can also be used with the
`present Three Dimensional Structure (3DS) methods to form
`3DS memory devices.
`The present invention furthers, among others, the follow-
`ing objectives:
`1. Several-fold lower fabrication cost per megabyte of
`memory than circuits conventionally made solely with mono-
`lithic circuit integration methods.
`2. Several-fold higher performance than conventionally made
`memory circuits.
`3. Many-fold higher memory density per IC than convention-
`ally made memory circuits.
`4. Greater designer control of circuit area size, and therefore,
`cost.
`
`5. Circuit dynamic and static self-test of memory cells by an
`internal controller.
`
`6. Dynamic error recovery and reconfiguration.
`7. Multi-level storage per memory cell.
`8. Virtual address translation, address wind