PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 1
`
` UNITED STATES PATENT AND TRADE MARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` ---oOo---
`
`SAMSUNG ELECTRONICS CO. LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.,
`
` Petitioners,
`
` vs.
`
`ELM 3DS INNOVATIONS, LLC,
`
` Patent Owner.
`____________________________/
`
` Consolidated IPR Nos.:
`
` 2016-00386
` 2016-00387
` 2016-00388
` 2016-00389
` 2016-00390
` 2016-00391
` 2016-00393
` 2016-00394
` 2016-00395
` 2016-00687
` 2016-00691
`
` DEPOSITION OF
`
` PAUL D. FRANZON, PH.D.
`
` _________________________________
`
` THURSDAY, OCTOBER 6, 2016
`
`REPORTED BY: HOLLY THUMAN, CSR No. 6834, RMR, CRR
`
` (BO-099768)
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2164
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`
`
`Page 1
`
` UNITED STATES PATENT AND TRADE MARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` ---oOo---
`
`SAMSUNG ELECTRONICS CO. LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.,
`
` Petitioners,
`
` vs.
`
`ELM 3DS INNOVATIONS, LLC,
`
` Patent Owner.
`____________________________/
`
` Consolidated IPR Nos.:
`
` 2016-00386
` 2016-00387
` 2016-00388
` 2016-00389
` 2016-00390
` 2016-00391
` 2016-00393
` 2016-00394
` 2016-00395
` 2016-00687
` 2016-00691
`
` DEPOSITION OF
`
` PAUL D. FRANZON, PH.D.
`
` _________________________________
`
` THURSDAY, OCTOBER 6, 2016
`
`REPORTED BY: HOLLY THUMAN, CSR No. 6834, RMR, CRR
`
` (BO-099768)
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2164
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 2
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` I N D E X
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` INDEX OF EXAMINATIONS
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`EXAMINATION BY: PAGE
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`MR. NEWMAN 7
`
` --o0o--
`
` PREVIOUSLY MARKED EXHIBITS - FIRST REFERENCE
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` (NOT ATTACHED)
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`NO. DESCRIPTION PAGE
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`Exhibit 1002 Previously marked 8
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`Exhibit 2163 Previously marked 47
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`Exhibit 2162 Previously marked 93
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`Exhibit 1045 Previously marked 126
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
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`Elm Exhibit 2159, Page 2
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 3
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` --o0o--
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` Deposition of PAUL D. FRANZON, Ph.D., taken by
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`the Patent Owner, at MINTZ LEVIN, 44 Montgomery
`
`Street, Suite 3600, San Francisco, California
`
`94104, commencing at 9:04 A.M., on THURSDAY,
`
`OCTOBER 6, 2016, before me, HOLLY THUMAN, CSR, RMR,
`
`CRR.
`
` --o0o--
`
` APPEARANCES
`
`FOR PETITIONER SAMSUNG ELECTRONICS CO., LTD.:
`
` PAUL HASTINGS LLP
` 515 South Flower Street, 25th Floor
` Los Angeles, California 90071
` By: PHILLIP CITROEN, Attorney at Law
` phillipcitroen@paulhastings.com
` ANDREW B. GROSSMAN, Attorney at Law
` andrewgrossman@paulhastings.com
`
`FOR PETITIONER MICRON TECHNOLOGY, INC.:
`
` O'MELVENY & MYERS
` 610 Newport Center Drive, 17th Floor
` Newport Beach, California 92660
` By: JOHN KAPPOS, Attorney at Law
` jkappos@omm.com
`
` O'MELVENY & MYERS, LLP
` 400 South Hope Street
` Los Angeles, California 90071-2899
` By: BRIAN MERRILL COOK, Attorney at Law
` bcook@omm.com
`
`FOR PETITIONER SK HYNIX INC.:
`
` K&L GATES LLP
` 70 West Madison Street, Suite 3100
` Chicago, Illinois 60602-4207
` By: BENJAMIN E. WEED, Attorney at Law
` benjamin.weed@klgates.com
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 3
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 4
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`(Appearances, cont'd)
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`FOR THE PATENT OWNER:
`
` MINTZ, LEVIN, COHN, FERRIS, GLOVSKY & POPEO,
` P.C.
` One Financial Center
` Boston, Massachusetts 02111
` By: MICHAEL C. NEWMAN, Attorney at Law
` mcnewman@mintz.com
` MATTHEW GALICA, Attorney at Law
` msgalica@mintz.com
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
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`Elm Exhibit 2159, Page 4
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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` SAN FRANCISCO, CALIFORNIA
`
` THURSDAY, OCTOBER 6, 2016
`
` 9:04 A.M.
`
` --o0o--
`
` PAUL D. FRANZON, PH.D.,
`
` _________________________________
`
`called as a witness, having been first duly sworn,
`
`was examined and testified as follows:
`
` ---oOo---
`
` PROCEEDINGS
`
` MR. NEWMAN: Just a matter of business for
`
`the record. The parties have agreed to the
`
`following reciprocal agreement: Parties agree to a
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`single consolidated deposition for all of IPR
`
`2016-00386, -387, -388, -389, -390, -391, -393,
`
`-394, -395, and the related IPR 2016-00687, and
`
`-691.
`
` Parties agree that this single
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`consolidated deposition can be used in each of the
`
`11 separate IPRs.
`
` The parties also agree to a single
`
`consolidated redirect, to the extent necessary,
`
`upon conclusion of the cross-examination.
`
` While the parties agree that the testimony
`
`guidelines apply as set forth in 77 Fed Register
`
`09:04:46
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`09:04:47
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`09:04:50
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`09:04:53
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`09:04:58
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`09:05:11
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`09:05:36
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`09:05:38
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`09:05:43
`
`09:05:47
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 5
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 6
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`48756, 48772, Appendix D, which prohibits counsel
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`from offering the witness -- from consulting or
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`conferring with the witness regarding the substance
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`of the witness's testimony already given or
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`anticipated to be given, except for the purposes of
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`conferring on whether to assert a privilege against
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`testifying or on how to comply with a Board order.
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` However, while the parties agree that
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`conferring with the witness during the day of the
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`deposition is improper, the parties have agreed
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`that, to the extent the deposition lasts multiple
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`days, after the deposition has concluded for the
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`day, Counsel will be allowed to meet with and
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`prepare the witness for the following day's
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`deposition.
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` Further, the parties agree that directly
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`following the end of cross-examination, the
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`defendant will be -- the defending party will be
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`allowed to speak to their witness prior to
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`redirect.
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` Counsel, did I state that correctly?
`
` MR. CITROEN: Yes. If I can just add one
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`other stipulation. I'll be making objections on
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`behalf of each of the three entities that are
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`involved for the petitioner.
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`09:05:50
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`09:06:55
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`09:06:57
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`09:07:01
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 6
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 7
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` EXAMINATION BY MR. NEWMAN
`
`BY MR. NEWMAN:
`
` Q. Good morning, Dr. Franzon.
`
` A. Good morning.
`
` Q. Have you ever been deposed before?
`
` A. Yes.
`
` Q. How many times?
`
` A. I'm not sure. I don't recall. A few.
`
` Q. More than five?
`
` A. Around five, plus or minus.
`
` Q. Have you ever been deposed in an inter
`
`partes review matter before?
`
` A. Yes.
`
` Q. On behalf of patent owner or petitioner?
`
` A. On behalf of the patent owner.
`
` Q. Have you ever testified on behalf of
`
`petitioner in an IPR before?
`
` A. No.
`
` Do you have a staple remover, please?
`
`Could I remove the staples while we're looking at
`
`documents?
`
` Q. We can -- I'll get one for you.
`
` A. Thank you.
`
` I've just handed you what's been marked as
`
`Exhibit 1002 from the -395 IPR with respect to the
`
`16:29:58
`
`09:07:11
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`09:07:11
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`09:08:35
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`09:08:40
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`09:08:43
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 7
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 8
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`'732 patent.
`
` (Previously marked Exhibit 1002 was
`
` placed before the witness.)
`
`BY MR. NEWMAN:
`
` Q. Do you recognize this?
`
` A. Yes.
`
` Q. And what is it?
`
` A. It's a report I wrote.
`
` Q. Are the statements in here true to the
`
`best of your knowledge?
`
` A. Yes.
`
` Q. Is there anything you would like to
`
`correct in this report?
`
` Let me withdraw that question.
`
` Is there anything that you've noticed that
`
`is wrong in this report that you would like to
`
`correct?
`
` A. No, though there might be certain things I
`
`notice as we go along.
`
` Q. Have you been asked to provide a
`
`supplemental declaration in this matter?
`
` A. No.
`
` Q. Please turn to paragraph 15 of
`
`Exhibit 1002. And throughout the day, when I
`
`reference Exhibit 1002, it will be Exhibit 1002
`
`09:08:53
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`09:08:54
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`09:08:54
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`09:08:55
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`09:08:55
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`09:08:58
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`09:08:59
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`09:09:05
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`09:09:07
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`09:09:09
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`09:09:11
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`09:09:12
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`09:09:28
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`09:09:30
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`09:09:32
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`09:09:34
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`09:09:34
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`09:09:37
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`09:09:40
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`09:09:41
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`09:09:43
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`09:10:07
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`09:10:10
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`09:10:15
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 8
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
`
`Page 9
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`from the -395 IPR.
`
` Paragraph 5, you mention that the relevant
`
`field is semiconductor processing.
`
` Can you describe what that field includes?
`
` MR. CITROEN: Objection as to form.
`
` THE WITNESS: I give that as an example of
`
`a relevant field.
`
`BY MR. NEWMAN:
`
` Q. What does the field of semiconductor
`
`processing include?
`
` A. I give this as an example of the relevant
`
`field. This patent is entitled, in fact, memories.
`
`So this patent is about memories and semiconductor
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`processing. Semiconductor processing is the
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`processes that are used to create integrated
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`circuits.
`
` Q. Does that include fabrication of
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`semiconductor devices?
`
` MR. CITROEN: Objection as to form.
`
` THE WITNESS: Yes.
`
`BY MR. NEWMAN:
`
` Q. Does semiconductor processing include
`
`packaging of semiconductor devices?
`
` A. It can.
`
` Q. Please turn to paragraph 7 of
`
`09:10:20
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`09:10:24
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`09:10:26
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`09:10:33
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`09:10:38
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`09:10:48
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`09:10:49
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`09:11:19
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`09:11:25
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`09:11:26
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`09:11:27
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`09:11:29
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`09:11:32
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`09:11:40
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`09:11:49
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 9
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 10
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`Exhibit 1002.
`
` You mention you have over 20 years of
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`experience with 3D circuits, applications,
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`analysis, and fabrication.
`
` Can you please describe your experience in
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`fabrication?
`
` A. Did you bring a copy of my CV?
`
` Q. No. Can you describe it in the absence of
`
`your CV?
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` A. I can start, but it would be more complete
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`if I have a copy of my CV.
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` MR. CITROEN: And Counsel, we brought --
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`we probably have a copy of the CV. It may be
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`helpful if he has it in front of him instead of
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`trying to remember based on just sitting here
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`today. It would be easier if he uses that.
`
`BY MR. NEWMAN:
`
` Q. Well, let's just see what you can do
`
`without it.
`
` But I appreciate that, Counsel. And to
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`the extent that he needs it, we'll consider putting
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`it in.
`
` A. In my undergraduate training, I took
`
`courses in VLSI design. To be a VLSI designer, one
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`has to understand semiconductor processing and
`
`09:11:51
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`09:11:56
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`09:11:58
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`09:12:02
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`09:12:04
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`09:12:07
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`09:12:18
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`09:12:44
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`09:12:47
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`09:12:47
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`09:12:49
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`09:12:51
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`09:12:54
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`09:12:56
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`09:12:58
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`09:13:05
`
`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 10
`
`
`
`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 11
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`apply the issues that arise in semiconductor
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`processing to the principles of design. There are
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`numerous issues there that come up the designer has
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`to be cognizant of in doing so.
`
` During my undergraduate degree, I designed
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`a chip that was fabricated. And in the design of
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`that chip, I had to be aware of the limitations
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`imposed on the chip design by semiconductor
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`processing.
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` I then went on and worked for Defence
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`Science and Technology Organisation in Australia.
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`I can't talk about everything I did there, but I
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`was involved in the design of chips there related
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`to various military projects. And in doing so, I
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`had to be cognizant, aware, and apply the issues in
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`semiconductor processing to the design of those
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`chips.
`
` I then went on to do a Ph.D. in electrical
`
`and electronic engineering, University of Adelaide.
`
`The title of my Ph.D. -- the subject of my Ph.D.
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`was related to wafer-scale integration.
`
` I -- earlier in my Ph.D., I wrote a yield
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`simulator. What a yield simulator does is take
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`issues involved in semiconductor processing and
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`defects introduced during semiconductor processing
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
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`Elm Exhibit 2159, Page 11
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`and estimate the yield of the detailed layout based
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`on those details.
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` In preparing this tool, I relied heavily
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`on work reported out of IBM on yield management of
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`DRAMs. And, of course, these patents are about
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`DRAMs as well. And I learned a lot about DRAMs
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`while I was an undergraduate and as a graduate
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`student.
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` I then went on and consulted at Bell Labs
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`as related to my Ph.D. At Bell Labs, I designed
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`and built a wafer-scale circuit.
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` Because I was doing something unusual, I
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`had to interact quite closely with the fabrication
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`facility in Allentown, Pennsylvania. There were
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`features I had to add to the chip to deal with
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`issues related to semiconductor processing that
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`arise in doing so.
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` That wafer was built, and it became part
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`of my Ph.D.
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` I then went on to North Carolina State
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`University. Early there, I had a consulting job
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`with what was then called the Microelectronics
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`Center of North Carolina. They had a yield problem
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`in their 1-micron fabrication facility. I worked
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`with them to help resolve that yield problem.
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`09:15:55
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 12
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 13
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` And that involved designing and -- you
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`know, with others, yield monitors that ran through
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`the fab, discussing yield-related issues with the
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`fabrication engineers and with the other principal
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`investigators at MCNC, and building with others
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`further versions of the yield estimator that I did
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`during my Ph.D.
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` I then have formed numerous projects at
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`North Carolina State University that require
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`fabrication either in our facility or elsewhere. I
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`ran for quite a period of time a series of projects
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`involving MEMS, or micromachines.
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` Again, in the design of the baseline MEMS,
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`or micromachines, we -- you have to be aware of the
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`issues related to semiconductor processing in the
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`design so as to get structures that yield.
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` We also did post-fabrication of
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`structures. We would design them and get them
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`built at MCNC or Sandia National Labs.
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` We then would go into the clean room,
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`identify processes to solve specific problems to
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`enable the devices we wanted built. And I had
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`graduate students run those processes in our clean
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`room at NC State.
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` For example, we had to put down
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`09:17:30
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 13
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`metallization on structures that came in from
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`Sandia National Labs. The structures from Sandia
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`National Labs did not have a metal on them. We
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`wanted metal on them either for reflectance
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`purposes or conductivity purposes. And we had to
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`develop processes to do that.
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` I recall doing that on moving parts and
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`stationary parts in the micromachine structure. I
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`identified processes to solve specific problems,
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`and I had graduate students performed those
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`processes.
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` The -- for example, we had to get
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`metallization in crossing structures. We invented
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`that, we did not file a patent, a process to do
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`that that involved multiple metallization steps, so
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`it was done in our fab. The -- and we -- so we
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`built and tested these MEMS structures.
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` In one of those MEMS projects, we were
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`working with -- we were working with a company
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`called NIPT. They were thinning chips, and we had
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`to -- in integrating those chips with our MEMS
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`structures. And so we were starting already to
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`deal with 3D structures and the integration of
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`those and the problems that arise in 3D processing.
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` We -- in addition, around that time, I
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 14
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`started a series of projects related to molecular
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`electronics. My -- we had to build and test the
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`integration structures onto which the synthesized
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`molecules were inserted, and we had to do the
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`testing of those.
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` We developed a number of structures that
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`we built in the labs at NC State. Again, I often
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`identified the overall process that would be used
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`in that and had grad students perform the details
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`of the work.
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` For example, we invented, though an
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`invention disclosure -- might have filed an
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`invention disclosure, but I don't think a patent
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`was pursued. We developed a structure that was a
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`cantilever structure that we built entirely in our
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`labs for purposes of testing molecules, and we
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`fabricated that and worked. That involved numerous
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`steps. We had to integrate a process flow in our
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`lab.
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` In addition, we had to -- we built a
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`structure whose name I don't recall, "Nano Cell" or
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`something like that. Since you won't let me see my
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`resume, I can't look up the exact name.
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` That structure -- which, actually, we did
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`file a patent on, and it was granted, and I'm an
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 15
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`inventor on that patent -- that structure was
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`fabricated for the purposes of integrating multiple
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`molecules into a circuit, and we built those. We
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`actually developed a new process to create -- to
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`create metal islands at the nano scale on the
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`semiconductor surface in order to -- in order to
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`build and fabricate the structure.
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` Also around that time, I was in a 3D
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`project, again with MCNC, within MCNC, no longer
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`Microelectronics Center of North Carolina. This 3D
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`project, we -- there was a solder process that we
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`applied in a 3D stack to create 3D memories. We
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`designed a number of structures to utilize that
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`solder process in order to integrate high-density
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`3D memories. I believe this project was funded by
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`DARPA.
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` Around the same time, I was involved in
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`another project called SHOCC, which was
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`high-density integration for the purposes of
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`integrating high-density chips to create a
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`high-density structure, much like many of these
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`patents are about, increasing functional density.
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` In doing that, we had to deal with
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`limitations of the processes used to make the 3D
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`integration structures in our designs, which we
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 16
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 17
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`designed, and there were some structures built --
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`BY MR. NEWMAN:
`
` Q. Let me stop you there.
`
` When you say that you're stacking, do you
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`consider stacking to be part of fabrication?
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` A. In stacking 3D chips, you have to perform
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`various steps to create the -- the ability to
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`integrate in 3D, or even in 2 1/2-D.
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` The term "packaging" and "fabrication"
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`related to semiconductor integration is used
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`loosely. We used that term before. Sometimes
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`people refer to packaging 3DIC, through-silicon via
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`processing, et cetera. Some people refer to that
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`as semiconductor processing, because it is done in
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`the -- at the wafer level. Other people might
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`refer to that as packaging.
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` You may also do what's called wafer-scale
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`packaging. There's various steps that are done in
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`the semiconductor plant before transferring to an
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`OSAT, for example, for further integration
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`processes.
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` Q. So your --
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` A. Do you want to go back -- should I
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`continue answering your earlier question?
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` Q. No, I think that was fine. Thank you.
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`09:23:23
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 17
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 18
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` A. And I have done -- just to summarize, I
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`have lots of years of experience in semiconductor
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`processing since all those. I don't think I barely
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`got past 1999.
`
` Q. Great. That's the -- that's where we're
`
`looking for, anyway.
`
` So here in paragraph 7 of Exhibit 1002
`
`again, you mentioned 3D refers to stacking of chips
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`or circuits.
`
` Is there a difference between stacking
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`chips and stacking circuits?
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` A. The difference is that a -- you fabricate
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`a circuit on a chip. You can have chips that are
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`not circuits. For example, a MEMS chip is not a
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`circuit. And I talked about how we had a project
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`stacking a MEMS chip with a circuit chip.
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` But in general, these also are
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`interrelated to the logic as well, many chips and
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`circuits.
`
` Q. You mentioned interconnecting and bonding.
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` What does "interconnecting" mean?
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` A. "Interconnecting" is a very broad term.
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`It generally means connecting different functions
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`together, either horizontally or vertically or
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`both, or sometimes even wirelessly or optically.
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`09:24:53
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 18
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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` So interconnecting generally revolves
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`around communicating information on voltages from
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`one portion of the design to another portion of
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`design.
`
` Q. And what does "bonding" mean?
`
` A. "Bonding" again is a very general term.
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`It generally involves some sort of physical joining
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`of devices or layers or structures.
`
` Q. And you mentioned through-silicon vias
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`here. What are those?
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` A. A through-silicon via generally means a
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`vertical via that can connect the front side of a
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`chip or wafer to the back side of a chip or wafer.
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`Technically, you'd think the name "through-silicon"
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`means it has to pass through silicon, but often
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`it's used for structures that don't pass through
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`silicon.
`
` Q. Have you -- are you familiar with the term
`
`"front end of line"?
`
` A. Yes.
`
` Q. Are you familiar with the term "back end
`
`of line"?
`
` A. Yes.
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` Q. What is -- can you describe what "front
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`end of line" means?
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`09:26:06
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 19
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`Page 20
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` A. "Front end of line" generally means
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`fabrication of the transistor structures and
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`related aspects of the -- the semiconductor
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`structure.
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` Q. What does "back end of line" mean?
`
` A. "Back end of the line" generally refers to
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`fabrication of the wiring layers that connect the
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`chip together.
`
` Q. Why are these differentiated?
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` MR. CITROEN: Objection as to form.
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` THE WITNESS: Convenience.
`
`BY MR. NEWMAN:
`
` Q. Let me ask the question: Why is front end
`
`of line and back end of line differentiated?
`
` A. Convenience.
`
` Q. What convenience does it create?
`
` A. Convenience of description, just like you
`
`were using.
`
` Q. What steps are involved in the front end
`
`of line?
`
` A. There are many steps involved in front end
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`of the line. I have not prepared a detailed answer
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`to that question.
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` Q. Do you know the answer?
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` A. I know there are many steps involved that
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`617-542-0039
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`DTI Court Reporting Solutions - Boston
`www.deposition.com
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`Elm Exhibit 2159, Page 20
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`can be used in the front end of the line. And --
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`but I'm not -- I'm not prepared today to give an
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`exhaustive list of such steps.
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` Q. Is metallization involved in front end of
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`line?
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` A. If metallization is used to create the
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`transistor gate, one may consider it a
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`front-end-of-the-line process.
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` Q. Can you give me an example of when
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`metallization is used to create a transistor gate?
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` A. That was the example. Many gates today
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`have many -- many MOSFET transistors today,
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`M-O-S-F-E-T, have metal gates.
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` Q. What type of metal?
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` A. There's a variety of metals they use. I
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`haven't -- I haven't prepared a detailed answer for
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`that today.
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` Q. Did they use aluminum?
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` A. I have not prepared a detailed answer for
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`that today.
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` Q. Do you know whether or not they use
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`aluminum?
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` A. I have not researched that question.
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` Q. In paragraph 7, you also mentioned
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`packaging. What are you referring to there?
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`09:28:42
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 21
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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` A. Packaging generally refers to the
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`connecting of the chip to other chips or to other
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`modules in the system. It refers -- it can also
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`refer to mechanical protection of the chips against
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`their environment. It can also refer to features
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`added to the chips or chip stack to help in cooling
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`of the chips. It refers to the provisioning of
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`power and ground to the chips as well as
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`interconnect signals.
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` Q. Does packaging involve any of the
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`circuitry?
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` MR. CITROEN: Objection as to form.
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` THE WITNESS: In designing packaging, one
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`has to co-design it with the circuits. And in
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`fact, the -- my fellowship that I earned as a
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`member of the IEEE, on the grade of fellow, is in
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`the area of chip package co-design.
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`BY MR. NEWMAN:
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` Q. Is packaging separate from back end of
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`line?
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` A. Not necessarily, no.
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` Q. Does packaging involve the through-silicon
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`vias?
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` A. Some people refer to a through-silicon via
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`process as the packaging process. Some people
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`09:30:11
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`617-542-0039
`
`DTI Court Reporting Solutions - Boston
`www.deposition.com
`
`Elm Exhibit 2159, Page 22
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`
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`PAUL D. FRANZON, PH.D. - 10/6/2016
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`refer to through-silicon via processing as
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`something done in wafer fab.
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` Q. Is -- packaging is not done in the fab,
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`then?
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` A. Packaging steps are commonly performed in
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`fabs.
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` Q. What packaging steps are performed in
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`fabs?
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` A. I haven't given a -- I haven't prepared a
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`detailed answer to that question.
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` Q. But you know that some of them are.
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`Right?
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` A. Some of them are. For example,
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`through-silicon vias are often performed in
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`semiconductor fabs.
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` For example, redistribution layers which
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`are necessary for connecting to the packaging are
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`often performed in semiconductor fabs.
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` For example, joining of chips in a 3D
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`structure are often performed in the semiconductor
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`fabs.
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` Q. And what parts of packaging are not
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`performed in fabs?
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` A. Again, I haven't researched the specific
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`answer to that question. And frankly, it varies
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`617-542-0039
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`DT
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