PACKAGING DECISIONS & SYSTEM DESIGN PROCESS 121
`
`Table 3-3 Performance and Cost Factors.
`
`I PERFORMANCE FACTORS
`
`1. Size and weight
`2. Interconnection capacity within each interconnection level
`3. Connection capacity between interconnection levels
`4. Electrical delay and noise
`5. Power consumption
`6. Heat dissipation
`
`I COST FACTORS
`
`l. Production cost:
`a. Manufacturing cost
`(setting up the manufacturing line and buying the required materials)
`b. Manufacturability costs
`(running the manufacturing line, mainly the impact of test and yield)
`2. Post production costs:
`(mainly replacing failed units-the effect of field reliability)
`3. Design and prototyping costs
`4. Time-to-market
`
`I
`
`I
`
`process can be broken down into steps, some of which are carried out
`simultaneously:
`
`1. Determine requirements and goals of the system.
`2. Express requirements and goals in terms of performance and cost
`factors.
`3. Determine partitioning and packaging alternatives.
`4. Evaluate performance and cost of design alternatives in terms of
`performance and cost factors.
`5. Decide on alternative that best meets the system's aims.
`
`These are discussed and an example given in the next section.
`
`3.7 DETERMINING SYSTEM REQUIREMENTS AND GOALS
`
`The requirements of the system are the "must haves," those aspects of
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`122 PACKAGE SELECTION: A SYSlEMS NEED PERSPECTIVE
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`performance and price that the system must achieve. These become constraints
`on the performance and cost factors. The goals of the system are the "want to
`haves," those aspects of performance and price where maximization is highly
`desirable. Satisfaction of the goals must be judged in terms of tradeoffs between
`the performance and cost factors. One of the first steps in system design is to
`determine the requirements and goals and to determine the relative weight or
`importance of each one. These requirements and goals should closely match
`those of the end customer.
`Six categories of electronic systems were identified in Chapter I: consumer,
`aerospace and military, computers, biomedical and telecommunications and
`instrumentation. Each of these system types has different requirements and goals
`related to packaging performance and cost.
`For example, most consumer products have a requirement that they be
`passively air cooled (no fan). Their goals are heavily weighed towards
`minimizing production cost, followed by maximizing customer satisfaction
`(minimizing post production costs) and minimizing size and weight. Rarely, is
`minimizing electrical delay an important goal.
`Aerospace and military products tend to emphasize performance and post
`production cost factors in their goals. However, they often are given minimum
`requirements in terms of these factors. For example, a radar signal processor
`might be required to resolve a target with a 1 meter squared radar cross section
`at 100 miles, fit into one electronics bay, and the technician must be able to
`locate and repair a fault within half an hour. They usually must be air cooled.
`A recent trend has been to pay increased importance to minimizing production
`cost.
`The requirements and goals of a computer system depend on the application.
`For example, a desktop workstation might have requirements that it be air cooled
`with a quiet fan, be software compatible with previous models and meet federal
`EMI standards. The goals of the system are to maximize computation
`performance while controlling cost. Marketing studies determine suitable
`minimum targets for these goals. It is shown in Section 3-10 how workstation
`performance depends on interconnect capacity and delay.
`On the other hand,
`a notebook computer must be passively air cooled and must be able to use a
`certain chip set. Ergonomics and price drive the goals of the system. Total
`system size, weight and user friendliness, together with battery life (power
`consumption) and selling price, all are given similar weight.
`At the other end of the scale, supercomputer and mainframe applications
`require high performance, while cost is secondary. These applications require
`high interconnection capacities throughout the entire system. Designers need to
`avoid the low interconnection capacities usually associated with the higher levels
`of the packaging hierarchy. Thus, they tend to make extensive use of MCM
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`DEfERMINING SYSTEM REQUIREMENTS & GOALS 123
`
`technology. An unusual perfonnance goal, sometimes appearing in large systems
`such as a supercomputer, is the need for scalability-the ability to make the same
`system in several different sizes without redesigning the system for each size.
`An example is being able to expand a system with 512 processors to one with
`1024 processors, without having to slow down the system to compensate for the
`larger size.
`The aims in biomedical systems vary widely according to application.
`However, they have tended to emphasize perfonnance and post production cost
`factors over production cost
`In main telecommunications switches, international standards dictate many
`requirements for perfonnance. The need to minimize system down time for
`maintenance and failures often is translated into a set of post production
`requirements and goals. For example, it is a common requirement that the
`It also must be
`switches be air cooled to simplify maintenance and repair.
`possible to run the system on batteries if main power fails. The goals of the
`system then are to maximize bandwidth (a function of interconnect capacity and
`electrical delay) and minimize life cycle cost.
`High end instrumentation systems, such as test equipment, often must
`operate at higher speeds than the systems they are designed to test. The pin
`counts of the high speed bipolar and gallium arsenide parts used usually have
`been low. Thus, hybrid packaging has been a common solution. Recently, the
`sizes and pin counts of chips made in these technologies have increased
`dramatically. As the pin counts climb, it becomes necessary to use packaging
`technologies that combine high interconnect capacity and high speed, such as an
`MCM technology.
`
`3.8 DETERMINING AND EVALUATING
`PACKAGING ALTERNATIVES
`
`Currently, the process of detennining a set of suitable packaging alternatives
`requires that the designer have some insight into the broad range of alternatives
`available and how their relationship to the requirements and goals of the system.
`No general methodology for generating these alternatives exists today. Often,
`the alternatives are discovered during the evaluation process, so the current
`emphasis is on making this evaluation process as efficient as possible.
`Partitioning alternatives usually are generated on the basis that functions should
`be grouped into chips and packages to minimize the need for high cost
`connections between the different levels of the packaging hierarchy.
`There are two levels of evaluation possible. First order evaluations use
`simple perfonnance and cost measures and models, such as substrate efficiency
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`124 PACKAGE SELECfION: A SYSTEMS NEED PERSPECTIVE
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`and time of flight delay, to quickly evaluate a large number of alternatives [1],
`[8] and [9]. Computer aided engineering (CAE) tools, such as SPEC [10] and
`PEPPER [11], are becoming more available to help with this task. These fIrst
`order evaluations often are useful in weeding out unsuitable alternatives. It often
`is necessary to conduct detailed evaluations to make the fInal decision and to
`determine the system parameters (such as the clock frequency). Detailed
`evaluations might be necessary when the possible options could violate a speciftc
`systems requirement (if the heat density is so high that air cooling might be
`difftcult). CAE tools are helpful in this task (MetaSim [12] for electrical delay
`and the routability estimators included in commercial tools). SPEC and PEPPER
`have some of these detailed evaluations built in.
`
`3.9 IMPACT OF SEMICONDUCTOR TECHNOLOGY
`
`The designer must decide which semiconductor technology to use: CMOS,
`bipolar, BiCMOS (bipolar and CMOS mixed together) or gallium arsenide, and
`which chip design style to use. The design style has two elements: circuit style
`(TTL or ECL logic families) and implementation style (gate array or full custom
`design). The choice affects the decision making process as follows:
`
`1. Determines the delay within each chip, both due to the circuits within
`the chip and the on-chip wiring.
`2. Determines how many functions can be provided within one chip. This
`is highest with CMOS technology. Large CMOS chips also tend to
`have high pin counts.
`3. Determines the on-chip interconnection capacity. This is generally
`high.
`4. Determines the power dissipated by the chip. This is high now, even
`for CMOS chips. There is a speed/power tradeoff to be considered.
`5. Determines semiconductor technology to use. Bipolar chips have lower
`test escape probabilities than CMOS chips.
`6. Determines cost. Large, complex chips have a cost usually greater than
`the fIrst level package cost.
`
`3.10 EXAMPLE OF THE SYSTEM DESIGN PROCESS
`
`In many computer products, particularly workstations, packaging technology has
`a main influence on system performance through its impact on memory access
`bandwidth. The memory is structured as a hierarchy (Figure 3-16), usually with
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`EXAMPLE OF THE SYSTEM DESIGN PROCESS 125
`
`Central
`
`, .................. ,
`
`pr~.~.~.~.~~~.~ .. ~:lt ),i~~lt~~~ r .................. :
`! Floating V
`/
`i
`~ Integer
`! Point
`!
`! Arithmetic!
`l
`~: Unit (lU)
`l Arithmetic l
`t ................. ~
`rR"'eg"':ls't'e"r"'~
`! Unit (FPU)i
`·
`.
`.....................
`s
`.
`·
`·
`.
`.
`·
`,.................. . ....
`·
`.
`..................
`!
`! Memory
`! management!
`i Unit (MMU) i
`
`..... •••••••••••••••••• 1
`
`Input!
`Outpu t
`
`t
`r-
`i
`
`Nt.· ~ U t d1+t a1
`I First Level Memory Cache 1 M 1
`N2.-~ U td2+t a2
`
`-~ Second Level Memory Cache
`
`Nt' ~ U td3+t a3
`
`M2
`
`Main Memory
`
`M3
`
`N i = Number of bits fetched each access
`. = Total round trip delay to fetch bits
`t d' +t
`al
`1
`M . = Number of bytes at each level
`1
`
`Figure 3-16 Block diagram of the main elements in a single CPU computer. Packaging
`affects workstation performance through the widths and speed of the data paths between
`each level of the memory hierarchy.
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`126 PACKAGE SELECTION: A SYSTEMS NEED PERSPECTIVE
`
`a small amount of fast memory (fIrst level cache) at the top of the hierarchy and
`a large amount of slow memory (main memory) at the bottom. This is part of
`the system organization.
`It is possible to write expressions that relate the
`computation performance of the system to the number of bits communicating
`between each level of the memory hierarchy (also called the fetch size, Nl, N2
`and N3, as shown in Figure 3-16), the interconnect delay between each level (tdl,
`td2, td3), the memory access time of each level (how long it takes to fetch a
`memory location for each memory chip tal' ta2 and ta3) and the number of
`memory locations at each level (Ml, M2 and M3). The performance is
`expressed as a function or model:
`
`Memory Performance '" f (Nl, N2 N3, tdl + tal' td2
`+ tal' td3 + ta3' Ml, M2, M3)
`
`(3-16)
`
`The elements in this expression relate directly to packaging performance factors
`[13], [14] and [15]. This function tends to be most sensitive to the attributes tdl
`+ tal' Ml and N2 (Nl is usually fixed), and reasonably sensitive to M2 and td2
`+ ta2.
`The choice of partitioning and packaging style has a large influence on the
`fetch sizes and interconnect delays. For example, the first level cache often is
`packaged with the CPU on one chip, allowing a minimum tdl + tal. However,
`in 1992 technologies, this limits Ml to 8 - 16 kBytes, which really is too small.
`This is the case assumed here.
`The progress of the IC technology (and the ability to integrate a fast, large,
`fIrst level cache onto the CPU chip with good yields) must not be neglected. In
`particular, a company may decide not to pursue developing an MCM technology
`for its computer chips if an anticipated small chip MCM product would only
`have a two year performance lead on the equivalent function packaged entirely
`within one chip [16].
`With the fIrst level cache placed on the CPU chip, packaging determines
`performance mainly through its effect on N2, M2 and td2. Three options are
`presented and discussed here: a single chip packagelPWB option, a laminate
`MCM option and a flip chip thin fIlm MCM option.
`If the CPU is packaged in a PGA, N2 is typically limited to 32 bits to 128
`bits, to limit the PGA pin count, and td2 might be as large as 23.1 ns. (Delays
`used here are based on the evaluations provided in reference [17].) This option
`provides the worst (though not bad) performance at the least cost.
`The simplest MCM alternative is to package the CPU chip(s) as bare die on
`a fIne pitch laminate MCM, either with TABor wire bonded chip attach, and
`then connect the memories as single chip packages. This reduces the fanout and
`CPU footprint, decreasing td2 and allowing for a modest increase in Nl. The
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`
`EXAMPLE OF THE SYSTEM DESIGN PROCESS 127
`
`memories are left in their single chip packages because their footprint is barely
`larger than that of the bare die (they only require 20 or so pins). This also
`td2 is decreased from 23.1 ns to 17.9 ns, a 5.2 ns
`simplifies memory testing.
`decrease. With the increased interconnect density it is possible to increase Nl
`to 128 bits or more. Based on assumptions beyond the scope of this text, a
`computation performance increase of around 11 % is gained over the single chip
`package option.
`With this laminate, the impact of thermal considerations is likely to be low.
`Thermal vias are used beneath the CPU but, if the chip is designed so that few
`signals run underneath this chip, then the impact on interconnection capacity is
`small. Manufacturing costs are low, possibly lower than the cost of using
`In
`ceramic PGAs on a PWB, and the manufacturability cost also is low.
`particular, the memory chips are easy to rework. It also might be possible to
`avoid reworking the CPU if it is a single die. The CPU can be tested after
`mounting it on the laminate, before mounting the memories, and scrapped with
`the low cost laminate if it fails. Other cost impacts also can be kept low.
`Sealing the bare chips in epoxy delivers sufficient environmental sealing at a low
`cost, and adequate mounting to the next level of packaging is through an
`standard edge connector. Overall, the price premium over the conventional
`option is small.
`The most aggressive MCM alternative, in terms of performance, is to use
`flip chip solder bumps on a thin film MCM. With this approach, N2 can be very
`high and the shortest possible interconnection delay, short of using some tbree(cid:173)
`dimensional technology, can be obtained. Then td2 is decreased further 3.1 ns
`delay over the laminate approach when the memories are packed in short lead
`TAB frames and mounted on a thin film substrate [17]. The fetch size, N2, can
`be substantial, possibly even 512 bits or more. The overall computation
`performance increase over the single chip package option is about 20%.
`The price premium is several hundred dollars however, and the risk of
`delayed time-to-market moderate unless close relationships had been established
`with parts suppliers and a carefully worked out test plan is used. If a silicon
`substrate is used, the cost of the package (typically a large ceramic PGA) can be
`higher than the substrate itself, possibly even $200 to $300. Manufacturability
`costs are higher as all the difficulties of working with bare die must be
`incorporated. An offsetting factor is that solder bump technology is the easiest
`bare die attach technology with which to do rework. If there is insufficient
`experience with flip chip thin film MCMs in the company, the risk and time-to(cid:173)
`market impacts might be high. These considerations should be balanced against
`the performance gains.
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`128 PACKAGE SELECTION: A SYSTEMS NEED PERSPECIIVE
`
`3.11
`
`SUMMARY
`
`System design may be driven primarily by performance, by cost or by the desire
`to maximize the ratio of performance to cost. Due to continuing rapid advances
`in chip technology, as well as advances in customer's needs, the lowest cost
`packaging alternative often does not return satisfactory performance. This has
`led to a growing need for advanced, customized packaging. MCM technology
`represents the high performance end of advanced packaging technology.
`The use of MCMs leads to improved system performance through the ability
`to pack the chips close together. This ability arises from the tight line and via
`pitches possible with MCM technology. These tight pitches reduce the impact
`of chip fanout on chip footprint, and results in sufficient interconnect capacity
`being available in a small area. This ability results in a reduction in interchip
`delay as compared with the conventional package alternatives. The reduction in
`delay is largest if the chips being packaged have high pin counts, as such high
`pin counts normally require a large fanout package and create a strong demand
`for wiring. For example, the size difference between a multiple 500 pin PGA
`mounted microprocessor array and the equivalent MCM mounted array is large,
`while the size difference between a surface mount packaged memory array and
`the equivalent MCM mounted array is small.
`In the former case, if system
`performance is very dependent on reducing interchip delays, the performance
`advantages of using MCMs are large. A further gain in performance comes
`about because the MCM-based solution fits onto fewer PWBs, reducing the need
`for higher levels of packaging in the packaging hierarchy. This allows the parts
`of the system to be more richly interconnected. The advantage is greatest with
`thin film MCMs, least with laminate MCMs. In all cases, however, the use of
`MCMs reduces size, weight and interconnect delays, and increases the total
`number of connections available.
`The above discussion applies to the use of both large and small « 10 chip)
`MCMs. Sometimes an alternative to a small MCM is to fabricate a single large
`ASIC chip. This is reasonable if the chip can be produced with sufficiently high
`yield. However, it is unreasonable if the production volume is too small to
`justify the extra design cost, if the time-to-market requirements are too short to
`justify the extra design time or if different semiconductor technologies have to
`be integrated.
`There are a number of potential disadvantages to using an MCM solution.
`The heat density is higher, possibly requiring a more expensive heat dissipation
`solution. The manufacturing cost is likely to be higher, more so for thin mm
`and high layer count coflfed MCMs than for laminate MCMs. The test cost
`almost certainly is higher when bare die are packaged on MCMs rather than in
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`
`SUMMARY 129
`
`easily tested, single chip packages. At the time of writing the risk of increased
`time-to-market is also greater with a bare die MCM solution due mostly to some
`infrastructure deficiencies. However, the infrastructure situation is improving
`rapidly.
`Thus, the engineer must select the most appropriate technology mix for each
`system. This must be done by evaluating different packaging and partitioning
`alternatives against the system cost and performance goals. This is best done
`through the use of clearly identified cost and performance factors. For an
`advanced system, a large number of alternative courses of action should be
`generated, evaluated and compared using suitably detailed models and
`simulations. Only then can it be determined if the extra cost of advanced
`packaging can be justified by the system's needs. This process also enables the
`designer to determine which functional blocks in the system benefits most from
`the use of advanced packaging. As a general rule, the most highly connected
`functional blocks tend to benefit more from advanced packaging than lowly
`connected functional blocks, such as memories.
`A somewhat idealized approach has been presented in which the system's
`cost and performance aims are clear and can be modeled numerically, as can the
`performance and cost of the different options. Unfortunately, this is not always
`the case. The customer's requirements might be vague and ill formed. In this
`case, scalability and flexibility of the solution becomes an important factor.
`Also, all of the models needed to do the evaluation might not exist. Quantifying
`time-to-market and test costs might be difficult. Nevertheless, by qualitatively
`understanding how the different performance and cost factors relate packaging
`alternatives to the systems aims, it is still possible to arrive at a sensible solution.
`
`Acknowledgments
`
`First, the author would like to take this opportunity to thank his co-editor, Dr.
`Daryl Ann Doane for her contributions to this book. In particular, I thank her
`for technical, organizational and editorial contributions to this chapter and to all
`of the other chapters in this book (all of which we edited as a team). Many of
`the concepts original to this book came about through long and detailed
`discussions between the two of us. It appears to be a result of extremely good
`fortune, rather than good planning, that our respective technical backgrounds and
`skills complemented each other to the point where this book is more than two
`times better than it would have been if either of us had done it alone.
`With regard to this chapter, the author also thanks Bob Evans, Tom Gray,
`David LaPotin, Steven Lipa, Sharad Mehrotra, Slobodan Simovich, Douglas
`Thomae and the anonymous reviewers for their comments.
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`130 PACKAGE SELECTION: A SYSTEMS NEED PERSPECTIVE
`
`References
`
`6
`
`8
`
`9
`
`H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, New York:
`Addison Wesley, 1990.
`2 D. Balderes, M. L. White, "Large General Purpose and Super-computing Packaging,"
`R. R. Tummala, E. J. Rymaszewski, eds., Microelectronics Packaging Handbook,
`New York: Van Nostrand Reinhold, 1989, Chap. 16.
`3 W. H. Knausenberger, L. W. Schaper, "Interconnection Costs of Various
`Substrates-The Myth of Cheap Wire," IEEE Trans CHMT, vol. CHMT-7, pp. 261-
`267, Sept. 1984.
`4 W. R. Heller, W. F Mikhail, "Packaging Wiring and Terminals," R. R. Tummala, E.
`J. Rymaszewski, eds., Microelectronics Packaging Handbook, New York: Van
`Nostrand Reinhold, 1989, Chap. 2.
`5 C. E. Bancroft, "Design for Assembly and Manufacture," Electronics Materials
`Handbook, Vol. 1: Packaging, Materials Park OH: ASM International, 1990, pp. 119-
`126.
`J. L. Hennessy, "Trends in Processor and System Design and the Interaction with
`Advanced Packaging," Proc. IEEE-MCMC Multichip Module Conj, (Santa Cruz,
`CA) pp. 1-3, March 1992.
`7 R. Miracky, et al., "Rapid Prototyping of Multichip Modules," Proc. IEEE-MCMC
`Multichip Module Conj, (Santa Cruz, CA), pp. 163-167, March 1992.
`L. L. Moresco, "Electronic System Packaging: The Search for Manufacturing the
`Optimum in a Sea of Constraints," IEEE Trans CHMT, vol. CHMT-13, no. 3, pp.
`494-508, Sept. 1990.
`J. P. Krusius, System Interconnection of High Density Multichip Modules," Proc.
`Internat. Symp. on Advances in Interconnections and Packaging, (Boston, MA), SPIE
`vol. 1390, pp. 202-213, Nov. 1990.
`10 P. Sandborn, "A Tool for Evaluating Performance and Technology Tradeoffs in
`Integrated Circuit Packaging," Proc. NEPCON-East, (Boston, MA) pp. 569-576, June
`1991.
`11 D. P. LaPotin, "Early Analysis of Multichip Modules," Proc 1990 IEPS Internat.
`Electr. Packaging Symp., (Marlboro, MA), pp. 557-563, Sept. 1990.
`12 P. D. Franzon, et al., "Tools to Aid in Wiring Rule Generation for High Speed
`Interconnects," Proc IEEE and A CM Design Automation Conj, (Anaheim, CA), pp.
`446-471, June 1992.
`13 1. L. Hennessy, D. A. Patterson, Computer Architecture, A Quantitative Approach,
`San Mateo CA: Morgan Kauffman, 1990.
`14 S. Przybylski, Cache and Memory Hierarchy Design, San Mateo CA: Morgan
`Kauffman, 1990.
`J. D. Roberts, W. M. Dai, "Early System Analysis of Cache Performance for RISC
`systems," Proc. IEEE-MCMC Multichip Module Conj, (Santa Cruz, CA), pp. 130-
`133, Mar. 1992.
`16 W. M. Su, "MCM and Monolithic VLSI Perspectives Ion Dependencies, Integration,
`Performance and Economics," Proc. IEEE Multichip Module Conj, (Santa Cruz,CA),
`pp. 4-7, Mar 1992.
`17 J. Shiao, D, Nguyen, "Performance Modeling of a Cache System with Three
`
`15
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`
`Interconnect Technologies: Cyanate Ester PCB, Chip-on-Board and CUIPI MCM,"
`Proc. IEEE Multichip Module Conj., (Santa Cruz, CA), pp. 134-137, Mar. 1992.
`18 G. Messner, "Cost-density Analysis of Interconnections," IEEE Trans. CHMT, vol
`CHMT-lO, no. 2, pp. 143-151, June 1987.
`
`SUMMARY 131
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`4
`
`MCM PACKAGE SELECTION:
`COST ISSUES
`
`Lee Hong Ng
`
`4.1 INTRODUCTION
`
`In the design of electronics packaging systems, there is rarely a single "best"
`solution; the fmal design is usually a tradeoff between different performance
`attributes (system speed, thermal constraints or size) and cost. In many cases,
`tradeoffs between cost and perfOlmance are the most important. Unfortunately,
`the analysis of cost and performance tradeoffs is a very complex task. On the
`performance end, the vast variety of design options available today to the
`packaging engineer precludes an exhaustive analysis of all viable alternatives.
`On the cost end, the treatment usually is even more cursory because of the
`complexity and uncertainty of cost before actual production.
`While many may argue that performance analysis is more important in the
`design phase, one must be aware that cost is very dependent on the product
`design. In fact, up to 80% of the cost of a product is determined in the design
`phase [1]. If a design decision is based primarily on performance, one may
`discover, after the decision is made, that a slight modification might have
`lowered the cost drastically without an appreciable degradation in performance.
`Obviously, both cost and performance issues must be addressed at the design
`phase to minimize sub-optimization. The designer must be able to think across
`the boundaries of different packaging approaches to optimize cost and
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`134 MCM PACKAGE SELECTION: COST ISSUES
`
`performance for a specific design. In the previous chapter, cost was divided into
`four factors: production cost, post production cost (reliability, repair and
`maintainability), design and prototyping cost and time to market cost impacts.
`In this chapter, details about how to model production cost and examples of the
`cost considerations of all of these cost factors are given. Sections 4.2 to 4.5
`present technical cost modeling (TCM) and its application to making cost-based
`decisions for MCMs and PWBs. The cost modeling approach presented in these
`sections is a process-based cost model. Section 4.6 discusses an alternative form
`of cost modeling used by a design bureau when it does not have access to
`manufacturing process information but does have access to vendor pricing
`information. This model is referred to as a design activity-based cost model.
`
`4.1.1 The Importance of Cost
`
`Product costing is important for strategic decisions, cost and performance
`evaluation, product pricing and product design, as well as to improve and
`manage existing operations. For example, product cost information is used by
`management to decide which products the company should drop to be more
`profitable, or it may be used to formulate a strategy for the company based upon
`its cost advantages in certain products.
`If the product cost information is
`inaccurate or biased, insensible decisions may result.
`Product costing also is important in material and process selection, as well
`as to target areas for cost improvement and optimization. A consistent product
`costing framework also can be used to assess the cost position of suppliers,
`competitors and customers, and to evaluate "make versus buy" decisions.
`Accurate product costing is especially important at the design phase where
`more than 80% of the cost of a product is determined. To be useful, cost
`evaluation at the design phase must incorporate the effects of design and
`manufacturing processes. This ensures that the design offering the optimum
`combination of cost and performance is selected.
`In many cases, process
`selection decisions also are made at the same time using product costing
`information. Thus, errors in product costing at this stage results in non-optimum
`designs being selected.
`In many applications, the direct manufacturing cost is only a small part of
`the total system costs. The total system costs include operational cost such as
`fuel and power consumption, cost of cooling, prototype design and testing, repair
`and higher level connections. Again, all of these must be included in the cost
`analysis to minimize sub-optimization at the system level.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 163
`
`

`
`INTRODUCfION 135
`
`Table 4-1 Example of Equations for Traditional Cost Estimation.
`
`Cost = Materials + Labor Cost· (1 + BURDEN) + Tooling
`
`t
`. I C
`M t
`a ena os =
`
`Part Weight· Material Price
`(1 _ Scrap)
`
`Labor Cost = Cycle Time· Labor Wage
`
`BURDEN = Other Costs (Depreciation, Energy, Indirect CostS)
`
`Tooling = Cost of Tooling and Setup
`
`4.2 TECHNIQUES FOR COST ANALYSIS
`
`There are many methods available today to analyze the cost of products. They
`are broadly categorized into three methods: traditional cost analysis, activity(cid:173)
`based cost analysis and technical cost modeling.
`
`4.2.1 Traditional Cost Analysis
`
`Traditionally, the task of cost analysis has been delegated to accountants, who
`are more familiar with the financial rather than the manufacturing aspect of a
`product. Traditional cost accounting systems, invented in the early 1900s,
`typically calculate the cost of a product based upon the labor content required for
`the product Burden or overhead then is added to the product as a percentage of
`direct labor (or touch labor). Table 4-1 shows an example of the equations used
`in traditional cost estimation, and Table 4-2 shows an example of how burden
`or overhead rate is estimated [2].
`In multi-step operations, the cost of a product is the sum of all the unit
`operations, each of which is estimated from the labor hours and materials
`required, adjusted by yield. Table 4-3 shows an example of the traditional cost
`analysis as applied to the assembly of a MCM [3].
`In Table 4-3, the total
`material cost per module is $4,214.84 and total labor hour is 10.66 hours.
`ASSuming that the overhead is 500% of direct labor cost of $121hr, the total
`variable cost per module is $4,854 ($4,214.84 + 10.66 x $12 x 500%).
`Traditional cost analysis works well when labor cost is the most influential
`cost driver. As manufacturing becomes more complex and automated, labor cost
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 164
`
`

`
`136 MCM PACKAGE SELECTION: COST ISSUES
`
`Table 4-2 Variable Burden Calculation.
`
`General Ledger
`#
`Qale
`Mat~rial~ Lallor En~rg}:
`!t~m
`1 Memory Chips
`1/1/90 II $200,000
`2 National Electric
`1/1/90 II
`3
`Resistors
`1/5/90 II $30,000
`Circuit Boards 1/10/90 II $90,000
`4
`5 National Electric 1/15/90 II
`6 Monthly Salaries 1/31/90 II
`7
`FlCA Payment 1/31/90 II
`
`$50,000
`~!l,OQQ
`$320,000 $56,000 $11,000
`
`$5,000
`
`$6,000
`
`Monthly Costs
`($000l
`(%l
`
`Direct Costs
`Materials
`Direct Labor
`Energy
`Depreciation Costs
`Equipment
`Building s
`
`$320
`$56
`$11
`
`60.2%
`10.5%
`2.1%
`
`$108
`
`20.3%
`7.Q:&
`~7
`$532 100.0%
`
`Variable Burden = "Other Costs" ($11 +$1 08+$37) I Labor Cost ($56) = 279%
`
`Table 4-3 Traditional Cost Analysis for Assembly of MCMs.
`
`Assumptions
`
`Glue Logic Die lModule
`VLSI DieIModule
`Sub. Test Socket Cost
`Good Die NLSI Wafer
`
`29
`12
`300
`40
`
`Task
`Attach Glue Logic
`Wirebond Glue logic
`Logic TesVRepair
`Passives Attach
`Attach VLSI Devices
`Wirebond VLSI Devices
`VLSI TesVRepair
`Scrap
`
`Substr